JPH0218673A - Inspecting device for test facilitating design rule - Google Patents

Abstract

PURPOSE:To inspect a scan design rule with higher accuracy by defining terminal polarity in addition to the terminal attribute and checking a test facilitating design rule by means of the attributes of the inverted and non-inverted signals. CONSTITUTION:The title device is provided with a means 103 which compiles the connection data on a logic circuit, which a linker 106 which carries out the hierarchical evolution of the logic circuit up to a primitive gate except a non-evolved module, and a means 102 which allocates the terminal attribute and the terminal polarity. Further, a means 11 is provided to produce the inverted and non-inverted signal attributes which are transmitted to the inside of the logic circuit from an input terminal and transmits these signal attributes while checking a test facilitating design rule via an event driving system or a compiling system. Furthermore a means 113 which decides the violation and analyzes the result based on the transmitting results of said signal attributes, the terminal attribute/polarity and the test facilitating design rule is provided. As a result, the terminal polarity is defined in addition to the terminal attribute and the test facilitating design rule can be inspected with higher accuracy and at a high speed with use of the attributes of inverted and non-inverted signals.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to a method for verifying testability design rules for digital logic circuits, and in particular, to a testability design rule verification method for checking the possibility of scan testing. The present invention relates to a verification device for design rules.

(Prior Art) In recent years, when designing large-scale logic circuits, it has become extremely difficult to create test vectors with a high fault coverage. For this reason, a design method is used that takes testing into consideration from the stage of designing a logic circuit. Among them, the scan design method is suitable for random logic circuits (circuits consisting of memory elements such as multiple gates and flip-flops).
It is well known as a testability design method.

In the scan design method, instead of ordinary flip-flops (hereinafter referred to as F/Fs) and latches, logic is designed using F/Fs and latches that have the same functions and also have a scan function. Then, by connecting the FZFs and latches with a scan path to configure a shift register,
The sequential circuit can be divided into the shift register and the remaining combinational circuits.

Furthermore, the shift register can be treated as if it were an external input/output terminal of a combinational circuit, and the state values inside the circuit can be scanned.

In a circuit designed in this way, test patterns can be generated by considering the 8-part combination circuit, and test patterns can be generated by an algorithm, and automatic test pattern generation systems have already been put into practical use.

However, setting M-1:? 5, it is necessary to perform scan design while observing complicated design rules. The following four design rules can be cited as rough scan design rules.

(1) There is no loop circuit consisting of gates in the circuit.

(2) The system clock must be controllable by an external input terminal.

(3) It must be possible to scan F/F or latch.

(4) Asynchronous signals can be controlled externally using mode signals.

The circuit must satisfy the following two design rules, and since the rules themselves are complicated, there is a risk that artificial bugs may be introduced into the circuit.

Generally, in the case of logic LSI design R-1, layout design π-1 is progressing at the same time as test design, and if a design rule violation is discovered during test generation, the logical connection description is revised. It is not possible to do so, and requires a lot of work such as changing circuit button data. Furthermore, once the process has progressed to the die sorting process, a serious situation arises in which circuit changes cannot be made. In other words, test patterns that could normally be generated are
A problem occurs that cannot occur in an actual circuit.

Conventionally, as a method for checking scan design rules, (a
) “Automatjc Checking of L
ogicDesign 5structures for
Compliance with Testabili
ty Ground Rules, Proc, 14
thDesign Automation Confe
rence, pp, 4fi9-478June 19
77 have been announced. (b) [Logic design rule verification method for large-scale logic circuits] Information Processing Society of Japan Research Report 8
7i) Δ-36 has been announced.

In method (a), the logic circuit is expanded to primitive gates such as AND and OR, and in addition to normal logic simulation, calculations are performed using a method called a behavior model instead of the gate calculations performed in normal logic simulation. Logical values “0” and “1” and tarok propagation value ゛′c
Design rule verification is performed by propagating one scan data propagation value.

In method (b), lower modules are made into black boxes and symbols (signal attributes) are used for propagated signals so that design rule verification can be performed even for circuits designed top-down or bottom-up. . The symbol (terminal attribute) assigned to the external input terminal is propagated from the input terminal to the internal circuit as a signal attribute, and the constraint signal value set (a collection of signal attributes that must not be propagated) is assigned to the input terminal of the black box module. Design rule checks are performed by making exclusive comparisons with

In method (a), it is necessary to propagate "0" and "1" signals to the internal circuit, so when designing from the top down, "0" and "'1" signals must be sent to the input/output terminals of undesigned modules.
"Design rule checking is impossible because it is only possible to set the expected value of the signal. Also, in method (b), as the number of terminal attributes increases, the number of signal attributes that make up the constraint signal value set increases. There is a risk that the number of checks will increase, the checking method will become complicated, and the processing time required to implement the check will increase.

Furthermore, both methods (a) and (b) have a problem in that they cannot be checked in consideration of the polarity of the input terminal because the signal attribute does not include the inversion attribute.

(Problem to be solved by the invention) In this way, in the conventional technology, scan design rule verification is performed by symbol propagation without considering inverted signals, so inversion of signal attributes is ignored in inversion gates such as NAND and NOR. from the external input terminal to the F/F in the circuit.
It was inaccurate to determine whether the device was controlled or latched. Another problem was that the verification system itself had to be changed every time a design rule was changed or a signal attribute was added.

The present invention has been made in consideration of the above circumstances, and its purpose is to be able to perform more accurate scan design rule verification using inverted signal attributes, and to be flexible in changing design rules. It is an object of the present invention to provide a testability design rule verification device that can cope with the problem, optimize a design rule verification system, and quickly realize old rule verification.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to define terminal polarity in addition to terminal attributes, and to create more accurate testability design rules using inverted signal attributes and non-inverted signal attributes. The purpose is to check.

That is, the present invention provides a testability design rule verification apparatus that hierarchically performs testability design rule verification of a logic circuit hierarchically designed in a top-down or bottom-up manner. and a linking process for hierarchically expanding the logic circuit to primitive gates, excluding non-expanding modules (flip-flop latches, uninstalled old modules, already designed modules, etc.), based on the data compiled by the means. means for assigning terminal attributes and terminal polarities to the input/output terminals of the non-deployable module and the external input/output terminals of the top module, respectively; means for creating inverted and non-inverted signal attributes propagated from the logic circuit into the inside of the logic circuit; means for propagating the signal attributes created by the means using an event-driven method or a compilation method; means for propagating the signal attribute while checking the testability design rules according to the propagation characteristics of the non-deployable module, and determining a violation based on the propagation results of the signal attributes, terminal attributes, terminal polarity, and the testability design rules. and means for analyzing the results.

In addition to this, the present invention provides means for reading and compiling testability design rules specified by master and user, and automatically generating a signal attribute propagation system and a result analysis system.

(Function) Assign terminal attributes and terminal polarities to modules of the same type that are not expanded, and then, when expanding the hierarchy, associate the terminal attributes and terminal polarities listed above to the nets connected to the input terminals of the non-expanded modules. , it is possible to check old and new rules at the same time as signal attribute propagation.

The signal attribute propagation means creates a signal attribute from the terminal attribute and terminal polarity assigned to the external input terminal, and propagates the signal attribute from the external input terminal into the circuit. The propagation characteristic calculation unit of the primitive gate and non-expanding module has already assigned a determination as to whether the testability design rule is violated to the signal attribute propagating to the input terminal of the gate and the non-expanding module. This is done by creating an expected signal attribute from the terminal attribute and terminal polarity, and comparing the two.

On the other hand, the output terminal of the gate propagates the result of the propagation characteristic calculation, and the output terminal of the non-expansion module propagates the signal attribute created from the terminal attribute and terminal polarity divided into the output terminals. ]0 At the same time, regarding the signal attributes propagated to the external output terminals, expected signal attributes are created from the already assigned terminal attributes and terminal polarities, and a check is made to see which ones are correct. The result analysis means indicates the locations where the testability design rules are violated using hierarchically displayed net names, and points out the violating design rule items.

You can also input your own testability design rules to optimize the signal attribute propagation system and results analysis system to validate your specific design rules.

(Example) First, testability design rules handled by the present invention will be described. In the section (Conventional example), it was mentioned that there are four design rules, but these can be further specified as follows.

■ Only F/F and latches are allowed for memory elements in the circuit, and RS latches consisting of gate loop circuits are not allowed.

■ System clock, system set, and system reset signals are provided via external input terminals. Must be able to be turned off.

■ It is not allowed to use logic between clocks.

■ The scan register must be configured correctly on the scan path, and the scan clock must be propagated directly from the external input terminal to the scan clock input terminal of the scan F/F and scan latch.

■ The asynchronous signal must be able to be turned off using an externally input mode signal.

Since the verification method for design rule (3) was not performed using the method of the present invention, the design rules (2) to (4) will be referred to as test packaging design rules in the following examples.

FIG. 1 shows a system configuration of a testability design rule verification device according to an embodiment of the present invention. In the figure, 101 is a connection description of a hierarchically logically designed circuit, 102 is the name of an uninstalled module or an existing module in the connection description (101), the input/output terminal name of the module, 5 the top module name, and the external Input/output terminal names and input/output terminals of these modules] 2 This is a file that stores terminal attributes and terminal polarities to be assigned to children (terminal attributes and terminal polarities will be described later). 103 is a compiler that checks the syntax of the logical connection description (101), converts the circuit data, and inputs the above-mentioned terminal attributes and terminal polarities (1, 02); 104 converts the circuit connection data, terminal attributes, and terminal polarities for each layer; This is a logical connection information database stored in . Reference numeral 105 is a cell library database that stores primitive gates that realize the functions of cells that are constituent elements of the logical connection description (101), terminal attributes, terminal polarities, etc. of the cells. 10
6 is a linker that links the logical connection information database (104) and the cell library database (105) and performs hierarchical expansion processing; 107 is connection data after hierarchical expansion.

This is a logic design database that stores terminal attributes and terminal polarities.

110 indicates a testability design rule verification system. IH is a signal attribute propagation processing unit that reads connection data, terminal attributes, and terminal polarity from the logic design database (+07) to create signal attributes, and also assigns expected signal attributes to the input terminals and external output terminals of non-expandable modules. Create and assign. Then, the signal attributes are propagated from the external input terminal to the entire circuit, and a design rule check is performed. l 1.2
is a file that stores the propagation results of the above signal attributes, and 11
3 is the propagation result file (11, 2), logical design database (1, 07), and testability design rule (114)
This is the part that analyzes the results. Reference numeral 115 is a file that stores locations that violate testability design rules and items of the design rules. This file becomes the input for the scanning circuit automatic conversion system.

FIG. 2 shows a system that automatically generates and edits the two systems (1, 11, 113) that perform the testability design rule check described above. 201 is a mask design rule that describes a design rule that can be handled by the testability design rule verification system (110), 202 is a user design rule that describes a testability design rule specified by the user, and 203 is a mask design rule that describes a testability design rule that can be handled by the testability design rule verification system (110). ) compiler. 204 is a design rule object that stores design rule check items, 205 is a source program that manages the creation and propagation of signal attributes, and 206 is a source program that is the backbone of the result analysis system.
2o7 is a part that generates, compiles, and edits a signal attribute characteristic calculation routine and a signal attribute violation determination routine. 208 is a load module of the signal attribute propagation system, and 209 is a load module of the result analysis system.

Before explaining the processing flow of the present invention, terminal attributes, terminal polarity, and signal attributes will be explained.

The terminal attributes are shown in FIG. 3(a). D represents a normal pig. Ca is the system clock, STn is the preset, R
S n represents reset. S D n indicates scan data, Au indicates scan clock, and A1B +1 indicates scan clock B. Further, if the terminal attributes of an undesigned module are not determined, a combined terminal attribute such as DSDn (combined use of normal data and scan data) is allowed. n is a phase number for determining whether a signal attribute is propagated from a different external input terminal.

] 5. Assign the terminal polarity to the system clock, preset reset clock B, etc. whose On/Off operation is controlled by the polarity of the signal. For example, mark "10" for those that turn on at 1", mark -" for those that turn on at 90", and mark "x" for those that do not matter.

The terminal attribute, terminal polarity, or input/output terminal is identified by another method.

Next, signal attributes will be explained using FIG. 3(b).

The signal attribute is created using the terminal attribute and terminal polarity, and is set to the external input terminal or the output terminal of the non-deployable module.

Normal data is D, but in actual logic it is either "0" or "1"
Take either. The scan data is S D a, and the actual logic is "0" or "1".

The system clock is C rl, which is created from the terminal attribute Cn and the terminal polarity (meaning signal polarity here) "10", and indicates a positive pulse. Similarly, system set is STn, system reset] 6 is R S n % scan clock A is A IL %
Scan clock B is 811. Further, a mode signal for asynchronous control is indicated as IH.

The inverted system clock CNa indicates that it is a negative pulse created from the terminal attribute Cm and the terminal polarity -. Similarly, the inversion system set is S T
N n % inversion system reset is R S N rL,
The inverted scan clock A can be expressed as A N rL, the inverted scan clock B can be expressed as B N n , and the inverted mode signal can be expressed as IHN. n is a phase number indicating propagation from different external input terminals.

In addition, (1) DD level signal is H, GND level signal is L1, undefined signal attribute is defined as X1 prohibited (signal indicating that a design rule violation has occurred) is defined as E.

Next, calculation of propagation characteristics of signal attributes will be explained in reference to testability design rules. Figure 4 shows a propagation characteristic table. FIG. 4(a) is a characteristic table of AND and OR gates used for system clock propagation check. This table shows the output results for a two-man powered gate.

The upper right half is the output result of the AND key 1, and the lower left half is the output result of the OR gate. m and n represent the phase numbers, and when m = n, it represents the characteristic calculation of the signal attributes of the same phase number, m *
In the case of n, it is a characteristic calculation of signal attributes in different cases.

In both AND and OR gates, calculations between clocks are prohibited. This is a testability design rule.
Indicates that logic between clocks is not allowed.

Although FIG. 4(a) shows the result for two-manpower, the result of this table can be expanded to calculate the characteristics of input signal attributes even if three or more manpower is required.

FIG. 4(b) shows a characteristic calculation table for NOT Kate.

Outputs for human signal attributes other than data "D" and indefinite attribute "X" have inverted attributes.

On the other hand, for NAND and NOR gates, the output signal attribute is the inversion of the AND and OR results. The exclusive logic OR and NOR characteristic calculation table can also be obtained by combining the above-mentioned gate characteristic calculations. A characteristic calculation table can be written for the tristate case in the same way.

Above, we have described how to calculate the propagation characteristics of signal attributes for system clock checks [design rules for testability ■ and ■]. The propagation characteristics of the signal attributes used in the check [Test package design rules ■] can be considered in a similar way.

In calculating the propagation characteristics of signal attributes, the signal attributes are propagated while checking the design rules. With this method, it is possible to check signal attributes that should not be based on logic. In addition, for the propagation of signal attributes, an event-driven method is used in which two-dimensional propagation characteristic calculations are performed and signal attributes that have occurred are propagated.

Here, the event-driven method is a method in which a logical operation is performed only on the element where the input signal has changed, and the simulation is executed while propagating the result to the output light element. In addition, instead of the event-driven method, a simulation load module is created using the Reherso-1-L compiler and a logic circuit model is created for each element from atomic power (input terminal of the circuit) to atomic output. It is also possible to use a compilation method that executes

5 and 6 do not show the processing flow of the testability design rule verification system shown at (1, 10) in FIG. 1. FIG. 5 is a flowchart 1 showing the signal attribute propagation processing procedure. 501 and 510 are terminals, 502-50 [i and 5
08,509 C indicates processing, and 507 indicates judgment.

First, the process starts (501). Design database (1,
07), the circuit connection data, input/output terminals of non-deployable modules such as F/F latches, undesigned modules or existing needle modules, terminal attributes and terminal polarities of external terminals are read out (502). Next, an expected signal attribute is created from the input terminal attribute and terminal polarity of the non-expansion module, and from the external output terminal attribute and terminal polarity (503). Furthermore, signal attributes are created from the terminal attributes and terminal polarities assigned to the external input terminals (504). However, processing (50
The order of 3) and processing (504) may be reversed. If we call the equipotential wiring that connects gates a node,
Initial values are set for nodes throughout the circuit (505).

The signal attributes created in the process (504) are propagated into the circuit from the external input terminal (50G).

When the signal attribute reaches each gate that makes up the circuit or the input terminal of a non-expandable module, the signal attribute is determined according to the propagation characteristics of each gate, while in the case of a non-expandable module, the signal attribute is determined from the terminal attribute and terminal polarity assigned to the output terminal. to propagate signal attributes from the output port. At the same time, a design rule check is performed using propagation characteristic calculations. Further, a design rule check is performed by comparing the expected signal attributes of the input terminal of the non-expanded module with the signal attributes propagated to the input terminal. Similarly, for external output terminals, a design rule check is performed by comparing propagated signal attributes and expected signal attributes. Next, repeat the process of (50B) until the signal attributes are determined for all notes (507).
), once determined, display the attribution of the signal propagated to the input terminal and external output terminal of the non-deployment module 508), output a result file containing the determined values of the signal attributes of all notes 509), and perform the series of processing. (510).

FIG. 6 shows the processing flow of result analysis. First, processing is started (801.). Similar to the signal attribute propagation check, connection data, terminal attributes, and terminal polarity are read out from the configuration 1 database (1, 07) (602), and expected signal attributes are created (803). Then, the result file output by the signal attribute propagation check is read (604).

Read the testability design rule object (204) specified by the user ((i05). Search for the node where the violating signal attribute is stored, and determine what signal attribute is present at the input of the gate that has the node as an output. Check whether the signal has propagated (coe).Similarly, the expected signal attribute of the input terminal of the non-deployment module is compared with the signal attribute of the node connected to the input terminal to determine a violation (GO7).

Furthermore, the same violation determination as in (807) is made for the external output terminal (608). For the violation location, the corresponding node F name is displayed in a hierarchical manner, and the identification name of the gate or non-deployment module inputting the note, the terminal attributes and terminal polarity that the input terminal has, and the information that has been propagated. Display signal attributes (609). The type of design rule that is being violated can be determined from the propagation signal attributes, expected signal attributes, violation gate or module identification name that provides information about the violation location, and the design rule information read in (605). (61,0). The data on the violation location and the violation rule data are output to a file (611), and the processing flow ends (612). In addition, the signal attribute propagation check and result analysis processing described above are
It is easy to perform continuous processing without dividing it into separate parts.

Finally, we will explain how to check testability design rules using a simple logic circuit as an example.

FIG. 7 shows how system clock signal attributes are propagated. FIG. 7(a) shows how the system clock signal attribute is propagated from the external input terminal.

701 to 704 are external input terminals, 705 to 707 are manual drivers, and 708 is an inverting input driver.

709 and 710 are NOR gates, 711 is NAND
In the gate, 712 is F/F. F/F (71
2) "D""C" indicates the terminal attribute. Also, "'+" indicates the terminal polarity. External input terminal (70
1) The clock signal attribute "C1" propagating from F/
It is input to the data input terminal of F (712).

This is an example of a violation of the design rule that ``the system clock must not be propagated to input terminals other than those having the clock input terminal attribute.'' External input (7
The clock signal attribute "C2" propagated from the gate (71, 1) is inverted at the gate (71, 1), further inverted at the gate (71, 0), and propagated to the input terminal having the terminal attribute "C".

Since the terminal attribute "C" does not care about the phase number, and the terminal polarity "10" assumes a positive signal as the expected attribute,
The signal attribute “C2” complies with the design rules.

FIG. 7(b) does not show propagation of asynchronous clock signal attributes.

713 and 714 are F/F, "D" and "C" in F/F
is a terminal attribute. D" is the terminal attribute of the Q output of the F/F. The attribute 'D-C' is propagated from the Q output of the previous F/F (713). The attached attribute "C1
is added to detect in-phase transfer violations between single latches. In the case of this figure, the first signal attribute “D” or F/
Since it is input to the input terminal attribute "C" of F (714), "as a general rule, the clock input terminal is
This violates the design rule that "signal attributes other than tsuku signal attributes must not be propagated."

FIG. 8 shows the propagation of scan signal attributes.

801 to 803 are external input terminals, 804 to 806 are input drivers, and 807 to 809 are scanning F/Fs. "SD", "A" and "B" in the scan F/F indicate the scan data terminal attribute, scan clock A terminal attribute, and scan clock B terminal attribute, respectively. “D”, “D”, “A”, and “B” on the signal lines in the circuit diagram indicate signal attributes. The signal attribute "D" is propagated to the input terminal with the attribute "SD" of the scan F/F (809), but this means that "no signal attributes other than the scan data signal attribute are propagated to the scan data input terminal." This violates the design rule that states that Also, check whether the signal attributes “B” and “A” are propagated to the input terminals having attributes “A” and “B” of the scan F/F (809), respectively. The input terminal of the scan clock signal has four attributes other than A (B).
This violates the design rule "Attribute No. 5 must not be propagated."

FIG. 9 shows the signal propagation of the asynchronous signal control system.

901 and 902 are F/Fs, and 903 is a NOR gate. °C” in F/F indicates the terminal attribute. Also,
"CI", "IH", "D-C", "IHN" on the signal wiring
” indicates the signal attribute. Now, the NOR gate (903
), as a result of the characteristic calculation of the first attribute "D" and "IHN" of "D-C,", the signal attribute "IH" is F / F (9
02) is propagated to the input terminal whose terminal attribute is "C". Since the terminal polarity of the input terminal is "'0", the logical value "
Set to 0 “off”. Therefore, “I” from the external input terminal
By propagating the HN” signal attribute, asynchronous clocks can be controlled.

As described above, according to this embodiment, terminal polarity can be defined in addition to terminal attributes, and more accurate testability design rule checks can be performed using inverted signal attributes and non-inverted signal attributes. Additionally, expected signal attributes created from terminal attributes and terminal polarities are assigned in association with connection data nodes, and design rules can be checked while performing characteristic calculations, resulting in high-speed processing. Additionally, it performs optimized design rule checks based on user-specific testability design rules, resulting in faster processing using minimal memory capacity. In addition, by outputting information about the design rule violation location and the type of violation design rule in the result analysis process, there is an advantage that an interface for automatic scanned circuit conversion can be realized.

Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to define terminal polarity in addition to terminal attributes, and it is possible to perform testing and facilitation design rule checks using inverted signal attributes and non-inverted signal attributes. This makes it possible to perform more accurate scan design rule verification, flexibly handle changes to old and old rules, and optimize the design rule verification system to speed up design rule verification. It is possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a system configuration of a testability rule verification device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a system configuration for automatically creating a characteristic calculation system and a violation determination system in the same embodiment. , Figure 3 is a diagram for explaining terminal attributes and signal attributes, Figure 4 is a diagram for explaining characteristic calculations, Figure 5 is a diagram showing the processing flow of the signal attribute propagation system, and Figure 6 is a diagram for explaining the results. A diagram showing the processing flow of the analysis system, FIG. 7 is a diagram showing the propagation of system clock signal attributes, FIG. 8 is a diagram showing the propagation of scan signal attributes, and FIG. 9 is a diagram showing the propagation of the scan signal attributes.
The figure is a diagram showing propagation of control signal attributes of an asynchronous signal. 101...Logic connection description, 102...Terminal attribute, terminal polarity, 103...Compiler, 104...Logic connection information pig base, 105...Cell library database, 10G linker-107...Logic design database, 110... Testability design rule verification system,] 11... Signal attribute propagation processing section, 113... Result analysis processing section, 207... Routine automatic generation, automatic editing processing section. Applicant's Representative Patent Attorney Takehiko Suzue System Diagram Diagram

Claims (2)

[Claims] (1) In a testability design rule verification device that hierarchically performs testability design rule verification of a hierarchically designed logic circuit, there is provided a means for compiling connection data of the logic circuit, and a means for compiling connection data of the logic circuit; based on the link processing means that hierarchically expands the logic circuit up to the primitive gate excluding non-expanded modules, and assigns terminal attributes and terminal polarities to the input/output terminals of the non-expanded modules and the external input/output terminals of the top module, respectively. means for creating inverted and non-inverted signal attributes propagated from the input terminal into the inside of the logic circuit using the terminal attributes and terminal polarity assigned to the external input terminal; means for propagating the signal attributes using an event-driven method or a compilation method; means for propagating the signal attributes while performing a testability design rule check according to the propagation characteristics of the primitive gate or non-expandable module; A testability design rule verification device comprising means for determining a violation and analyzing the results based on a propagation result of a signal attribute, a terminal attribute, a terminal polarity, and a testability design rule. (2) having means for automatically creating a system comprising a means for calculating the propagation characteristic of the primitive gate or non-deployable module and a system comprising a means for determining a violation based on testability design rules; 2. The testability design rule verification device according to claim 1.