JPH02186724A - Level detection circuit - Google Patents

Abstract

PURPOSE:To output an AC component with a linear characteristic without lowering the output level of the AC component when an antenna input level is low by inserting HPF between an amplifier and a level detection circuit in a post stage. CONSTITUTION:HPF 16 as a band limiting means is inserted between the output of the IF amplifier 7 in the final stage among IF amplifiers constituting an intermediate frequency amplifier, and the level detection circuit 14. The output of an adder 15 is outputted to an output terminal 18 through an output circuit 17 which executes DC level shift. Since the amplification factor of the intermediate frequency amplifier circuit goes to the product of the amplification factors of amplifiers in respective stages, the amplifier 7 with the high amplification factor firstly generates the output when the antenna input level gradually shifts from a low state to a high state. Next, an IF amplifier 6 in a preceding stage operates and the outputs are generated from the preceding stages in order. Thus, the AC component comes to the linear characteristic without lowering the output level of the AC component when the antenna input level is low, and a AC characteristic and an AC characteristic can be level-shifted to a high output-side through the output circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a level detection circuit in an intermediate frequency amplifier of a radio receiver, for example.

[Conventional technology]

An intermediate frequency amplifier in a radio receiver has a configuration in which differentially connected amplifier circuits for amplifying intermediate frequency signals are cascaded in multiple stages.

Then, the outputs of the intermediate frequency signals from each of the amplifier circuits are level-detected and added by an adder circuit, and the output is used as a drive output (S meter output) for a level meter or the like.

For example, in car radios, etc., in recent years, in order to obtain better reception conditions, a diversity reception method has been adopted, which prepares multiple reception antennas and automatically switches to the antenna that can receive better reception one after another. It has been reached.

In this case, the output of the S meter is often used to find an antenna that can provide better reception.

That is, FIG. 4 shows the conventional S meter output characteristics, where the horizontal axis shows the antenna input level and the vertical axis shows the output level.

In the figure, (a) shows the output characteristics of the DC component, and (b) shows the output characteristics of the AC component.

Here, the DC component shown in characteristic (a) is relatively linear with respect to the antenna input level, and the signal level display area is used as another control signal. On the other hand, in the above-mentioned diversity receiver, it is preferable to utilize the output of the AC component (noise component) shown in (b) in the figure, which occurs when the antenna input level is low.

[Means to solve the problem]

This AC component exhibits a characteristic that its output increases as the antenna input level decreases. However, when the antenna input level falls below a certain level, the output does not rise linearly, but drops again below a certain point, as shown in characteristic (b).

This occurs because some of the intermediate frequency amplification stages, which are connected in series in multiple stages, lose their operating bias due to the drop in the input antenna level and become saturated as no signals are carried.

Therefore, the AC characteristic output of the conventional level detection circuit has a problem that it is difficult to use it as a control output of a guivacity receiver.

[Problem to be solved by the invention]

The present invention has been made in view of the problems with the conventional level detection circuits described above, and it is an object of the present invention to provide a level detection circuit having a characteristic that the AC output increases more linearly when the antenna input level decreases. That is.

In order to solve the above problems, a level detection circuit according to the present invention includes an intermediate frequency amplification circuit which receives an intermediate frequency signal and has amplifiers connected in cascade in multiple stages to sequentially amplify this signal, and each of the amplifiers. a plurality of level detectors for detecting the level of each output, an adder for adding each output of the plurality of level detectors, at least a subsequent stage amplifier of the cascade-connected amplifiers forming the intermediate frequency amplification circuit, and the The feature is that a band-limiting filter is inserted between the level detector and the level detector.

[For production]

According to the above configuration, since there is a band-limiting filter between at least the downstream amplifier of the cascade-connected amplifiers and the level detector, the output level of the AC component does not decrease even when the antenna input is weak. , the output will be relatively linear. Therefore, the output of this AC component can be effectively used for antenna switching control of a diversity receiver, for example.

〔Example〕

Embodiments of the present invention will be described below based on the block diagram shown in FIG.

2 is an input terminal for an intermediate frequency signal, and 2 is a first-stage IF amplifier that amplifies the intermediate frequency signal applied to this input terminal.

A differential amplifier is normally used as this IF amplifier, and its output is further provided to the IF amplifier 3 at the next stage. Similarly I
F amplifiers 4 to 7 are sequentially connected in cascade to form an intermediate frequency amplification circuit with a total of six stages of IF amplifiers, and the final stage! It is configured such that the output of the F amplifier 7 is led out to an output terminal 8.

Each of the IF amplifiers 2 to 7 includes level detectors 9 to 7 that receive the IF multiplied signal obtained from each amplifier and detect the level.
14 is provided, and the outputs of the respective level detectors 9 to 14 are added by an adder 15.

On the other hand, the latter stage amplifier of the cascade-connected IF amplifiers constituting the intermediate frequency amplification circuit, that is, the final stage IF
A bypass filter 16 is inserted between the output of the amplifier 7 and the level detector 14 as a band limiting means.

The output of the adder 15 is outputted to an output terminal 18 via an output circuit 17 that performs DC level shifting.

As shown in FIG. 2, the output circuit 17 is configured to receive a positive signal output current No+is) and a negative signal output current (■.+18) from the adder 15, and is connected to the current source of the positive current. 171 and a negative current source 172
One end of the resistor RLI is connected to the connection point with the resistor RL.
A diode D is inserted between the other end and the reference potential point, and a current (2) is applied to this diode D independently. A constant current source 173 is connected thereto. and the current source 17
The connection point between 1 and 172 is the detection level output terminal 18.

In the above configuration, the amplification factor of the intermediate frequency amplification circuit made up of the IF amplifiers 2 to 7 is the product of the amplification factors of the amplifiers in each stage. Therefore, when the antenna input level gradually increases from a low state, the final stage IF amplifier 7 with a high amplification factor operates first to generate an output. Next, the IF amplifiers 6 before and after it operate, and in the same way, outputs are generated from the amplifiers at the previous stage.

Therefore, if a bypass filter 16 is inserted between the final stage IF amplifier 7 and its level detector 14 as shown in the illustrated example, the AC characteristics when the antenna input level is low, as shown in FIG. (b) A sufficient output level can be obtained without the level drop as in the conventional case.

In addition, in the output circuit 17, the constant current source 1 is connected to the resistor Rt.
The difference current between 71 and 172, i.e. (r01m)
(Io +1.) = 2 II flows,
Furthermore, the level shift amount VIIE caused by the current I0 flowing through the diode D is added, and the output becomes {circle around (2)}. =
It can be 2L+Vat.

As a result, as shown in FIG. 3, both the DC characteristic (a) and the AC characteristic (b) are level-shifted to the high output side.

In addition, in the above embodiment, an example was shown in which a bypass filter as a band-limiting filter was inserted only between the final stage IF amplifier and its level detector. A bypass filter may also be inserted into the IF amplifier.

〔effect〕

As is clear from the above explanation, according to the present invention, when the antenna input level is low, the AC
It is possible to extract the output of the component linearly, and it is very effective when used as an antenna switching control signal for a guivacity receiver.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a wiring diagram showing a part of the configuration of Fig. 1, and Fig. 3 is a characteristic diagram showing the operating characteristics of the present invention. , FIG. 4 is a characteristic diagram showing the operating characteristics of the conventional device. l...Intermediate frequency signal input end, 2-7...IF amplifier, 8...Intermediate frequency signal output end, 9-14...Level detector, 15...Adder, 16... Band-limiting filter, 17... Output circuit, 18... Output end of detection level. Figure (a) DC special trend diagram

Claims (2)

[Claims] (1) an intermediate frequency amplification circuit which receives an intermediate frequency signal and has amplifiers connected in cascade across multiple stages to sequentially amplify the signal; and a plurality of level detectors that level detect the outputs of the respective amplifiers; In a level detection circuit equipped with an adder that adds each output of a plurality of level detectors, the level detector is provided between at least a subsequent amplifier of the cascade-connected amplifiers forming the intermediate frequency amplification circuit and the level detector. A level detection circuit characterized by inserting a band-limiting filter. (2) The level detection circuit according to claim (1), characterized in that a DC bias source is connected to the output end of the adder to level shift the level of the adder output.