JPH0218496B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that outputs data according to a prescribed format.

[Description of prior art and its problems] Fig. 1 shows a conventionally known data recording device.
Input addresses and symbol code signals such as characters are output from signal lines 12 and 13 of an input unit such as a magnetic tape, paper tape, disk, or keyboard. Such a signal enters the address and code converter 14,
Here, the input address is converted into a physical address of a page data storage unit (hereinafter referred to as PDM) 17 indicated by 17 and outputted onto a signal line 15, and the symbol code signal is transmitted to a symbol pattern generation unit (hereinafter referred to as PDM) indicated by 18. CG) 18, the corresponding symbol pattern is converted into a stored address and output onto the signal line 16.

The signal dot patterns generated by the CG 18 are sequentially applied to the output section 20 and recorded on a recording medium (not shown).

What is shown in FIG. 2 is the format of data to be output from the output section 20. In the conventional apparatus shown in FIG. 1, in order to output such data, It is necessary to take the Y coordinate axis and input coordinate axis information (address) and character code information for all coordinates. Generally, this work is complicated and requires a huge amount of time. Also, this operation is necessary for all coordinates each time the output format changes. Even if the output format is the same and there is no change in the head part (kanji part), the output information will change in the front part (name part) and data part (numeric part), so at least write the character code with coordinates for this changed part. I needed to input it.

[Means and operations for solving the problems] The present invention has been made in view of the above-mentioned conventional technology, and includes a storage means for expanding data to be output, and a storage means for expanding and storing data to be outputted. an output means for outputting, an input means for inputting area information specifying data to be output and an area on the storage means in which the data is expanded, and the storage means corresponding to the area information input by the input means. an arrangement direction specifying means for specifying the arrangement direction of data within the above area; and an arrangement direction specifying means for specifying the arrangement direction of data in the above area, and the storage means for storing the data stored in the storage means in accordance with the arrangement direction specified by the arrangement direction specifying means, corresponding to the area information. By providing a data processing device having a control means that is expanded within a region on the means and outputted by the output means, it is possible to reduce the complexity of inputting data when outputting data according to a predetermined format. The purpose of this is to reduce the complexity and improve the operability of data entry, corrections, changes, etc.

[Example] An example of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing a recording apparatus to which the data processing apparatus according to the present invention is applied, in which the members denoted by the same numbers as in FIG. 1 are composed of the same members as in FIG. 1.

In FIG. 3, numeral 21 indicates a format storage section that stores formats in advance, and this format will be explained in detail.

If we consider the area surrounded by ruled lines in the form shown in Fig. 2 as one area, we can consider that Fig. 2 is made up of eight areas R1 to R8 as shown in Fig. 4. I can do it. Then, by specifying the two diagonal points of each region as (Xsn, Ysn) (Xen, Yen) as shown in FIG. 5, the region Rn can be specified. Each is first stored in the format storage section 21 using the coordinates of two diagonal points. Here, the arrangement order of data in each area will be described. For example, in the region R1, characters are arranged in the direction 6a as shown in FIG. 6a, and the characters are arranged in a downward direction from the top. Therefore, the sixth
Character data as shown in Figure c (however, b is a blank code) and arrangement direction information S as shown in Figure 6 a.
1, it is possible to reproduce the character arrangement shown in FIG. 6a.

In addition, in region R2, as shown in FIG. 6b, 6b
The characters are arranged in the direction, and the characters are arranged in the left to right direction. Therefore, Figure 6d
If there is character data such as , and arrangement direction information S5 as shown in FIG. 6b, it is possible to reproduce a character arrangement as shown in FIG. 6b. When storing the regions R1 to R8 using two coordinates, the format storage section 21 also stores arrangement direction information for each region.

There are eight types of such arrangement directions as shown in FIG. 7 a to h, and these arrangement directions are designated as S1 to S
8, S1 to S8 can be represented by 3 bits as shown in FIG.

Therefore, as shown in FIG. 9, the format storage unit 21 stores the coordinates Xs ₁ , Ys ₁ , Xe ₁ ,
Ye ₁ and array information S1 will be stored.

Similarly, the coordinates and arrangement information S of each area are stored in advance from the input unit 11 via the input line 11-a.

The output of the format storage section 21 and the character code signal from the input section are applied to the expansion section 22, which has a circuit configuration as shown in FIG.

In Figure 10, there are three switches SWA,
There are SWB and SWC, and these switches are controlled by bits SA, SB, and SC of the array signal shown in FIG. 8, respectively, and have the same signs as bit signals 0 and 1 shown in FIG. Contact 0 or 1 marked with
It is something that comes into contact with. That is, when the array signal S2 is applied from the format storage section 21 to the expansion section 22, the SWA contact piece contacts contact point 1, the SWB contact piece contacts contact point 0, and the SWC contact piece contacts contact point 0. It is. Therefore, FIG. 10 shows a state in which the switches SWA, SWB, and SWC are controlled by the array signal S1.

Reference numeral 31 denotes a data latch section which receives input data via the signal line 11b and sequentially outputs data to the signal line 13 at every data reading clock of the signal line 32. Memory 2 included in format storage unit 21
The subtraction circuit 33 receives the X-axis information Xns and Xne of the start and end of the region Rn from 1-1 and 21-2.
Xns (X area size) is determined and inputted to the X comparison circuit 35 via the signal line 34.

On the other hand, this comparison circuit 35 is connected to
A signal Xc from a counting circuit 37 is input. When the two input numerical values match, the X comparison circuit 35 outputs an X match signal (X end signal) to the signal line 38. This X end signal is input to the clear terminal of the X counting circuit 37 and makes the value of the X counting circuit 37 zero. On the other hand, the clock line 39 of the X counting circuit 37 is connected to the common terminal (C terminal) of SW1 of the switch circuit SWC. 40 Y
Connected to receive a match signal. 41 is the X starting point Xns and the X count value Xc by the counting circuit 37.
Xns+ is connected to the signal line 42.
It outputs the added value of Xc and is connected to the "0" side of the switch circuit SWA. Furthermore, 43 is the end point of X
It is a subtraction circuit for Xne and the X count value Xnc, and outputs the subtraction value of Xne-Xc to the signal line 44, which is connected to the "1" side of the switch circuit SWA. A numerical value on the X coordinate of the data at that time is outputted to the common terminal C of the switch circuit SWA and given to the signal line 45. If the switch circuit SWA is "0", a numerical value that is incremented from the X start point Xns is output on the signal line 45 every time data is sent to the signal line 13, and if it is "1", it is decremented from the X end point Xne. The numerical value will be output.

Next, the Y-axis side will be explained. Format storage section 2
1 receives the Y-axis information Yns Yne of the start and end of the area Rn from the memories 21-3 and 21-4 included in the memory 21-3, 21-4, and calculates Yne-Yns (Y area size) in the subtraction circuit 46, and performs a Y comparison via the signal line 47. input to circuit 48; On the other hand, a signal Yc from a Y counting circuit 50 is inputted to this Y comparing circuit 48 via a signal line 49.
The Y comparison circuit 48 outputs a Y match signal (Y end signal) onto the signal line 40 when these two input values match. This Y end signal is input to the clear terminal of the Y counting circuit 50 and makes the value of the Y counting circuit 50 zero.

On the other hand, the clock line 51 of the Y counting circuit 50 is connected to the common terminal (C terminal) of SW2 of the switch circuit SWC, and if SW2 is on the "0" side, the X match signal on the signal line 38 is set to "1". For example, the signal line 32 is connected to receive the clock signal. Further, 52 is an addition circuit for the Y starting point Yns and the Y count value Yc, which outputs the added value of Yns+Yc to the signal line 53, and is connected to the "0" side of the switch circuit SWB.

Furthermore, 54 is a subtraction circuit for the Y end point Yne and the Y count value Yc, which outputs the subtraction value of Yne-Yc to the signal line 55 and is connected to the "1" side of the switch circuit SWB. The value on the Y coordinate of the data at that time is outputted to the common terminal C of the switch circuit SWB and given to the signal line 56. If the switch circuit SWB is “0” in the signal line 56, the signal line 1
Every time data is sent to 3, a numerical value is output that is incremented from the Y starting point Yxs, and if it is "1", a numerical value that is decremented from the Y ending point Yne is output.

On the other hand, in the switch circuit SWC, SW1 and SW2
operate in conjunction with each other, and if it is on the “0” side, the X counting circuit 3
7 is counted by the clock on the signal line 32, and the Y counting circuit 50 is counted by the X coincidence signal from the signal line 38. If it is "1", the X counting circuit 37 is counted by the Y coincidence signal of the signal line 40, and the Y counting circuit 50 is counted.
is counted by the clock on the signal line 32. The switch circuits SWA, SWB, and SWC correspond to bits SA, SB, and SC of the sequence code shown in FIG.

In synchronization with the data outputted to the signal line 13 in this manner, X and Y address data on the form are outputted to the signal line 12. As shown in FIG. 3, the data and address sent out in this way are converted into internal codes of PDM addresses and CG addresses by the address and code converter 14, output to signal lines 15 and 16, and stored in the PDM 17. Ru.
Then, it is given to the character generation section 19 and the output section 20 through the CG 18 according to a startup command or the like, and is outputted.

Although the above embodiment did not use a data buffer, as shown in FIGS. 11a to 11d,
The data buffer DB can also be used in various locations.

[Effects of the Invention] According to the present invention, when outputting data in a predetermined format, the complexity of data input can be reduced and the operability of data input, correction, change, etc. can be improved. We can provide a data processing device that can

[Brief explanation of drawings]

FIG. 1 is a front view showing the output form of stored data, FIG. 2 is a block diagram showing a conventional storage device, and FIG. 3 is a block diagram showing a recording device using a data processing device according to the present invention. Fig. 4 is an explanatory diagram showing the division of the output form shown in Fig. 1 into a plurality of regions, Fig. 5 is an explanatory diagram showing the coordinates given to the regions, and Figs. 6 a and b show the arrangement of recording data in the regions. Front view, Figures 6c and d are diagrams showing recorded data, Figures 7a to h are explanatory diagrams showing data arrangement order, Figure 8 is a diagram showing code signals of data arrangement order, and Figure 9 is a memory diagram. 10 is a block diagram showing essential parts of a data processing apparatus according to the present invention, and FIGS. 11a to 11d are block diagrams of a recording apparatus to which the present invention is applied. Here, 11 is an input section, 14 is an address and code conversion section, 17 is a page data storage section, 19 is a character generation section, 20 is an output section, 21 is a format storage section, 2
2 is a development part, R1 to R8 are regions, 33, 43, 4
6, 54 are subtraction circuits, 35, 48 are comparison circuits, 3
7 and 50 are counting circuits, and 41 and 52 are addition circuits.

Claims (1)

[Scope of Claims] 1. Storage means for expanding data to be output; Output means for outputting the data expanded and stored in the storage means; Data to be output; an input means for inputting area information specifying an area on the storage means; and an arrangement direction specifying means for specifying an arrangement direction of data within an area on the storage means corresponding to the area information input by the input means. , control means for expanding the data stored in the storage means within an area on the storage means corresponding to area information according to the arrangement direction designated by the arrangement direction designation means, and outputting the data by the output means; A data processing device consisting of. 2. The data processing device according to claim 1, wherein the output means is a printer. 3. The data processing device according to claim 1, wherein a plurality of areas are stored on the storage means.