JPH02183350A - Memory access circuit - Google Patents

Abstract

PURPOSE:To efficiently store data to a memory or to read the data by counting a clock signal and preparing the access timing of the memory. CONSTITUTION:A counter 31 of a memory timing adjustment circuit inputs a clock signal the inverse of CLK and counts the number of the clocks corresponding to the pointer of the memory. A counter 29 counts the number of the input and output data to the memory synchronizing with the clock signal the inverse of CLK. A comparator 30 compares these count values and when those values are coincident, a coincidence signal 24 is made high level. Then, an SE signal outputted from an AND circuit 27 writes the data of an SD bus to the serial port of the memory with the rising of a clock signal SAS. Thus, since the serial port side of the dual port memory can be asynchronously accessed, the memory can be simultaneously read and written and the use efficiency of the bus is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory access circuit that accesses a memory such as a dual port memory and executes data input/output processing between the memory and an input/output device. It is something.

[Prior Art] Conventionally, when storing image data such as image data from a scanner or the like, or image data output to a printer or CRT, etc., a unit that can write and read data through the same boat has been used. It was stored in a memory consisting of RAM with only one port.

[Problems to be Solved by the Invention] However, in the above conventional example, when data is being written to the memory, data cannot be read from the memory.
While data was being read from memory, it was not possible to write data to that memory. For this reason, for example, if you are inputting image data from a scanner and outputting that image data to a printer, you will not be able to output to the printer while the image data is being input from the scanner.
There is also a problem in that the image data cannot be manually scanned by the scanner while it is being output to the printer.

Furthermore, since such image data is generally large in amount, the bus is occupied for a long time while the image data is being transferred, resulting in the problem that other resources on the same bus cannot be used effectively.

The present invention has been made in view of the above-mentioned conventional example, and uses a memory that manually generates a clock signal, updates a pointer indicating a memory buffer using the clock signal, and calculates the memory access timing by counting the clock signal. It is an object of the present invention to provide a memory access circuit that can efficiently store and read data from and to a memory by creating the memory and accessing the memory.

[Means for Solving the Problems] In order to achieve the above object, a memory access circuit of the present invention has the following configuration. That is, it is a memory access circuit that receives a clock signal, counts the clock signal, and accesses a memory provided with a pointer that points to a buffer in the memory. a first counting means for counting the number of said clock signals; a second counting means for counting the number of input/output data to said memory in synchronization with said clock signal; and said first and second counting means. It has a comparing means for comparing the counted values, and an accessing means for writing to or reading from the memory when the comparing means determines that the counted values match.

[Operation] In the above configuration, the clock signal is manually generated and the number of clocks is counted in correspondence with the pointer of the memory. In addition, the number of human output data to the memory is counted in synchronization with the clock signal. These counted values are compared, and if it is determined that the counted values match, it operates to write to or read from the memory.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Overall Configuration (FIG. 1)] FIG. 1 is a block diagram showing the entire memory circuit of this embodiment.

In FIG. 1, 11 is a memory timing adjustment circuit whose details are shown in FIG. 2, which controls data transfer between the memory 12 and the I10 device 14.

Reference numeral 12 denotes a memory having two ports, a random access port and a serial access port (hereinafter referred to as dual port memory), which stores data input via a data bus from a CPU (not shown), or vice versa. SD bus data can be input and output asynchronously via the serial port.

13 is a memory controller for the dual port memory 12, which controls the memory 12 address and row address (RAS).
It outputs column address (CAS), write signal (WE), etc. 14 is a 110 device with DMA function,
Outputs a data input/output request to memory 12, and
2 or read data from dual port memory 12.
Data can be written to.

[Memory Timing Adjustment Circuit (FIGS. 2 and 3)] FIG. 2 is a circuit diagram showing the configuration of the memory timing adjustment circuit 11. As shown in FIG.

JK flip-flops 17 to 21 and 26 operate at the falling edge of the clock signal SAS. 29.
30 is one of the serial ports of dual port memory 12
A counter that counts the number corresponding to the number of line buffers.
The counter 31 counts the same as the count value of the line buffer of the serial port of the dual port memory 12, and the counter 29 counts up every time SD bus data is written to the dual port memory 12.

30 is a comparator, and counters 29 and 31
When these values match, a match signal 24 is set to high level and output to an AND circuit 27.

SE double signal output from the AND circuit 27 This is a signal for writing data into the dual port memory 12. When the SE double signal is at high level, the dual port memory 12 writes the SD bus data to the memory 12 at the rising edge of the clock SAS.
Write to the serial boat. For example, when the number of serial port buffers in the dual port memory 12 is 256, the counters 29 and 31 each consist of 8 bits, and corresponding to the count value of the counter 29, the serial port buffers in the dual port memory 12 are sequentially loaded. Data is transferred.

When data is written to all line buffers of the serial ports of the dual port memory 12 in this way, the counter 2
A carry signal (TREQ) is output from 9 to the memory controller 13. As a result, the memory controller 13
outputs TR10E (word) to the dual port memory 12, writes the data in the serial port buffer of the dual port memory 12 to the real memory, and resets the address to the new write pointer.The TREAD signal is sent from the memory controller 13 to the memory It is output to the timing adjustment circuit 11, and is set to a high level in the serial read mode from the dual port memory 12, and set to a low level in the serial write mode.

Next, the operation of the memory timing adjustment circuit 11 will be explained based on the circuit diagram of FIG. 2 and the timing chart of FIG. 3.

To illustrate the operation of writing data to the serial port of the dual port memory 12, first the I10 device 14 writes data to the serial port of the dual port memory 12.
2, the REQ signal is output to the memory timing adjustment circuit 11. When the memory timing adjustment circuit 11 receives the REQ signal, the AND
The flip-flops 17 to 21 are sequentially set via the gate 16, and an ACK signal is sent back to the I10 device 14 at the timing shown in FIG. As a result, the I10 device 14 outputs the write data to the dual port memory 12 to the IOD bus, and this data is latched into the flip-flop 33 in synchronization with the falling edge of the ACK signal (
Timing Tl).

Further, the flip-flop 26 is set at this timing T1, and when the values of the counters 29 and 31 become equal and the match signal 24 of the comparator 3o becomes high level, the SE multiplied signal is outputted at a high level at timing T2. Here, since the I10 device 14 is writing to the memory 12, the TREAD signal is at a low level, so the output of the AND circuit 40 becomes a low level in synchronization with the SE multiplied signal. As a result, ■O from I10 device 14
Data inputted through the D bus and latched in the flip-flop 33 is outputted to the memory 12 through the tri-state buffer 38 and the SD bus. Then, the SD bus data is written to the serial port of the dual port memory 12 at the rise of the SAS clock (timing T3) when the SE double signal is at high level.

In this way, data is written to all line buffers of the serial ports of the dual port memory 12, and the counter 2
When the carry signal (TREQ) of 9 becomes high level (
At timing T5), as described above, the memory controller 13 outputs the TR10E signal and writes the serial port data to the real memory of the dual port memory 12.

[Description of writing data to memory (FIGS. 4 to 7)] FIGS. 4 to 7 are flowcharts showing the operation of the memory circuit of the embodiment.

FIG. 4 is a flowchart showing the operation of the I10 device 14. First, in step Sl it is checked whether there is data to be written in the memory 12, and if there is data to be written, the REQ signal is sent to the memory timing adjustment circuit in step S2. 1
Output to 1. Then, in step S3, wait for the input of the ACK signal from the memory timing adjustment circuit 11, and when the ACK signal is input, the data to be written is transferred to the IOD in step S4.
Output to bus.

FIG. 5 shows the operation of the memory timing adjustment circuit 11 in response to this.

When the REQ signal from the I10 device 14 is input in step S5, the ACK signal is output in step S6 as described above, and the data on the IOD bus is input and latched into the flip-flop 33 in step S7. In step S8, it is waited for the counted value of the counter 29 and the counted value of the counter 31 to match, and when they match, they are outputted to the SE multiplied signal memory 12 in step S10. As a result, the tri-state buffer 38 is enabled, and the data latched in the flip-flop 33 is output as an SD bus. and,
At the next rise of the clock SAS, the counter 29 is incremented by 1 (step S11, step 512), and step S1
When a carry occurs in the counter 29 at step 3, the TREQ signal is output to the memory 12. This turns off the SE signal and closes the AND circuit 32.

FIG. 6 is a flowchart showing the operation of the serial port of the dual port memory 12. In step S20, it is checked whether the SE signal from the memory timing adjustment circuit 11 is at a high level, and if it is at a high level, the serial port is The SD bus data is stored in the buffer of the boat (step 522), and the write pointer in the memory 12 pointing to the line buffer is incremented by 1 (step 523). On the other hand, if the SE signal is at a low level in step S20, the process proceeds to step S24, and in synchronization with the rising edge of the SAS clock, similarly to step S23,
Add 1 to the write pointer.

FIG. 7 is a flowchart showing the operation of the memory controller 13. When the TREQ signal is input from the memory timing adjustment circuit 11 in step S26, the TR10E signal is output to the dual port memory 12, and the serial port data of the memory 12 is transferred to the real memory. Transfer to. Then, in step S28, the pointer in the memory 12 is advanced by one line.

[Explanation of reading from memory to 170 devices (Figures 3 and 8)
11)] Next, the operation of reading data from the serial port of the dual port memory 12 and transferring it to the I10 device 14 will be described.

Since the TREAD signal is at a high level when reading from the memory 12, the Q output of the JK flip-flop 26 is set to a high level by the CLR signal. As a result, even if the REQ signal is output from the I10 device 14, the AND
Since circuit 16 is not opened, no data is transferred to I10 device 14. Then, when the outputs of the counter 29 and the counter 31 match, an SE signal is output to the dual port memory 12. As a result, the SD bus data is output from the dual port memory 12, and the SD bus data is sent to the D flip-flop 34 in synchronization with the falling edge of the SAS clock.
The bus data is latched.

At the same time, the JK flip-flop 26 is inverted,
Since the Q output becomes low level, one input of the AND circuit 16 becomes high level. When the REQ signal is input from the I10 device 14, the output of the AND circuit 16 becomes high level, and an ACK signal is sent back to the I10 device 14 in the same way as in the serial write mode to the memory 12.

At the same time, the output of the AND circuit 37 becomes low level, so the tri-state buffer 36 is enabled, and the data input from the SD bus stored in the flip-flop 34 is output to the IOD bus and output to the I10 device 14. be done. This is shown at timing T6 in FIG.

When the carry signal (TREQ) is output from the counter 29, the TREQ signal is output as in the serial write mode, causing a data transfer cycle in the dual port memory 12.

The above operation will be explained using flowcharts shown in FIGS. 8 to 11.

FIG. 8 is a flowchart showing the operation of the I10 device 14.

If data input is possible in step S30, step S31
Then, the REQ signal is output to the memory timing adjustment circuit 11. Then, when the ACK signal is input from the memory timing adjustment circuit 11, data on the IOD bus is input in step S33.

FIG. 9 is a flowchart showing the operation of the memory timing adjustment circuit 11.

If the outputs of the counters 29 and 31 match in step S34, the process proceeds to step S35, where an SE multiplied signal is output. As a result, flip-flop 3 is activated at the falling edge of the SAS clock.
4, the data on the IOD bus is latched. At the same time, the counter 29 is incremented by 1, and when a carry occurs, TR
An EQ signal is output (steps 337-539). As a result, the contents of the real memory of the dual port memory 12 are transferred to the serial port, making the next serial read possible.

In this state, the flip-flop 26 is inverted and the REQ signal can be input, so the I1
Wait for the REQ signal to be input manually from the 0 device 14, and then
When a Q signal is received, AC is activated at the same timing as when writing.
Output the K signal to the I10 device 14 (step 541)
. The data 36 is opened in synchronization with this ACK signal, and the data from the memory 12 is output to the IOD bus.

FIG. 10 is a flowchart showing the operation of the dual port memory 12.

When the SE multiplication signal is manually operated in step S50, step S51
Outputs the data to the SD bus. Then, at the rising edge of the SAS clock, the read pointer pointing to the buffer of the serial port in the memory 12 is incremented by 1.

FIG. 11 is a flowchart showing the operation of the memory controller 13.

Here, when the TREQ signal is input in step S54, the contents of the real memory in the dual port memory 12 are transferred to the serial port in step S55, and in step S56
The read pointer is updated by one line.

[Other Embodiments (FIG. 12)] FIGS. 12 and 13 are block diagrams showing other embodiments of the present invention, in which parts common to the previous embodiments are designated by the same numbers.

The difference from the above-mentioned embodiment is that the memory controller 13a
TAC output to the memory timing adjustment circuit 11a
The point is that the K signal is provided. As a result, the memory controller 13a accepts the TREQ signal and stores TR1 in the memory 12.
Before the 0E signal is output and the data is transferred from the real memory to the serial buffer within the memory 12, reading and writing of the next data to the memory 12 can be inhibited.

FIG. 13 shows a memory timing adjustment circuit 11 of another embodiment.
11a is a circuit diagram showing the configuration of 11a.

In the figure, a JK flip-flop 25 is provided and TR
Reading and writing data for EQ signal output is prohibited. That is, when the TREQ signal is output from the counter 29, the Q output of the JK flip-flop 25 becomes low level, closing the AND circuit 32a and inhibiting the counter 29 from counting and from latching to the flip-flop 34. Then, when the TACK signal is returned after the memory controller 13a completes data transfer from the real memory in the memory 12 to the serial port, the Q output of the JK flip-flop 25 becomes low level and the AND circuit 32
a is opened, and the memory 12 can be read and written again.

Note that the dual port memory 12 can be read and written even from the middle of the serial port buffer, so if the counter 30 is configured to be presetable, reading and writing can be performed from any position (address) in the dual port memory 12. It goes without saying that it can be done.

As described above, according to this embodiment, the serial port side of the dual port memory can be accessed asynchronously, so that simultaneous reading and writing of the memory is possible, and bus usage efficiency is improved.

[Effects of the Invention] According to the present invention as described above, a memory that receives a clock signal and updates a pointer indicating a buffer in the memory using the clock signal is used, and the memory is accessed by counting the clock signal. By creating the timing and accessing the memory, data can be efficiently stored and read from the memory.

[Brief explanation of the drawing]

Figure 1 is an overall configuration diagram for explaining the positioning of the memory timing adjustment circuit of this embodiment, Figure 2 is a circuit diagram showing details of the timing adjustment circuit of this embodiment, and Figure 3 is the timing adjustment of Figure 2. A timing chart showing the operation timing of the circuit. Fig. 4 is a flowchart showing the write operation to the memory by the 110 device. Fig. 5 is a flow chart showing the write operation to the memory by the memory timing adjustment circuit. Fig. 6 is a flow chart showing the write operation to the memory by the memory timing adjustment circuit. FIG. 7 is a flowchart showing the operation of the memory controller when writing to the memory; FIG. 8 is a flowchart showing the readout operation from the memory by the 110 device; FIG. 9 is the memory timing adjustment circuit. 10 is a flowchart showing the readout operation in the memory, FIG. 11 is a flowchart showing the operation of the memory controller when reading from the memory, and FIG. 12 is the memory of another embodiment. FIG. 13 is a block diagram showing the overall configuration of the circuit, and FIG. 13 is a circuit diagram showing the circuit configuration of a memory timing adjustment circuit according to another embodiment. In the figure, 11. lla...Memory timing adjustment circuit, 12...Memory, 13.13a...Memory controller, 14...170 equipment, 17-21, 25.
26...JK flip-flop, 29.31...Counter, 30...Comparator, 33.34...D
It is a type flip-flop. Patent applicant Canon Co., Ltd. Figure 6 Figure 7 Figure 10 Figure 11

Claims (1)

[Claims] (1) A memory access circuit that receives a clock signal, counts the clock signal, and accesses a memory provided with a pointer that points to a buffer in the memory, which inputs the clock signal and counts the clock signal to access a memory that has a pointer that points to a buffer in the memory. a first counting means for counting the number of the clock signals; a second counting means for counting the number of input/output data to the memory in synchronization with the clock signal; and the first and second counting means. and access means for writing to or reading from the memory when the comparing means determines that the counted values match. Memory access circuit.