JPH02181552A - High efficient code packet transmission system - Google Patents

Abstract

PURPOSE:To execute correct coding and decoding by using high efficient sound coding based upon a forecasting difference coding principle to suppress a silent part, and even in case of sending a packet, executing reset control. CONSTITUTION:At the time of inputting the number of samples P corresponding to a packeting period, an arithmetic circuit 2 sends the added result of the samples P obtained up to that point to a decision circuit 3 to decide a sound part or a silent part. In the case of the silent part, a reset signal is sent from the circuit 3 to a coding circuit 5 through a signal line 8 at the timing when a sample value inputted to the circuit 5 is set up between the final sample out of P samples and its succeeding sample. In the case of a sound part, the circuit 5 continuously codes the inputs and packets and sends the coded results of P samples stored in a memory 6. The packet received by a receiving circuit 9 is stored in a memory 10. The data outputted from the memory 10 are decoded and outputted to a selection circuit 14. When a packet control circuit 11 decides silence, noise is generated from a noise generating circuit 13 and the selection circuit 14 is controlled to select the output of the circuit 13. After resetting the packet, decoding is started by a decoding circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-efficiency code packet transmission system in which an analog signal such as voice is digitized and only the voiced portion thereof is converted into packets and transmitted and received.

[Conventional technology]

When transmitting analog signals such as voice in packets, A/
It is converted into a linear PCM code or a more compressed playPcM code by D conversion, which is assembled into a packet and sent. Even when suppressing silent parts and packetizing and transmitting only the sound part, if you use these codes, there is no problem if you simply transmit the code of the sound part as is. This is because PCM codes such as linear codes and μlaw is unaffected by the previous sample value when encoding one sample,
This is because the encoding has a one-to-one correspondence.

On the other hand, ADPCM codes that rely on predictive difference quantization use past sample values for sample encoding. Correct decoding is not possible due to missing information. In other words, in predictive differential encoding, the internal state at the time of encoding determined by the past input signal must match the internal state of the decoding circuit when decoding the code. First, the reset timing needs to be synchronized between encoding and decoding. Therefore, conventionally, when transmitting packets using such differential encoding, it has been assumed that consecutive codes are packetized and transmitted without suppressing silence.

[Problem to be solved by the invention]

However, since this method does not improve transmission efficiency by suppressing silence, there is a need for a technology that can correctly decode signals even when suppressing silence.

There are two ways to do this: On the transmitting side, when processing a silent part, the encoding circuit is stopped, and the encoding of the next sound part is started from the stopped state at that time. One possible method is to pseudo-reset the internal state of the circuit.

On the receiving side, if the next packet does not arrive (silence suppression)
In response to the above processing, the decoding circuit can be stopped or inputted with 0 to create a pseudo reset state. In the former method, the internal states of the encoding circuit and the decoding circuit match, so
Theoretically correct decoding can be performed. However, since predictive differential encoding uses correlation between voices, it may not perform as well as it should for discontinuous voices. The latter requires a sufficiently long time to equivalently bring the device into the reset state with zero human effort, and it is not always possible to reach the reset state sufficiently in a short silent period.However, the biggest problem with these methods is that On the transmitting side, the processing time (delay time) increases because it is necessary to first determine whether there is a sound or no sound and then perform encoding.

Therefore, if the voice/silence detection process and the encoding can be performed in parallel, an increase in delay time can be prevented.

However, in order to do this, a method is required that can process the encoding regardless of whether there is a sound or no sound.

The present invention provides a high-efficiency coded packet transmission method that enables correct decoding by synchronizing an encoding circuit and a decoding circuit when transmitting packets with silence suppression using predictive differential encoding. The purpose is to

[Means to solve the problem]

In order to achieve the above object, in the high-efficiency code packet transmission system according to the present invention, the transmitting side receives a digital code sequence such as an audio signal, and determines whether the code sequence is voiced or silent using the code sequence of a certain length. An identification circuit that identifies each block (this is called a block), a predictive differential encoding circuit that receives, encodes and outputs the digital code sequence in parallel, and writes the encoded output from the predictive differential encoding circuit. A memory that stores one block at a time, and a block stored in that memory.
If the identification circuit determines that there is a sound, the block is read out from the memory and packetized, and the relative transmission time relationship between the packet transmitted before the packet and the packet transmitted after this is indicated. A transmitting circuit attaches a sending time related display signal to its header and transmits it, and if the block is determined to be silent by the identifying circuit, the block is not packetized and the beginning of the next block is a reset means for resetting the predictive differential encoding circuit immediately before the constituent code sequences are input to the predictive differential encoding circuit; a receiving circuit that interprets and decomposes the packet, a decoding circuit that decodes the high-efficiency encoded signal by predictive differential encoding, and a decoding circuit that interprets the transmission time relationship display signal included in the header and decodes the received packet. If the block is consecutive to the code block of the previously received packet, the code block of the received packet is input as is to the decoding circuit; if the block is not consecutive, then
and a control circuit that manually inputs the code sequence of the block to the decoding circuit after resetting the decoding circuit.

[Effect]

Considering a method of identifying voice and silence, and packetizing and transmitting only the voice portion, first of all, it is difficult with conventional technology to identify voice/silence on a sample-by-sample basis; For example, the power for a certain length of time, such as 16 ms or 32 ms, is calculated, and it is determined whether that part is silent or has sound. Therefore, when a PCM code such as linear or μlaw is encoded with higher efficiency and packetized, if the voiced part is encoded and sent after determining whether there is a voice, for example, in the determination time of 32ms, the packetization is further increased by 32m5. This results in a total delay time of 64m5. In order to prevent this delay time from increasing, it is sufficient to simultaneously execute the determination process based on calculations such as power and the encoding process in parallel, and by doing so, the delay time can be suppressed to only 32 m5 of the storage time. But with this method,
The encoding process must be performed continuously regardless of whether the block is voiced or silent.In other words, even if the block is determined to be silent, the encoding of that block cannot be stopped. If the encoding result of the block determined to be silent is not sent after encoding, the decoding side will not be able to synchronize its internal state with the encoding circuit, resulting in errors in decoding.

Therefore, in the present invention, when it is determined that the block is silent, the encoding process of the first sample of the next block is first reset and then performed.By resetting, the internal state of the encoding circuit is set to the initial value. , so it can be encoded without being affected by the previous sample value. Therefore, even if the decoding side does not receive the code samples of the silent period, by starting decoding after resetting, the internal state can be synchronized and correct decoding can be performed.

[Embodiment] (1) in FIG. 1 is a block diagram showing an embodiment of the encoding side circuit. In the figure, 1 is a signal input terminal, for example, a linear or .mu.la- PCM code string. Reference numeral 2 denotes a circuit that calculates the power of the signal inputted from the terminal 1 at double cycles in order to perform sound/silence determination processing. 3 is arithmetic circuit 2
This is a circuit that determines whether there is a sound or no sound based on the calculation result of 5.
is a high-efficiency encoding circuit based on a predictive differential encoding method, for example, an ADPCM code encoding circuit; 6 is a memory that stores the output of the encoding circuit 5; 7 is a memory that reads out the code string stored in the memory 6 and uses the necessary This is a packetization circuit (transmission circuit) that adds a header etc. and sends it to the line according to the protocol.

Further, 4 is a delay circuit provided to guarantee reset timing.

For example, a signal inputted from the input terminal 1 at a cycle of 125 μs is first subjected to calculations such as power in the arithmetic circuit 2, and is simultaneously inputted to the delay circuit 4, where it is delayed for several cycles, and then inputted to the encoding circuit 5, where it is encoded. The converted results are sequentially written into the memory 6. Assuming that the packetization cycle is 32m5, when 256 samples are manually generated, the calculation circuit 2
The power addition results for 6 samples are sent to the judgment circuit 3,
There, it is determined whether there is a sound or no sound. If it is determined that there is no sound, the sample value input to the encoding circuit 5 is passed from the determination circuit 3 to the encoding circuit 5 through the signal line 8 by checking the timing between the last sample and the next sample of the 256 samples. Sends a reset signal. If it is determined that there is a voice, the encoding circuit 5 continuously encodes without resetting,
It also instructs the transmitting circuit 7 to packetize the encoding results of 256 samples stored in the memory 6 and send them out. If there is no sound, no packetization instruction is given, so the encoding results corresponding to that are discarded.

FIG. 2 is a timing chart for explaining the above operation. In the figure, 21 represents the timing of the signal input to the input terminal 1 in Figure 1 (1), and in this example, 1
It is assumed that input is performed at a cycle of 257zs.0, 1, etc. from a certain point as shown in the figure. ...and number them in the order of input.

Assuming that the delay circuit 4 provides a delay of one period, the input to the encoding circuit 5 is delayed by one period as shown at 24. Assuming that the packet length is 32m5, that is, 256 cycles, first the input value sequence 0. l, 2. . . ., the power and the like are calculated by the arithmetic circuit 2 at the time within each cycle. When the 256th sample, that is, the sample of the input value string 255, is input, the power calculation results for the previous 256 samples including that sample are input to the determination circuit 3.

At the same time, the encoding circuit 5 encodes the input samples with a one-cycle delay and sequentially stores them in the memory 6. The value string 254 is being processed, so it is necessary to finish the judgment process in the judgment circuit 3 by the end of the next cycle.If the judgment process in the 0 judgment circuit 3 determines that there is no sound, the code circuit 5 Input value string 256 in the circuit of
The determination circuit 3 instructs the encoding circuit 5 to reset before processing. Therefore, in this case, even if packet 1 in Figure 2 is not sent out and is discarded from memory, the beginning of packet 2 is encoded from the initial state after reset, so packet 1Φ information is not used for decoding. do not need.

FIG. 1(2) is a block diagram showing an embodiment of the decoding side circuit. In the same figure, 9 is the packet reception 2 public solution part (
10 is a memory for storing received packet data; 11 is a control circuit that reads information headers such as time stamps and controls the next packet to be reproduced; 12
is a decoding circuit, 13 is a noise generation circuit, and 14 is a decoding circuit 12.
and a selection circuit for the output of the noise generation circuit 13.

The receiving circuit 9 performs a packet receiving process according to the protocol, and stores the received packet in the memory IO. A packet control circuit 11 reads information headers such as time stamps from the memory 10 and controls appropriate reproduction timing of the packet. The decoding circuit 12 reads data from the mailbox 10 under control from the packet control circuit 11, decodes it, and outputs it to the selection circuit 14. When there is no packet to be reproduced, that is, when it is determined that there is no sound, the packet control circuit 11 causes the noise generation circuit 13 to generate noise, and controls the selection circuit 14 to select the output of the noise generation circuit 13. In this case, when decoding the first packet to be reproduced after the silent period, the decoding circuit 1.2 starts decoding after being reset. Since the encoding circuit 5 always resets and then encodes the next packet after the packet determined to be silent, the decoding side is also reset in the same way, so that the internal state is lost between the encoding circuit and the decoding circuit. be able to.

〔Effect of the invention〕

According to the present invention, even when transmitting packets by suppressing silent parts using high-efficiency speech encoding based on the principle of predictive differential encoding, correct encoding and decoding can be performed by performing reset control as described above. It can be carried out.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart explaining the operation of the circuit shown in FIG. 1. Explanation of symbols 1...Signal input terminal, 2...Circuit for calculating power etc., 3...Circuit for determining whether there is a sound or no sound, 4...Delay circuit, 5...Prediction difference code 6...Memory, 7...Packetization circuit (transmission circuit), 9...Packet reception 1-element processing unit (receiving circuit)
, 10...Memory, 11...Control circuit for controlling packets, 12...Decoding circuit, 13...Noise generation circuit, 14...Selection' circuit. Agent Patent Attorney Akio Namiki

Claims (1)

[Scope of Claims] 1) An identification circuit that receives a digital code sequence such as an audio signal and identifies whether the code sequence is voiced or silent for each code sequence of a certain time length (this is called a block); a predictive differential encoding circuit that inputs, encodes and outputs the digital code sequence in parallel; a memory that stores the encoded output from the predictive differential encoding circuit one block at a time; If the identified block is determined to be audible by the identification circuit, the block is read out from the memory and made into a packet, and the packet is compared to the packets sent before the packet and the packets to be sent after this. a transmitting circuit that adds a transmission time relationship display signal indicating a transmission time relationship to its header and transmits the same; and if the block is determined to be silent by the identification circuit, the block is not packetized; and a reset means for resetting the predictive differential encoding circuit immediately before the code sequence forming the head of the next block is input to the predictive differential encoding circuit, the transmitting side receiving a packet transmitted from the transmitting circuit. a receiving circuit that interprets the header and decomposes the packet; a decoding circuit that decodes the high-efficiency encoded signal by predictive differential encoding; and a decoding circuit that interprets the transmission time relationship display signal included in the header. If the code block of the received packet is continuous with the code block of the previously received packet, the code block of the received packet is input as is to the decoding circuit, and if the code block is not continuous, the code block of the received packet is A high-efficiency code packet transmission system characterized by having a control circuit on a receiving side that resets the circuit and then inputs the code sequence of the block to the decoding circuit.