JPH02181258A - Semiconductor integrated circuit device using neuro network and its production and neuro network device - Google Patents

Abstract

PURPOSE:To relieve the defects of a neuron learning circuit without deteriorating the overall degree of integration of a semiconductor integrated circuit device by separating the neuron learning circuit from a neuro network to use it in common and attaining such a constitution where the detects can be relieved for the neuron learning circuit. CONSTITUTION:A learning circuit system 999 is separated from each neuron 1 and used in common among the neurons 1, and a signal system 998 is neces sary for learning. In a neuro network enclosed by a broken line, the learning is performed normally as long as the system 999 is normal even when a defect is generated. Then a defective neuron is excluded. Since the defect of the learn ing system is relieved in advance, an erroneous learning signal is never transmit ted to the neuro network. The learning is carried out as follows. That is, the synapse weight value of the neuron of an Lm layer is fetched to the system 999 and then written into the original synapse after the weight value is changed. This operation is applied to each neuron of an Lm layer. The same process is carried out to the next Ln layer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device such as an electronic computer, and more particularly to an information processing device equipped with a neural network.

[Prior Art] As a typical neural network structure, pattern associative
or) network is known. Furthermore, the pack propagation method is known as a typical learning algorithm for pattern associative networks.

Nikkei Electronics August 10, 1987 for information on pattern associative networks and pack propagation methods.
The details are shown in P115 to P124 of No. 8 (No. 427).

The outline of the pattern associative network structure will be explained using FIG. 1 is a neuron, and the neuron is composed of one cell body 2 and a plurality of synapses 3. 9
is a signal line, and the arrows indicate the signal flow. An input signal input from the left side of the drawing is processed while propagating through the network and output from the right side of the drawing. Note that the traffic lights shown here are the signal paths when the network is normally operated, and do not indicate the flow of learning signals during learning. The flow of the learning signal will be described later. In this figure, each /1 (Ll to Ln) is composed of three neurons, but it may be composed of any number of neurons.

FIG. 3 is a schematic diagram for explaining a learning algorithm based on the pack propagation method, and shows one of the neurons 1 shown in FIG. 2. II.

I2.13 is the output signal from each neuron in the previous layer, and UT is the output signal of the neuron, which is input to the synapse of the neuron in the first layer. In this figure, solid lines indicate the flow of signals during normal operation, and broken lines indicate the flow of signals during pack propagation learning. Each synapse 3 is given a unique weight value W, and each input signal is given a weight value W.
Multiply.

This corresponds to the step of outputting that value. 4 indicates a step of calculating the sum of input values after being multiplied by the weight value W, and 5 indicates a step of outputting a function value f of the input values. Note that a sigmoid function and the like are known as the functional form of 5. 6 is a switch, which can be switched between normal operation and learning. 7 indicates a step of calculating a change in synaptic weight value 1d (n) during learning. D (n+1) is a learning signal from the next stage. Specifically, d(n)=aXf'(s)XIX (sum of D(n+1)) (1) is the formula. Here S is the output of step 4 and f
' is the differential value of the function value f in step 5 mentioned above. (2) is an input signal (II to I3) to the synapse, and a is a constant. 8 is a step of calculating the learning signal D (n) to the previous stage. D (n) is D (n)=W
Xd (n) Calculated using equation (2). By repeating the normal operation and learning operation described above, the weight value W of the synapse is changed by d (n), and the entire network is configured to realize the desired input/output correspondence.

As explained above, the pattern associative network structure and pack propagation learning algorithm have a simple structure and a simple algorithm, so they are not limited to computer simulations, and have the potential to be easily realized as semiconductor integrated circuit devices. There are advantages. That is, the third
In the figure, 3 is a multiplication circuit, memory circuit 4 is an adder circuit 5 is a memory circuit, 6 is a switch circuit 7 is a multiplier circuit, an adder circuit, and a memory circuit 8 can be easily implemented as a multiplication circuit. Furthermore, a major feature of this prior art is that it automatically eliminates neuron defects through learning when a device is fabricated using a semiconductor integrated circuit.

The advantages thereof will be explained below using the fourth @. 100 is a defective neuron, 101 is a cell body of the defective neuron, and 102 is a synapse of the defective neuron. 200 is a neuron in the previous stage of the defective neuron, 201 is a cell body, and 202 is a synapse. 300 is a neuron at the next stage of the defective neuron, 301. is the cell body. 3
02 is a synapse connected to the output of the defective neuron 100. The solid line shows the signal flow during normal operation, and the broken line shows the learning signal flow. Output OUT of defective neuron 100
Since is an abnormal value, the neuron 300 sets the synapse 3020 weight value W to O by repeating learning.

That is, the signal connection between the defective neuron 100 and the neuron 300 is separated by learning. This defect also affects the learning circuit system of the neuron 100, that is, 3 in FIG.
, 4, 6, 8, 7 (3, 4 are also used for normal operation,
If there is no defect in the common circuit system), the learning signal D (n) to the previous stage is also transmitted normally. Therefore, the neurons 200 in the previous stage can also learn normally. In summary, in such a defect mode, that is, if the learning system is normal even if the output value of the defective neuron 100 is abnormal, the entire network will perform learning normally and the defective neuron 1
00 can be automatically excluded. This is equivalent to neurons automatically correcting defects through learning. Therefore, when this network structure and algorithm are incorporated into a device using a semiconductor integrated circuit, the above-mentioned defects are automatically repaired by learning, and the yield of the device is greatly improved.

[Problems to be Solved by the Invention] On the other hand, a disadvantage is when there is a defect in the learning circuit system of the defective neuron 100. Even in this case, as described above, the next stage neuron 300 sets the weight value W of the synapse 302 to O by learning. However, since the preceding neuron 200 receives an incorrect learning signal from the defective neuron 100, it is very difficult to perform correct learning. Therefore, in such a defect mode, the defect cannot be automatically repaired. For this reason, the normal 1
Even if the device is made into a semiconductor chip with a size of 1 cm, the yield will be 1.
It is difficult to approach 00%.

Furthermore, when realized with wafer scale integrated circuits,
Since the total area of the learning circuit system becomes very large, the improvement in yield is almost equal to 0%.

FIG. 5 is a schematic diagram of the device formed on a semiconductor wafer. , 10 is a wafer, and 11 is a neuron made by a semiconductor manufacturing process. neuron 11
A shaded portion 12 is a learning circuit system (including a common circuit system during normal operation). The learning circuit system 12 occupies nearly 1/2 of the area of the two-needle 11. wafer 1
The dimensions of 0 are 5 inches, and 400 0.4cm x 0.4cm two-kneelons 11 are placed thereon. For this example,
The total area A of the learning circuit system is 32 cm". As explained earlier, the yield is determined by the total area of the learning circuit system, so yield calculation Y = exp (-DXA) (3) Equation Y2 Yield D: Defect density A: The yield rate is almost 0% from the area.Here, the defect density is set at 1 piece/cm2, but as a way to solve the problem, there is a method of providing multiple learning circuits 12 in anticipation of the yield rate. The outline thereof is shown in FIG. 6. 10 is a wafer, 12' is a learning circuit, and 12' is a circuit 3, 4, 6, 7, . . . in FIG.
It is 8. Further, 13 in FIG. 6 is a circuit other than the learning circuit system, and is equal to 5 in FIG. 3. Neuron 1 is constructed by combining 12' and 13 as a pair.

Here, the number of learning circuits 12' is greater than the required number N of neurons. By selecting N learning circuits 12' having internal focal defects and connecting them to the circuit 13 as a pair, it is possible to make the learning circuits of all neurons defect-free. A method for relieving defects by multiplexing circuits is known, for example, from Journal Electronics, June 1, 1987 (vol. 422), issue P141 to P161.

However, this method causes the following problems.

That is, in order to realize the number of neurons N, the learning circuit 1
It becomes necessary to make the number of 2' larger than N, which reduces the number of neurons that can be realized on a wafer or chip.

The purpose of the present invention is to solve the above-mentioned problems.
The goal of neuronetworks is to (1) execute learning normally even if a defect occurs in the learning circuit system, and (2) convert it into a highly integrated semiconductor integrated circuit device.

[Means for solving the problem] In order to achieve the above object, the present invention has the following features: 1. The learning circuit system is separated from each two-needle system and shared, and the separated learning circuit system is constructed by a device capable of repairing defects.

[Operation] The concept of the network according to the present invention is shown in FIG. 99
9 is a learning circuit system separated from each neuron 1 and shared, and 998 is a signal system for learning. The area inside the broken line is the same as the network structure explained earlier in FIG. 2, but each two-neelon 1 does not have a learning circuit. As described above, the neural network within the broken line performs learning normally and eliminates the defective neuron if the learning circuit system 999 is normal even if a defect occurs. On the other hand, in the present invention, since defects in the learning circuit are repaired in advance, an erroneous learning signal is not transmitted to the neural network.

Learning is performed, for example, as follows. That is, the synapse weight value of the Lm layer neuron is taken into the learning circuit system 999, and after the weight value is changed, it is written to the original synapse. This is executed for each neuron of LmJl, and the same process is then executed for the Ln layer.

Furthermore, as shown in FIG. 3, all the neurons 1 are composed of a common circuit, so that the learning circuit can be shared. The learning circuit system 999 according to the present invention can be constructed only from circuits 3, 4, 6, and 7.8 in FIG. 3 and a control circuit that commonly allocates these circuits to each neuron. Therefore, the degree of integration can be increased not only in the case of FIG. 6 but also in the case of FIG. 5.

On the other hand, although all neurons are composed of common circuits, it is difficult to make the circuits necessary for normal operation (ie, the area within the broken line in FIG. 1) common in the same way as the learning circuit. This is because if N neurons are shared, for example, into one, the processing speed of the entire network will be reduced to 1/H. For example, if N=1000, the processing speed of the entire network decreases to 1/1000. With this level of processing speed, network simulation on a computer can be sufficient to achieve this without using a semiconductor integrated circuit as a device.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 7 is a diagram for explaining an embodiment of a shared learning circuit system 999 and a neuron 1' from which the learning circuit is removed. For details of the functional blocks in this figure, see Section 8.
This will be explained later using FIGS. Further, an embodiment of a defect relief method for a learning circuit will be described later. 999 is a shared learning circuit, and 1' is a neuron from which the learning circuit has been removed. Synapse (multiplication circuit and memory circuit) 3.
Addition circuit 4. The memory circuit 5 is the same as that shown in FIG.

20 is a multiplication and addition circuit that multiplies the input signals 11 to In to each synapse by the weight value W of the synapse and calculates the sum thereof. This is equivalent to circuits 3 and 4. 21 is a memory circuit 6 which outputs the differential value of the function value f described in FIG.
22 is a multiplication circuit and an addition circuit for calculating D (n) and d (n) in FIG. Circuit 21,22 is equal to 7°8 in FIG. 20, 21, and 22 are circuits commonly used for each neuron, and 23 is a control circuit that oversees sequential assignment to each neuron.

20, 21, and 22 are circuits that are small enough to be included in the neuron shown in FIG. 3, and the learning circuit 999, including the control circuit 23, is about 0.5 cm2. Therefore, the yield of the learning circuit 999 is about 60% according to equation (3). Since the network does not depend on defects, that is, the yield is 100%, the yield of the entire semiconductor integrated circuit device is equal to the yield of the separated and shared learning circuit 999 of 60%. When this embodiment is applied to a wafer scale integrated circuit device, it is possible to increase the yield of the wafer scale integrated circuit to 60% even without a defect relief structure. By simply separating and sharing the learning circuit, the yield can be dramatically improved compared to the conventional configuration shown in FIG. In addition, lx and Wx in the figure are the output values of other neurons,
Shows wires connected to synaptic weight values of other neurons.

FIG. 8 is a diagram for explaining in detail 3 and 4.5 in FIG. 7. A multiplier 1100 calculates the product IXW)p/ of the input signals 11 to 3 to the synapse 3 and the weight values W stored in the respective weight value registers 1111. The multiplication results are sequentially selected by the selector circuit 1112, and the adder 111
3 is added sequentially. The added results are then shown in Table I
10 circuit 1114. The function value f corresponding to the result of addition here is the f function table (memory) 111
The value f selected from 5 and 9 becomes the output of the cell body.

FIG. 9 is a diagram for explaining 20 to 23 in FIG. 7 in detail. The output signals 11 to In of each neuron and the weight values W1 to Wn of each synapse are connected to the selector circuits 1010 and 1011. Select signal 2000.
2001 is output from the address generation circuit 1000.degree. 1001 in the control circuit 23. Selector circuit 10
The output signal of the neuron selected at 10°1o11 and the weight value of the synapse are respectively stored in the register circuit 1007.1.
012, and the multiplier 1008 calculates the product TXW. Note that 1013 is a buffer circuit for writing and reading synaptic weight values. Multiplier 10
The multiplication results of 08 are sequentially added by an adder 1009. The added result corresponds to S in equation (1). The addition result S is input to the table I10 circuit 1014, and the function f' corresponding to the addition result S is selected from the f' function table 1015. Multiplier 1017 is for executing the multiplication of equation (1) shown above. The multiplication result d (n) is input to an adder 1016 and added to the weight value W before change held in the weight value register 1012. The added result is the new synaptic weight value W after the change, that is, after learning. The changed W is stored in the weight value register 1012. R/
Through the W buffer 1013 and the selector circuit 1011,
It is written to each synapse weight value register (1111 in FIG. 8) in the network. Note that the multiplier 1o20 is a multiplier for calculating the product of the value W of the weight value register 1012 and d(n), and executes the multiplication shown in equation (2). Adder 1021 and register 1022 are multiplier 102o
The sum of D (n) is calculated by sequentially adding the results of D (n) until learning of neurons in the next layer is executed.
) is used to hold the total value. When the next layer learning is performed, the value of D(n) is in register 10
Transferred to 19. The above is the circuit configuration of 20.21.22. 23 is a control circuit for controlling the learning (weight value changing process) described above. The control is executed in synchronization with the clock signal input from the particle 1o05. Note that although this figure shows an example in which a clock signal is supplied from outside the control circuit 23, a clock signal oscillator may also be provided in the control circuit 23. 1004 is a distribution circuit for supplying a clock signal to each circuit block of the control circuit 23. A timing signal is generated by the timing signal generation circuit 1003 using this clock signal. According to the timing signals, the series of learning processes described above, namely data transfer to registers, sequential addition, and multiplication, are performed. In addition, in this figure, timing signal 2
Although it is specified that 000 is only connected to circuits 20, 21 and 22, it is actually connected to each circuit block. 10
02 is an interface circuit 10 for connection with an external circuit. External control signals etc. input from the input/output signal pin 1006 are decoded by the 170 circuit 10o2 and sent to the I/O signal pin 1006.
From the 10 circuit 1002, the synapse address generation circuit 10
00, neuron output signal line address generation circuit 1001
, transmits a control signal to the timing signal generation circuit 1003. Synapse address generation circuit 1000. In accordance with the select signal transmitted from the neuron output signal line address generation circuit 1001, the selection of WORK and W described above is executed.

An example of a defect relief structure for a learning circuit will be described with reference to FIG. 999' is, for example, the separated and shared learning circuit shown in FIG. 9. In this embodiment, the learning circuit 999'
is set up in five layers.

997 is a switch circuit which selects one of the outputs d(n) of the five-fold learning circuit 999'. After the manufacturing process of the device is completed, each learning circuit 999' is inspected, and the output of the learning circuit 999' determined to be defect-free is selected by the switch circuit 997. When the yield of one learning circuit 999' is 60% as described above, the probability that at least one of the quintuple learning circuits is defect-free, that is, the yield of the learning circuit is 99%. It is possible to further increase the yield by further increasing the degree of multiplicity. Note that since the learning circuit 999' is about 0.5 cm", even if five pieces are multiplexed, the total area is only about 2.5 cm2, and including the switch circuit 997, it is about 3 cm".

This is only about 5% of the device formation area of a 5-inch wafer.

FIG. 11 shows an example of the relationship between a neuron network circuit formed on a wafer and a learning circuit. 10 is a wafer, and 800 is a learning circuit 999' and a switch circuit provided multiplexed in FIG. 10. This is a learning circuit system consisting of 997.

1' is a neuron without a learning circuit shown in the lower part of FIG.

In the above embodiment, a case has been described in which a defect in a learning circuit is repaired in a structure in which a learning circuit is formed simultaneously with the formation of neurons on the same wafer.

On the other hand, it is also possible to remedy defects in the learning circuit by a so-called rehybrid method. FIG. 12 shows one embodiment. 10 shows a cross section of a wafer on which a network of neurons without a learning circuit is formed. 8
00' shows a cross section of a semiconductor integrated circuit chip on which a learning circuit 999' is formed, but the learning circuits are not provided in multiple layers. Chip 800' mounted on wafer 10
As shown in FIG. 13, defect-free chips are selectively cut out from a wafer in which only a plurality of chips 800' are formed. The electrical connection between the wafer 10 and the chip soo' shown in FIG. 12 is performed, for example, by a flip-chip connection method using solder as shown at 30. The size of the chip 800' is 1 cm". Another embodiment in which the learning circuit 999 is defect-free will be described with reference to FIG. The wafer 10 on which the neuron network is formed is mounted on the substrate 32. The connection between the substrate 32 and the wafer z11Q is made through wire bonding 31, and the connection between the substrate 32 and the computer 500 is are electrically connected by the connector 33 and the cable 34. In this embodiment, the learning circuit 999 is realized by the computer 500 and the program on the computer 500, so that the learning circuit system can be made defect-free. In this embodiment, in addition to transmitting learning signals from the computer 500 via 31, 32, 33 and 34, input/output signals of the neural network are also transmitted.

In the above, embodiments have been mainly shown based on one chip or one wafer. Further, the above-mentioned wafer 10 is a wafer on which a learning system 80o which is separated and shared with the neurons according to the present invention described above is mounted. wafer 10
10 or more sheets are stacked vertically. According to this embodiment, since the wafers can be mounted very close to each other, large-scale neuron circuits can be mounted at extremely high density. In this embodiment, the learning circuit 800 is provided for each wafer 10, but one learning circuit 800 may be provided for a plurality of wafers. Furthermore, the learning circuit 800 may be implemented with a learning circuit chip 800' using the hybrid technology shown in FIG.

Furthermore, the computer 500 shown in FIG. 14 may be connected to the computer 500 shown in FIG. 14 via the connector 33 provided on the board 32, and learning control may be performed using the computer 500.

Incidentally, as a method for stacking wafers vertically and electrically connecting the wafers, for example, a technique disclosed in Japanese Patent Application Laid-Open No. 2662/1998 is used.

[Effects of the Invention] As explained above, according to the semiconductor integrated circuit device using the neuronet according to the present invention, it is possible to make defect repair possible without impairing the high degree of integration of the entire device including the learning circuit system. This is effective in converting large-scale neuronets into semiconductor devices.

[Brief explanation of the drawing]

Figure 1: Diagram for explaining the basic idea of the present invention, Figure 2: Diagram for explaining the prior art, Figure 3...
- Diagram for explaining the prior art, FIG. 4... A diagram for explaining the learning process when there is a defective neuron. Fig. 5: A diagram for explaining a neuronet semiconductor integrated circuit device according to the prior art. Fig. 6: A diagram for explaining a defect relief technique according to the prior art. Fig. 7: The present invention. FIG. 8...A diagram to explain FIG. 7 in detail. FIG. 9... A diagram to explain FIG. 7 in detail. FIG.・
・A diagram for explaining one embodiment for relieving a defect in a learning circuit, FIG. 11... A diagram for explaining one embodiment of the present invention, FIG. 12... A diagram for explaining one embodiment of the present invention A diagram for explaining one embodiment, FIG. 13... A diagram for explaining the embodiment in FIG. 12, FIG. 14... A diagram for explaining one embodiment of the present invention. FIG. 15: A diagram for explaining one embodiment of the present invention. Explanation of symbols 1...Neuron, 2...Cell body, 3...Step of multiplying weight values (Sibunas), 4...Step of calculating sum, 5...Step of calculating function value, 6...
- Switch, 7... Step of calculating a change value of the weight value, 8... Step of calculating a learning signal, 9... Signal path, 10... Wafer, 11... Neuron according to conventional technology, 12.12'...Learning circuit according to conventional technology, 13...Circuit other than neuron learning circuit, 2
0... A circuit that multiplies the weight value according to the present invention and calculates the product, 21... A circuit that outputs a differential value of a function value, 22...
- Circuit for calculating a learning signal, 23... Control circuit, 30... Flip chip, 31... Wire bonding, 32... Board, 33... Connector, 34
... Cable, 100 ... Defective neuron, 101
...Cell body of defective neuron, 102...Synapse of defective neuron, 200...Neuron in front of defective neuron, 201...Cell body of neuron in front of defective neuron, 202...Synapse of defective neuron Synapse of the previous neuron, 300...Neuron next to the defective neuron, 301...M cell body of the neuron next to the defective neuron, 302...Neuron next to the defective neuron Output of the defective neuron Connected synapses, 500... Computers, 800°800'.
...A learning circuit according to the present invention that can be separated, shared, and capable of relieving defects, 997...Selection circuit, 998...Learning signal, 999...A structure that can be separated, shared, and capable of relieving defects is provided. Learning circuit, 999'... Separate and share,
Multiple learning circuits, 1100...multipliers, 111
1... Weight value register, 1112... Selector circuit, 1113... Adder, 1014.1114... Cable I10 circuit, 1015.1115... Function table, 1000° 1001... Address generation circuit ,1
002... I10 circuit, 1003... Timing signal generation circuit, 1004... Clock distribution circuit, 100
5... Clock signal input pin, 1006... External signal input/output bin, 1007.1012, 1018, 101
9゜1022...Register, 1010.1011...
・Selector circuit, 1008, 1017.1020...
Multiplier, 1009, 1016, 1021...Adder 2
000.2001. Select signal, 2002...timing signal. L7 No.? Figure 4th Rod 8 Figure 7 Eye 7 Figure 10

Claims (11)

[Claims] 1. 1. A semiconductor integrated circuit device using a neural network, characterized in that a neuron learning circuit is separated from a neural network and shared, and the learning circuit is configured to be capable of repairing defects. 2. A semiconductor integrated circuit device using a neuronetwork, characterized in that the number of learning circuits is less than or equal to the number of neurons. 3. A semiconductor integrated circuit device comprising a first circuit that can operate even if there is a defect in the circuit, and a second circuit that cannot operate if there is a defect, wherein only the second circuit is defective. A semiconductor integrated circuit device characterized by having a structure for relieving. 4. A semiconductor integrated circuit device in which a plurality of neural circuits that do not include a learning circuit are formed, wherein the learning circuit that is commonly used by the plurality of neural circuits and has a structure capable of repairing defects is used for the plurality of neural circuits. A semiconductor integrated circuit device characterized in that it is formed simultaneously with a circuit. 5. A semiconductor substrate on which a plurality of neurocircuits without a learning circuit are formed is mounted with another chip on which a learning circuit that is commonly used by the plurality of neurocircuits and is defect-free is formed. Semiconductor integrated circuit device. 6. A neural network device comprising a semiconductor integrated circuit device in which a plurality of neural circuits without a learning circuit are formed and a computer electrically connected to the semiconductor integrated circuit device, the neural network device being configured to perform learning of the neural circuits by the computer. and a neuronetwork device that is operated by a program on the computer. 7. The first step is to form elements, wiring, electrode pads, and protective films on the semiconductor substrate, the second step is to repair defects in circuit parts that do not work if there are defects, and the learning algorithm allows the circuit to work even if there are defects. A method for manufacturing a semiconductor integrated circuit device using a neuronetwork, comprising a third step of separating defective neurons in a possible circuit. 8. A first step of mounting another semiconductor integrated circuit chip on which a learning circuit used for learning of the plurality of neurons is formed on a semiconductor substrate on which a plurality of neurons without a learning circuit are formed, and mounting. A method for manufacturing a semiconductor integrated circuit device using a neural network, comprising a second step of separating defective neurons from the plurality of neurons through learning by the semiconductor integrated circuit chip. 9. A structure in which a plurality of semiconductor wafers on which a plurality of neurons without a learning circuit are formed are stacked vertically,
A semiconductor integrated circuit device using a neural network, characterized in that a learning circuit capable of repairing defects is formed simultaneously with the plurality of neurons, one for each of the plurality of wafers or one for each of the plurality of wafers. 10. It has a structure in which a plurality of semiconductor wafers on which a plurality of neurons without a learning circuit are formed are stacked vertically, and another chip on which a defect-free learning circuit is formed is commonly used for the plurality of neurons. A semiconductor integrated circuit device characterized in that one semiconductor integrated circuit device is mounted on each of the plurality of wafers or on each of a plurality of wafers. 11. It has a structure in which a plurality of semiconductor wafers on which a plurality of neurons are formed without a learning circuit are stacked vertically, and a computer is electrically connected to the plurality of wafers, and the learning of the neurons is performed by the computer and the computer. A neuronetwork device characterized by being operated by the above program.