JPH02179966A - Checking device for pll phase comparing waveform - Google Patents

Abstract

PURPOSE:To check values in a short time on a real time basis by converting a counted value corresponding to the length of a phase comparing pulse DELTAphiinto an analog signal G, and respectively holding its maximum value and minimum value. CONSTITUTION:The device is the checking device to measure the minimum length and maximum length of the phase comparing pulse DELTAphi outputted from a PLL phase comparing circuit, and a reference oscillator 15, a counting circuit 16, which counts an output pulse Fc of the reference oscillator 15 with the phase comparing pulse DELTAphi as a gate, and a digital/analog converter 18, which converts the counted value of the counting circuit 16 into the analog signal G, are provided. Further a maximum value holding circuit 19 and a minimum value holding circuit 20, which respectively hold the maximum and minimum values of the analog signal G, and a display means 25, which simultaneously displays the held maximum and minimum values, are provided. Thus the minimum length and maximum length of the phase comparing pulse can be promptly and quantitatively measured.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is based on PLL (Phase Locked L).
The present invention relates to an inspection device that measures the minimum length and maximum length of a phase comparison pulse output from a phase comparison circuit of an .

[Summary of the invention]

The present invention provides an inspection device for measuring the minimum length and maximum length of a phase comparison pulse output from a PLL phase comparison circuit, which includes a reference oscillator and a counter that counts output pulses of the reference oscillator using the phase comparison pulse as a gate. circuit and
A digital-to-analog converter that converts the count value of this counting circuit into an analog signal, a maximum value hold circuit and a minimum value hold circuit that hold the maximum value and minimum value of the analog signal, respectively, and a maximum value and a minimum value held by these circuits. By providing a display means that simultaneously displays the minimum value,
The minimum length and maximum length of the phase comparison pulse can be measured quickly and quantitatively.

[Conventional technology]

P L L (Phase Locked Loop)
This type of servo circuit is commonly used in video tape recorders, optical disc playback devices, etc., as it is capable of extremely high-precision control, and advances in semiconductor technology have made it possible to mass-produce inexpensive circuits. It has become so.

FIG. 2 shows a so-called compact disc (CD) playback device as a type of optical disk playback device using such a P L,L type servo circuit. 2) is a spindle rotation motor, and (3) is an optical pickup.The RF multiplied signal as a reproduction signal generated by this optical pickup (3) is converted into a binary signal by a waveform shaping circuit (4). After that, the signal is supplied to a synchronization detection circuit (5) and a PLL circuit (6).

This PLL circuit (6) is itself a phase comparison circuit.

It has a built-in low-pass filter and a voltage controlled oscillator (VCO) to generate a pit clock signal Fb that is synchronized with the RF multiplied signal, and this bit clock signal Fb is sent to a synchronization detection circuit (
5), digital signal processing circuit (force and phase comparison circuit (8)
) to one input terminal of the Its synchronization detection circuit (5
) extracts a frame synchronization signal from the input binary signal, and its digital signal processing circuit performs EFM demodulation on the binary signal and then performs processing such as error correction.

Further, the reference clock Fo of a predetermined frequency output from the reference oscillator (9) is supplied to the other input terminal of the phase comparison circuit (8), and the reference clock FO and the reference clock Fo are supplied from the output terminal of the phase comparison circuit (8). A phase comparison pulse Δφ corresponding to the phase difference with the bit clock Fb is output. This phase comparison pulse Δφ is converted into a DC signal by a low-pass filter (or charge pump circuit) (10) and is supplied to a drive circuit (11) of a spindle rotation motor (2).

In the example in FIG. 2, the optical disc (1) is rotated by the spindle rotation motor (2) so that the pit clock Fb output from the PLL circuit (6) is synchronized with the reference clock Fo output from the reference oscillator (9). It is made to look like it is being rotated. Therefore, optical pickup (3) → waveform shaping circuit (4) → PLL circuit (6) → phase comparison circuit (8)
)→Low pass filter (lO)→Drive circuit (11)
→ Spindle rotation motor (2) → Optical disk (1) loop also constitutes a PLL type servo circuit.

In the example of FIG. 2, when the phase of the pit clock Fb is slower than the phase of the reference clock Fo, the phase comparison pulse Δφ output from the phase comparison circuit (8) is <2.5V as shown in FIG. 3A. It becomes a pulse signal within the range of ~5■,
If the phase of the pit clock Fb is ahead of the phase of the reference clock Fo, as shown in FIG. 3B, <2.
It becomes a pulse signal within the range of 5V to 0■.

In compact disc playback devices, optical discs (
1) is constant linear velocity CL V (Constant Li
When the optical pickup (3) is on the inner circumferential side of the optical disk (1), the rotational speed is about 500 r, ρ, m, whereas the optical pickup ( 3) is on the outer circumferential side of the optical disk (1), the rotational speed is 200r,
p, s. Therefore, when the optical pickup (3) is on the inner circumferential side of the optical disk (1), the phase of the bit clock Fb is slightly behind the reference clock Fo, and the waveform of the phase comparison pulse Δφ is as shown in FIG. 3A. On the other hand, when the optical pickup (3) is located on the outer peripheral side of the optical disc (1), the phase of the bit clock Fb is the reference clock F.

The waveform of the phase comparison pulse Δφ becomes as shown in FIG. 3B.

[Problem to be solved by the invention]

When manufacturing equipment that incorporates a PLL type servo circuit, it is necessary to inspect whether the PLL is operating normally, and one of the inspection items is the output from the phase comparison circuit of the PLL. There is a measurement of the minimum and maximum length of the phase comparison pulse to be used. This is mainly because the difference between the maximum length and the minimum length corresponds to so-called PLL jitter, so it is necessary to manage the maximum length and minimum length so that they fall within predetermined standard values.

Conventionally, in order to measure the length of the phase comparison pulse Δφ of the PLL shown in the example in FIG. 2.5v as shown in Figure 3A as pulse Δφ
〜5■ so as to obtain a pulse signal within the range,
The waveform of the pulse signal was visually observed using an oscilloscope. In this case, when the pulse signal is synchronized at the rising edge, its waveform becomes as shown in Figure 3C, and the minimum length To and maximum length T1 of the phase comparison pulse Δφ can be read from the scale of the oscilloscope. Can be done.

However, reading the waveform of an oscilloscope visually is not quantitative due to variations in measurement values depending on the operator, and if the waveform of the oscilloscope cannot be read well, the phase comparison pulse Δφ must be generated again and observed. There was an inconvenience that the inspection required time.

In view of this, an object of the present invention is to enable rapid and quantitative measurement of the minimum and maximum lengths of phase comparison pulses.

[Means to solve the problem]

The PLL phase comparison waveform inspection device according to the present invention is, for example, as shown in FIG. 1, in which the reference oscillator ( 15) and its reference oscillator (15) using its phase comparison pulse Δφ as a gate.
a counting circuit (16) that counts the output pulses Fc of the counting circuit (16), a digital-to-analog converter (18) that converts the count value of the counting circuit (16) into an analog signal G, and the maximum and minimum values of the analog signal G. a maximum value hold circuit (19) and a minimum value hold circuit (20) that respectively hold the
A display means (25) for simultaneously displaying the held maximum value and minimum value is provided.

[Effect]

According to the present invention, the count value corresponding to the length of the phase comparison pulse Δφ is converted into the analog signal G, and the maximum and minimum values of the converted analog signal G are held, respectively. In other words, the maximum length and minimum length of the phase comparison pulse Δφ are respectively held.

Therefore, the inspection can be performed in real time and in a short time without generating the phase comparison pulse again without being able to read the maximum and minimum lengths.

Furthermore, since the held maximum and minimum values are displayed simultaneously, the measurement is quantified without variations in the reading of the maximum and minimum values by operators.

〔Example〕

Hereinafter, an embodiment of a testing device for a PLL phase comparator circuit according to the present invention will be described with reference to FIG. In this example, the present invention is applied to a testing device for a PLL phase comparator circuit for driving a spindle rotation motor of a compact disc playback device.

FIG. 1 shows the inspection device of this example, and in this FIG.
(12) is an input terminal, and a phase comparison pulse Δφ as shown in FIG. 3A is supplied to this input terminal (12) from the outside. This supplied phase comparison pulse Δφ consisting of a pulse signal in the range of 2.5V to 5V is transferred to a level converter (13).
After converting it to a CMOS level by and the other input terminal of the timing generator (17) are supplied with a frequency of 10 M from the reference oscillator (15).
A clock pulse Fc of Hz is supplied.

Then, the output terminal of the AND gate (14) outputs a clock pulse Fc gated by the level-converted phase comparison pulse Δφ, and the gated clock pulse Fc is sent to the count signal input terminal of the counter (16). supply to. The timing generator (17)
The control signal J2 becomes a high-level "IJ" pulse at the falling timing of the level-converted phase comparison pulse Δφ, and the control signal J5 becomes a high-level "1" pulse a little later than the control signal J2. , a control signal J that becomes high level rlJ at approximately 0.5 second intervals, and the control signal J.

The control signal J4, which becomes a high level "1" pulse a little earlier, is generated.

(18) indicates a digital/analog CD/A) converter, and this D/A converter (18) holds the count value of its counter (16) at the timing when the control signal J2 becomes high level "1". After converting this held count value into an analog signal G, this analog signal G is sent to a peak hold circuit (19) and a bottom hold circuit (20).
supply to. Immediately after the D/A converter (18) holds the count value of the counter (16), the count value of the counter (16) is cleared by the control signal J. In the peak hold circuit (19) and the bottom hold circuit (20), the control signal J generated by the timing generator (17) is within approximately 0.5 seconds, which is the interval at which the pulse of high level "1" occurs. The maximum and minimum values of the analog signal G at are held respectively.

(21) and (22) are sample/hold (S/
H) circuits and these sample/hold circuits (21
) and (22) hold the analog signals held in the peak hold circuit (19) and the bottom hold circuit (20), respectively, at the timing when the control signal J4 becomes high level "1". Immediately after these sample/hold circuits (21) and (22) hold the maximum analog signal and minimum analog signal within approximately 0.5 seconds, the peak hold circuit (19) and The values of the analog signals held in the bottom hold circuits (20) match the values of the analog signals G output from the D/A converter (18). Therefore, the peak hold circuit (19) and the bottom hold circuit (20) hold the maximum and minimum values, respectively, for approximately 0.5 seconds until the control signal J becomes high level "1" again.

The maximum value analog signal and minimum value analog signal held in the sample/hold circuits (21) and (22), respectively, are sent to an analog two-needle voltage meter (25) via buffer circuits (23) and (24), respectively. supply to. This analog two-needle voltage meter (25) has a front needle (
26) and a red needle (27), the indicated value of the front needle (26) corresponds to the minimum value analog signal output from the sunfur/hold circuit (22), and the indicated value of the red needle (27) This is done so as to correspond to the maximum value analog signal output from the sample/hold circuit (21). In addition, the display section of the analog two-needle voltage meter (25) shows, for example, lμ.
A scale in units of s is provided, and the red needle (27) and front needle (2
The indicated values of 6) are the maximum length and minimum length of the phase comparison pulse Δφ within approximately 0.5 second intervals, respectively.

According to this example, the maximum length and minimum length of the phase comparison pulse Δφ during approximately 0.5 seconds at intervals of approximately 0.5 seconds are the red needles (27) of the analog two-needle voltage meter (25), respectively. and can be directly read as the indicated value of the front hand (26) at the same time. Therefore, there is an advantage that there is no variation in the reading of the maximum length and minimum length by the operator, and the measurement can be made objective and quantified quantitatively.

Furthermore, according to this example, the maximum length and minimum length of the phase comparison pulse Δφ are each held after being converted to an analog signal, so the measured value does not become unreadable and the phase comparison pulse Δφ is re-inputted. This has the advantage that the test can be performed in real time and in a short time because there is no generation of data.

In the above-mentioned embodiment, the held maximum value analog signal and minimum value analog signal were each displayed by the analog two-needle voltage meter (25), but the present invention is not limited to this, and these maximum value analog signals The signal and the minimum value analog signal may each be converted back into digital signals and displayed simultaneously on a digital voltmeter or the like.

As described above, the present invention is not limited to the above-described embodiments, and it goes without saying that various configurations may be adopted without departing from the gist of the present invention.

〔Effect of the invention〕

According to the PLL phase comparison waveform inspection device according to the present invention, after converting the length of the phase comparison pulse into an analog signal, the maximum value and minimum value of this analog signal are held respectively, so that the phase There is the advantage that the minimum and maximum lengths of comparison pulses can be determined quickly and quantitatively.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of a PLL phase comparison waveform inspection device according to the present invention, Fig. 2 is a block diagram showing an example of a PLL circuit, and Fig. 3 shows the phase comparison pulse of the example shown in Fig. 2. FIG. (15) is the reference oscillator, (16) is the counter, (18)
is a digital-to-analog converter, (19) is a peak hold circuit, (20) is a bottom hold circuit, and (25) is an analog two-needle voltage meter. Agent Ito Sadado Matsukuma Hidemori PLL Eguchi Michino - Child 2nd figure

Claims (1)

[Claims] An inspection device for measuring the minimum length and maximum length of a phase comparison pulse output from a phase comparison circuit of a PLL, comprising: a reference oscillator; and an output pulse of the reference oscillator using the phase comparison pulse as a gate. a counting circuit for counting; a digital-to-analog converter for converting the count value of the counting circuit into an analog signal; a maximum value hold circuit and a minimum value hold circuit for holding the maximum value and minimum value of the analog signal, respectively; A PLL characterized by being provided with display means for simultaneously displaying a held maximum value and a held minimum value.
Phase comparison waveform inspection device.