JPH0217987B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a separation circuit for separating and extracting high-frequency signal components and low-frequency signal components from an input video signal to be processed, and high-frequency signals separated from each other from the separation circuit. The present invention relates to a video signal processing circuit including a noise suppression circuit that operates on one of a signal component and a low frequency signal component.

U.S. Pat. No. 3,715,477 discloses a video signal processing circuit of the above-mentioned type for use in a television camera. In this conventional video signal processing circuit, a noise suppression circuit suppresses high frequency video signal components. At the same time, small-amplitude high-frequency video signals were suppressed by a simple amplitude selection circuit.

An object of the present invention is to provide a video signal processing circuit of this type particularly suitable for use in television receivers.

Therefore, the video signal processing circuit of the type mentioned at the beginning according to the present invention is a circuit in which the noise suppression circuit operates on low frequency signal components, and has a delay circuit and a coupling circuit, and the coupling circuit operates on low frequency signal components. This is characterized by the provision of a comb-shaped filter that adds the output signal of the delay circuit to the frequency signal component.

The inventors of the present invention first discovered that when reproducing video signals, low frequency noise components are the most troublesome and, moreover, essentially cannot be suppressed by a simple amplitude selection circuit. I found out.

However, it should be noted here that the use of a comb filter having a delay circuit in a noise suppression circuit is known per se from U.S. Pat. No. 4,058,836, but the noise suppression circuit according to the present invention Although it operates only on the low frequency signal components of the video signal, the number of delay circuits used can be considerably reduced if necessary, and such a reduction in the number of delay circuits used is particularly important in television receivers. That's true.

The invention will be explained in detail below by way of example embodiments with reference to the drawings.

First, an example of a schematic configuration of a video signal processing circuit according to the present invention is shown in FIG. In the illustrated schematic configuration, the video signal supplied to the input terminal 1 of the separation circuit 3 is divided into a low frequency signal component and a high frequency signal component, and these are taken out from the output terminals 5 and 7, respectively. For this purpose, in the separation circuit 3, the input terminal 1
A low-pass filter 9 is disposed between the input terminal 1 and the output terminal 5, and a delay time C that is the same as the delay time of the low-pass filter 9 is provided between the input terminal 1 and the output terminal 7. A delay line 11 for passing an input video signal having a width of 100 nm and a subtraction circuit 13 for subtracting the wave output signal of the low-pass filter 9 from the delayed output video signal are sequentially arranged. As a result, only the high frequency signal components of the input video signal appear at the output end 7. Note that the cutoff frequency of the low-pass filter 9 is selected to be approximately equal to 1MHz for black and white video signals, and is selected to be approximately equal to 1MHz for color video signals.
It is preferable to select approximately equal to 500KHz.

Next, the high frequency signal component taken out from the output end 7 is directly supplied to the input end 15 of the adding circuit 17, and the low frequency signal component taken out from the output end 5 is fed to a noise filter configured in the form of a comb filter. The signal is supplied to the other input terminal 20 of the adder circuit 17 via the suppressor circuit 19 .

The noise suppression circuit 19 has an input terminal 23 connected to the output terminal 5 of the separation circuit 3 and an output terminal 25.
The analog/digital converter 29 is connected to the input terminal 20 of the adder circuit 17 and the input terminal 27 of the analog/digital converter 29.
The output end 31 of the digital converter 29 is the output end 3
7 to the input terminal 3 of the digital-to-analog converter 41
Input terminal 3 of digital delay circuit 35 connected to 9
3, and the output terminal 43 of the digital-to-analog converter 41 is connected to the other input terminal 45 of the coupling circuit 21.

In order to properly suppress noise, as detailed in the above-mentioned U.S. Pat. Image signal components and noise components are separated according to the magnitude of the components.

Therefore, in the coupling circuit 21, the input terminal 23 of the coupling circuit 21 is connected to the input terminal 4 of the subtraction circuit 49.
7, and the other input terminal 45 is connected to the other input terminal 51 of the subtraction circuit 49. The output terminal 53 of the subtraction circuit 49 is connected to the input terminal 5 of the addition circuit 59 via the variable transfer coefficient circuit 55.
7, the other input terminal 61 of the adding circuit 59 is connected to the input terminal 45 of the coupling circuit 21, and the output terminal 63 of the adding circuit 59 is further connected to the output terminal 25 of the coupling circuit 21. be.

Note that the variable transfer coefficient circuit 55 can be a circuit whose transfer coefficient changes depending on a voltage extracted from the input video signal by, for example, a motion detector or a nonlinear circuit, or alternatively, the variable transfer coefficient circuit 55 can be It is also possible to operate 55 as a non-linear circuit, the transfer coefficient of which depends on the amplitude of the input video signal.

Further, the operation of the noise suppression circuit is detailed in the aforementioned US Pat. No. 4,058,836, so please refer to it.

Therefore, the advantage of the video signal processing circuit of the present invention having the configuration shown in FIG. 1 is that the coupling circuit 21 is included in the analog signal processing section, and only the delay circuit 35 handles digital signals. It is. Therefore, the separation circuit 3 can have a simple configuration, and due to the incomplete wave action of the low-pass filter 9, there is a shift in the signal components between the high and low frequency signal components separated from each other. If this occurs, as a result of the complementary configuration of the separation circuit 3, the deviation of the signal component will act on the addition circuit 17 in the opposite direction. will be offset and removed. Furthermore, since no sampling is performed on the signal path from the output end of the separation circuit 3 to the addition circuit 17, undesired superposition of frequency spectra, that is, so-called aliasing (aliasing distortion) occurs. There is no possibility that this will occur. In other words, even if aliasing due to the sampling effect occurs in the analog-to-digital converter 29, it is recognized that such aliasing occurs only during sudden signal transients due to the sampling effect and is not transmitted by the coupling circuit 21. Therefore, there will be no problem.
Moreover, the coupling circuit 21 is
It can be easily realized in an analog circuit format. An example of the configuration of the coupling circuit 21 configured in such an analog circuit format is shown in FIG.

However, to prevent the occurrence of troublesome phenomena,
Alternatively, if it is necessary to take measures for suppression, it goes without saying that the coupling circuit 21 and the adder circuit 17 can be configured in a digital circuit format.

Further, in the configuration example shown in FIG. 1, the noise suppression circuit is provided in the form of a recursive circuit, but if necessary, a transversal circuit can also be used.

In FIG. 2 showing an example of the configuration of the coupling circuit 21, the same circuit elements as in FIG. 1 are shown with the same symbols, but the input terminal 45
and 23 are connected to the bases of emitter followers 65 and 67, respectively, whose emitter circuits include three diode series circuits 69 and 71 and current sources 73 and 75, respectively. Note that the diode groups 69 and 71 are, respectively,
It is used to shift the DC level. Each signal supplied to the input terminals 45 and 23 is guided to the connection point between the current sources 73 and 75 and the diode groups 69 and 71 via the emitter followers 65 and 67, respectively, but these connection points are connected to the transistors. The emitters of these transistors 77 and 79 are connected to a current source 84 via resistors 81 and 83, respectively. Furthermore, the collector of transistor 79 is connected to a transistor 85 connected in the form of a diode, which transistor 85 is arranged in parallel with the base-emitter circuit of transistor 86 to form a current reflection circuit.

The collectors of transistors 86 and 77 are connected to a series circuit of two diodes 87 and 89, and the intermediate connection point of the series circuit is connected to the emitter of transistor 67 and to one end of resistors 91 and 93. The resistors 91 and 93 are connected in common, and the other ends of the resistors 91 and 93 are connected to both ends of the resistor 95, respectively.

Therefore, those resistances 91 and 95 and 9
The voltage at each connection point between 3 and 95 is supplied to the output end 25 of the coupling circuit via emitter followers 97 and 99, respectively, with a transfer coefficient determined by the bias voltage of these emitter holons 97 and 99, respectively. Their bias voltages are generated by diodes 87 and 89, respectively. On the other hand, a resistor 101 connected between the emitter of the transistor 65 and the output terminal 25
together with an emitter lead wire connected to the output end 25 common to transistors 97 and 99, constitutes an adder circuit equivalent to adder circuit 59 in the configuration example shown in FIG.

Also, transistors 77, 79 and 97,9
9 constitutes a nonlinear subtraction circuit that is substantially equivalent to the combination of the subtraction circuit 49 and the variable transfer coefficient circuit 55 in the configuration example shown in the first figure, although the combination is different, and the connection of the resistors 91 and 93 The signal voltage from the input terminal 23 appearing at the point and the transistor 9
The voltage difference between the signal voltage from the input terminal 45 that appears at the connection point of the emitters 7 and 99 via the resistor 101 is the current flowing from the transistor 77 to the diode 87 and the current flowing from the transistor 79 to the transistor 8.
The bias voltages of the transistors 97 and 99 are determined by the current flowing through the diode 89 through the current reflection circuit formed by the transistors 5 and 86. is transmitted with an attenuation that changes non-linearly depending on the bias voltage, appears across the emitter follower load resistor 101, and is transmitted from the emitter of the transistor 65 to the resistor 10.
It is added to the signal voltage from input terminal 45 appearing at the base end of 1.

Thus, when there is a large difference between the signal voltages at inputs 23 and 45, which would occur if there was no correlation between the signals, transistor 77 controlled by the input signal , 86, the diodes 87, 89
A high voltage is generated in one of the emitter followers 97 and 99, so one of the emitter followers 97 and 99 conducts without attenuation.
The voltage appearing at the output terminal is the voltage appearing at the emitter of the transistor 67, and therefore the voltage appearing at the input terminal 23.
It is determined almost exclusively by the signal voltage supplied to.

On the other hand, if the difference in signal voltages at the inputs 23 and 45 is relatively small and therefore there is a high degree of correlation between the signals, the diode 87,
Emitsuta follower that occurs on one side of 89 97,99
Since the bias voltage of the transistor 65 is significantly reduced, reducing its transfer coefficient, the contribution of the signal appearing at the emitter of the transistor 65 to the signal appearing at the output 25 increases, and therefore the input 2
3 and 45, respectively, will appear at the output terminal 25.

Note that, if necessary, the transfer characteristics of the emitter followers 97 and 99 can be further changed by controlling the current source 84 using, for example, a noise amplitude dependent signal.

Next, another example of the schematic configuration of the video signal processing circuit of the present invention is shown in FIG. Note that in FIG. 3, the same circuit elements as in FIG. 1 are indicated with the same symbols. In the illustrated configuration example, the output terminal 3 of the analog-to-digital converter 29
1 and the input terminal 3 of the digital-to-analog converter 41
9, a delay line 103 having a delay time (R-1/2L) obtained by subtracting half the line period from one field period, and a delay line 103 having a delay time (R-1/2L) obtained by subtracting half the line period from one field period.
A changeover switch 10 is connected directly to the output end 31 of the digital converter 29, and in the other field, the connection is made via a delay line 107 having a delay time of one line period (L).
A delay circuit consisting of a series connection with 5 is provided.
According to the delay circuit having such a configuration, it is possible to obtain a noise suppression effect that is almost equivalent to that obtained by conventional noise suppression that is inevitably accompanied by image delay, and moreover, it is possible to obtain a noise suppression effect that is almost the same as that obtained by conventional noise suppression that is accompanied by image delay. This also eliminates the occurrence of troublesome noise patterns that would otherwise occur. According to the configuration shown in this third diagram,
Since the number of circuit elements can be further reduced than in the configuration shown in the first figure, it is more suitable for use in a television receiver.

The video signal processing circuit of the present invention is suitable not only for use in television receivers as described above, but also for use in image recording and display devices for video signals obtained by ultrasonic imaging devices, for example. It can also be applied to other video signal display devices such as display devices.

Note that when a digital nonlinear circuit is used for the variable transfer coefficient circuit 55 in the configuration shown in the first figure, the digital nonlinear circuit can be configured in the form of a programmable read-on memory (PROM).

Next, FIG. 4 shows still another example of the configuration of the video signal processing circuit of the present invention. It should be noted that in FIG. 4, the same circuit elements as in FIGS. 1 and 3 are shown with the same symbols, and explanations of these circuit elements will be omitted.

In the configuration example shown in FIG. 4, in addition to noise suppression for the low frequency signal component of the luminance signal Y in the input color video signal, noise is also suppressed for the chromaticity signal CHR also supplied to the input terminal 1. is carrying out oppression. Note that this chromaticity signal
The CHR consists of two color difference signal components U and V modulated on a color subcarrier.

That is, at the output terminal 5 of the separation circuit 3, not only the high-frequency luminance signal component _YH in the input color video signal but also the chromaticity signal CHR appears, and the total signal Y appearing at the output terminal 5 of the separation circuit 3 _H +CHR is supplied to the input terminal 109 of the demodulation circuit 111, the input terminal 113 of the oscillation circuit 115, and the input terminal 117 of the subtraction circuit 119.

Therefore, the oscillation circuit 115 has its input terminal 11
With the aid of the color synchronization signal present in the above-mentioned total signals supplied to the output terminal 12, two reference color phase signals having a phase difference of 90° from each other are generated.
1 and 123 respectively, and the demodulation circuit 1
11 input terminals 125 and 127, respectively. In the demodulation circuit 111, the chromaticity signal is synchronously demodulated using the two types of reference color phase signals, and one color difference signal U is sent out from the output end 129, and the other color difference signal V is sent out from the output end 13.
Send from 1.

These color difference signals U and V are transmitted through two sets of complementary transistor circuits 133, 135 and 137,1.
39 emitters, respectively, and two sets of current sources 141, 143 and 145, 147 respectively supply power to the bases of these complementary transistor circuits. Therefore, these current sources 141, 143, 145, 147 have their input terminals connected to the output terminal 53 of the subtraction circuit 49, as detailed in the above-mentioned US Pat. No. 4,058,836. It is controlled by a motion detector 149 configured to detect image motion when the inter-frame difference component of the supplied input video signal exceeds a predetermined threshold. The motion detector 149 detects the low frequency luminance signal component in the input color video signal.
Variable attenuator 45 in the noise suppression circuit for Y _L
It also controls the amount of attenuation of 5. Therefore, the first
Variable transfer coefficient circuit 55 in the illustrated schematic configuration
is the variable attenuator 455 in the configuration example shown in FIG.
This corresponds to a combination of the motion detector 149 and the motion detector 149, and the motion detector 149 is built-in.

Complementary transistor circuits 133, 135 and 137, 139 also have resistor voltage dividers 151, 153 and 155 connected between their respective bases.
The center taps of other resistor voltage dividers 159, 161 and 163, 165, respectively connected to the center tap of 157 and similarly connected between their respective bases, are connected to the delay circuits 171 and 165 through resistors 167 and 169, respectively. 173, and the delay time of these delay circuits is equal to that of the delay line 10 in the noise suppression circuit for the low frequency luminance signal component in the input color video signal.
3. It is set equal to the delay time set by changeover switch 105 and delay line 107. That is, the delay time in one field is the value obtained by subtracting half of one line period from one field period, and in the other field is the value obtained by adding one half of one line period to one field period. may be equal to one image period, for example.

The input terminals of the delay circuits 171 and 173 are connected to the mutually connected collectors of the complementary transistor circuits 133, 135 and 137, 139, respectively, and are connected to the resistive voltage dividers 159, 161 and 161 through the resistors 175 and 177, respectively. They are connected to the central taps 163 and 165, respectively.

Furthermore, complementary transistor circuits 133, 135
and 137, 139 correspond to the signals coming from the output ends 129 and 131 of the demodulation circuit 111, respectively, and the signals coming from the output ends of the delay circuits 171 and 173, respectively.
Each operates as a nonlinear circuit for the difference signal appearing between the emitters.

Therefore, each complementary transistor circuit 133,1
The difference signals appearing at the collectors of 35, 137, and 139, respectively, are connected to delay circuits 171 and 17.
The three output signals are added together. Therefore, the small amplitude difference signals are transmitted highly attenuated by their complementary transistor circuits 133, 135 and 137, 139, respectively, and
Large amplitude difference signals are transmitted with attenuation close to unity. Note that the amplitude of the signal appearing at the collector of the complementary transistor circuit when the degree of attenuation is approximately equal to 1 is determined by the values of the currents generated from the current sources 141, 143 and 145, 147, respectively.

Further, the mutually connected collectors of the complementary transistor circuits 133, 135 and 137, 139 are further connected to output terminals 179 and 18 for taking out the noise-suppressed color difference signals U and V, respectively.
1 and the modulation circuit 187.
are also connected to input terminals 183 and 185 of the modulation circuit 187, respectively, and the other input terminal 18 of the modulation circuit 187.
9 and 191 are connected to the output terminals 121 and 123 of the oscillation circuit 115, respectively.

As a result of the above configuration, the chromaticity signal CHR of quadrature phase modulation with suppressed noise is transmitted to the modulation circuit 187.
The chromaticity signal is supplied to the other input 195 of the subtraction circuit 119 and subtracted from the total signal Y _H +CHR, so that the high frequency luminance signal component is present at the output 197. Only _YH will appear.

This high-frequency luminance signal component Y _H is supplied to the input terminal 15 of the adder circuit 17 and then to the other input terminal 20.
Since it is added to the low frequency luminance signal component Y _L supplied to the adder circuit 17 , a full range luminance signal Y=Y _L +Y _H appears at the output terminal 199 of the adder circuit 17 .

In the overall luminance signal Y appearing at the output terminal 199 of the adder circuit 17, noise in the low frequency region is suppressed, and crosstalk of the chromaticity signal with respect to the luminance signal component in the high frequency region, that is, leakage. The luminance signal component is also suppressed.

Furthermore, the motion detector 149 also includes the complementary transistor circuit 13 that forms the transmission path for the color difference signals U and V.
3,135 and 137,139, it not only suppresses noise in static images, but also suppresses the chrominance signal component from the luminance signal component generated in the transmission path of the color difference signals U and V. The crosstalk to, that is, the leaky chromaticity signal component is also suppressed, but this suppression of the leaky chromaticity signal component is performed separately and independently from the above-mentioned suppression of the leaky luminance signal component.

Note that if necessary, frame memories can be used for each of the delay circuits 171, 173 and 103, 105, 107, but if field memories are used as in the illustrated example, leakage chromaticity signal components can be suppressed. can be done relatively quickly.

In addition, in the above configuration example, the circuit was explained as a circuit that processes a PAL color video signal.
This circuit can also be applied to processing NTSC color video signals. Note that in a circuit that processes PAL color video signals, the color difference signal U
It is also possible to average V and V using a noise suppression circuit.

Furthermore, if the color difference signals U and V pass through a noise suppression circuit in a time-division multiplexed manner, a single noise suppression circuit may be used for both color difference signals, if necessary. The common use of such a single noise suppression circuit is particularly advantageous when digital signal processing is performed.

In addition, in each of the above configuration examples, analog circuits are used for the linear circuit and the noise suppression circuit, but it is also possible to appropriately add and use digital nonlinear circuits configured with programmable read-only memory (PROM), for example. Of course, it can also be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the schematic configuration of the video signal processing circuit of the present invention, FIG. 2 is a block diagram showing an example of the configuration of the coupling circuit, and FIG. 3 is another example of the schematic configuration. FIG. 4 is a block diagram showing still another example of the configuration. 1, 15, 20, 23, 27, 33, 39, 4
5, 47, 51, 57, 61, 109, 113,
125, 127, 183, 185, 193, 19
5...Input end, 3...Separation circuit, 5, 7, 25, 3
1, 37, 43, 53, 63, 121, 123,
129, 131, 179, 181, 193, 19
7,199...Output end, 9...Low pass filter, 1
1,103,107...delay line, 13,49,11
9... Subtraction circuit, 17, 59... Addition circuit, 19... Noise suppression circuit, 21... Coupling circuit, 29... Analog-digital converter, 35... Digital delay circuit, 41... Digital-analog converter, 55...
Variable transfer coefficient circuit (digital nonlinear circuit), 6
5,67...Emitsuta Holowa, 69,71,8
7, 89...Diode, 73, 75, 84, 14
1,143,145,147...Current source, 77,7
9,85,86,133,135,137,13
9...Transistor, 81, 83, 91, 93, 9
5,101,151,153,155,157,
159, 161, 163, 165, 167, 16
9,175,177...Resistor, 105...Selector switch, 111...Demodulation circuit, 115...Oscillation circuit, 1
49...Motion detector, 171, 173...Delay circuit,
187...Modulation circuit, 455...Variable attenuator.

Claims (1)

[Scope of Claims] 1. A separation circuit that separates and extracts a high frequency signal component and a low frequency signal component from an input video signal to be processed, and the high frequency signal components separated from each other from the separation circuit and the A video signal processing circuit comprising a noise suppression circuit that operates on one of the low frequency signal components, wherein the noise suppression circuit is a circuit that operates on the low frequency signal component, and includes a delay circuit and a coupling circuit. A video signal processing circuit characterized in that a comb-shaped filter is provided, the coupling circuit coupling the output signal of the delay circuit to the low frequency signal component. 2. In the video signal processing circuit according to claim 1, the noise suppression circuit for color information in an image to be displayed based on the input video signal is transmitted in the coupling circuit included in the noise suppression circuit. A video signal processing circuit further comprising a motion detector whose output end is coupled to a nonlinear circuit whose coefficients change nonlinearly and controls a transfer coefficient of the nonlinear circuit in accordance with the motion of the image. 3. A video signal processing circuit according to claim 2, which suppresses color information in a high frequency signal component of the input video signal using color information extracted from the noise suppression circuit for color information. A video signal processing circuit further comprising: 4 Claims for use in an interlaced operation television system In the video signal processing circuit according to any one of the preceding claims, the delay circuit in the comb-shaped filter has one field period and one field period in each field scanning period. A switchable delay time consisting of a delay time of the sum of /2 line period and a delay time of the difference between 1 field period and 1/2 line period in each field scanning period of the other intervening in each field scanning period of the one field scanning period. A video signal processing circuit comprising: 5. Claims: The video signal processing circuit according to any of the above claims, characterized in that the separation circuit and the combination circuit are in the form of an analog circuit, and the delay circuit is in the form of a digital circuit. Video signal processing circuit.