JPH021796U - - Google Patents

Info

Publication number
JPH021796U
JPH021796U JP7881788U JP7881788U JPH021796U JP H021796 U JPH021796 U JP H021796U JP 7881788 U JP7881788 U JP 7881788U JP 7881788 U JP7881788 U JP 7881788U JP H021796 U JPH021796 U JP H021796U
Authority
JP
Japan
Prior art keywords
scanning
circuit wiring
matrix circuit
scanning signal
signal generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7881788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7881788U priority Critical patent/JPH021796U/ja
Publication of JPH021796U publication Critical patent/JPH021796U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案を適用して構成した電子楽器
の全体回路図、第2図は操作子走査回路の詳細図
、第3図はクロツクA,B及びCを作るCPU内
部の部分的回路図、第4図は第3図で使用されて
いるNAND回路の真理値表を示している図、第
5図は第3図で使用されているデコーダの真理値
表を示している図、第6図は第2図で使用されて
いるトライステートバツフアの真理値表を示して
いる図である。 1……CPU、2……鍵盤部、3……スイツチ
部、6……ROM、7……RAM、8……楽音作
成部、11……スピーカ、12,13,14……
マトリクス、12a,13a,14a……トライ
ステートバツフア。
Figure 1 is an overall circuit diagram of an electronic musical instrument constructed by applying this invention, Figure 2 is a detailed diagram of the operator scanning circuit, and Figure 3 is a partial circuit diagram inside the CPU that creates clocks A, B, and C. , Figure 4 shows the truth table of the NAND circuit used in Figure 3, Figure 5 shows the truth table of the decoder used in Figure 3, and Figure 6 shows the truth table of the decoder used in Figure 3. The figure shows a truth table of the tristate buffer used in FIG. 2. 1... CPU, 2... Keyboard section, 3... Switch section, 6... ROM, 7... RAM, 8... Musical tone creation section, 11... Speaker, 12, 13, 14...
Matrix, 12a, 13a, 14a...tristate buffer.

Claims (1)

【実用新案登録請求の範囲】 複数のスイツチを使用頻度別にグループ分けし
、このグループ分けされた複数のスイツチを夫々
配線接続した複数のマトリクス回路配線手段と、 これらの複数のマトリクス回路配線手段を繰り
返し走査するための走査信号を発生する走査信号
発生手段と、 この走査信号発生手段を制御して、最も使用頻
度の高いマトリクス回路配線手段に対する走査処
理を行うと共に、その他のマトリクス回路配線手
段に対して順番に、又はその使用頻度に応じて順
次走査処理を行う走査制御手段と を具備したことを特徴とする電子機器の走査装
置。
[Scope of Claim for Utility Model Registration] A plurality of matrix circuit wiring means in which a plurality of switches are grouped according to the frequency of use, and each of the grouped switches is connected by wire, and a plurality of matrix circuit wiring means are repeatedly connected to each other. A scanning signal generating means for generating a scanning signal for scanning, and a scanning signal generating means for controlling the scanning signal generating means to perform scanning processing for the most frequently used matrix circuit wiring means, and for other matrix circuit wiring means. A scanning device for an electronic device, comprising: a scanning control device that performs scanning processing sequentially or sequentially according to the frequency of use.
JP7881788U 1988-06-16 1988-06-16 Pending JPH021796U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7881788U JPH021796U (en) 1988-06-16 1988-06-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7881788U JPH021796U (en) 1988-06-16 1988-06-16

Publications (1)

Publication Number Publication Date
JPH021796U true JPH021796U (en) 1990-01-08

Family

ID=31303714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7881788U Pending JPH021796U (en) 1988-06-16 1988-06-16

Country Status (1)

Country Link
JP (1) JPH021796U (en)

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