JPH02179045A - Clock frequency adjustment method for data receiver - Google Patents

Abstract

PURPOSE:To prevent the occurrence of an idle buffer or an occupied buffer by adjusting a frequency of a readout clock in response to the frequency differ ence between a write clock and the readout clock. CONSTITUTION:When an oscillated frequency of a VCO 5 is lowered and a count of an up-down counter 6 exceeds +x, an output of a ROM 7 is accumulat ed to a voltage outputted before the excess in the increasing direction and an output of an integration device 8 is increased. The oscillated frequency of the VCO 5 is increased accordingly and the count of the counter 6 is corrected so as to be within a range of '-x or over and +x or below'. When the oscillated frequency of the VCO 5 is increased and the count of the counter 6 exceeds -x, the output of the ROM 7 is accumulated to the voltage outputted before the excess in the decreasing direction and the output of the integration device 8 is lowered. The oscillated frequency of the VCO 5 is decreased accord ingly and the count of the counter 6 is corrected so as to be within a range of '-x or over and +x or below' similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock frequency adjustment method for a data receiving device that receives data representing real-time audio or images sent through a communication line.

[Conventional technology]

Conventionally, there is a data receiving device in which real-time input data from a communication line is written into a buffer using a write clock from the transmission source, and data read from this buffer using a read clock different from the write clock is output data. .

FIG. 3 shows a conventional device of this type.

In this figure, L is a communication line, 1 is a decoder, 2 is a buffer, 3 is a crystal oscillator, and 4 is a D/A converter. Real-time input data from a communication line is input to a decoder 1. This decoder 1 performs decompression processing to return human data to the original time axis when it is sent after being time-axis compressed on the transmitting side, and also demodulates the input data. Generate a clock with a frequency corresponding to the frequency. Input data is thus decoded and separated into data and clock. The data is given to buffer 2 as write data and the clock is given as write tally to buffer 2, so that the data from decoder 1 is stored in buffer 2.

The output of the crystal oscillator 3 is used as a read clock by the buffer 2.
is supplied to. As a result, the data stored in the buffer 2 is read out, converted into an analog signal by the D/A converter 4, and output data representing real-time audio and images.

In this way, the input data is first written into the buffer 2 using the clock from the transmission source, and then read out using the clock from the oscillator 3, and this is used as output data, so that the data is transmitted over the communication line L'2. It is designed to absorb frequency variations caused by delays at the nodes passing through when the signal is being transmitted.

[Problem to be solved by the invention]

However, the oscillation frequency of the crystal oscillator that constitutes this conventional device may fluctuate due to fluctuations in power supply voltage or temperature changes, and in this case, a difference in frequency occurs between the write clock and the read clock to buffer 2. do. Therefore, if such a state continues, the frequency error will accumulate and there will be a problem that reading data from the buffer 2 will not be performed normally. In other words, if the read clock has a higher frequency than the write clock, writing cannot keep up with reading, resulting in a situation where there is no data in buffer 2 even if an attempt is made to read, and vice versa. If the frequency is low, reading cannot keep up with writing, and the buffer 2 becomes full, resulting in data loss.

Here, let the fundamental frequency be fs and the actual read clock frequency fS', for example, fS-1000010H
Assume that zS is constant at fs'-1000000Hz,
Assuming that one byte is transferred in one clock,
0. Data is accumulated in the buffer 2 at a rate of 1 byte per 1 (=1/I fs - fs'l) second. If the capacity of the buffer 2 is, for example, 100 kilobytes, the buffer 2 becomes full in 10 (-100 kilobytes XO,, 1) seconds.

The present invention has been made in view of the problems of the prior art, and its purpose is to provide a clock frequency adjustment method for a data receiving device that does not cause the buffer to become empty or full. Our goal is to provide the following.

[Means to solve the problem]

A clock frequency adjustment method for a data receiving device according to the present invention detects a frequency difference between a write clock and a read clock, adjusts the frequency of the read clock according to this frequency difference, and represents a frequency difference within a predetermined value. The present invention is characterized in that the detection signal is controlled by a control signal from a control signal generation circuit whose output remains unchanged.

[For production]

One major feature of the present invention having such a configuration is that the frequency of the read clock is adjusted based on the frequency of the write clock.

That is, as mentioned above, the frequency of the write clock varies due to transmission factors, but on average it is fs. The present invention focuses on this point, and ignores slight frequency fluctuations as an uneven frequency of the write clock due to transmission factors, and when it exceeds this range, corrects it as a frequency fluctuation of the read clock. This is what I decided to do. According to the present invention, first, the frequency of the read clock is adjusted according to the frequency difference between the write clock and the read clock, so that the oscillation source of the read clock is free from the effects of power supply voltage fluctuations, temperature changes, etc. Accordingly, even if a frequency difference occurs between the write clock and the read clock, the difference is corrected and errors can be prevented from accumulating.

In addition, the control signal generation circuit that performs this control has a dead band for frequency differences within a predetermined value, so if the range of the dead band is set as the range of variation in transmission, this type of device The original variation absorption operation is performed reliably.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a data receiving device implementing the method of the present invention, and FIG. 2 is a curve diagram showing the output characteristics of a ROM constituting the control signal generating circuit.

First, in FIG. 1, reference numeral 5 denotes a voltage-controlled crystal oscillator, and the output of this voltage-controlled oscillator 5 is supplied as a read clock to the buffer 2 here.

6 is an up/down counter. The up/down counter 6 counts up by the write clock from the decoder 1 and counts down by the read clock from the voltage controlled oscillator 5, and its output contains a count corresponding to the difference in frequency between the write clock and the read clock. The up/down counter 6 detects the frequency difference between the write clock and the read clock.

7 is a ROM, and 8 is an integrator. The ROM 7 holds data that is the manipulated variable of the read clock frequency corresponding to each count value of the up/down counter 6, and as shown in FIG. When , it remains unchanged and the same count value is +
When the count value is greater than X, the output increases in proportion to the increase in the count value, and when the count value is less than -X, the output decreases in proportion to the decrease in the count value.

The above-mentioned range of "-X or more and +X or less" corresponds to the maximum range of variation in the count value of the up/down counter 6 due to non-uniformity in the frequency of the write clock. The integrator 8 is designed to integrate the output of the ROM 7, and the integrated value is supplied to the control terminal of the voltage controlled oscillator 8, and a clock having a frequency corresponding to the output voltage of the integrator 8 is output from the oscillator 5. be done.

According to this embodiment, first, while the count value of the up/down counter 6 is within the range of "-X or more +X or less", the ROM 7 outputs zero, so the output voltage of the integrator 8 is Therefore, the oscillation frequency of the voltage controlled oscillator 5 maintains a constant value unless there is an influence of fluctuations in power supply voltage, temperature changes, etc.

However, due to such factors, the oscillation frequency of the voltage controlled oscillator 5 changes and the count value of the up/down counter 6 exceeds the range of "-X or more +X or less",
An input to the integrator 8 in the + direction or in one direction is generated.

First, when the oscillation frequency of the voltage controlled oscillator 5 decreases and the count value of the up/down counter 6 exceeds +X, the output of the ROM 7 is cumulatively added in the raw direction to the voltage value that was output before exceeding +X, and is integrated. The output of the oscillator 8 increases, and accordingly, the oscillation frequency of the voltage controlled oscillator 5 is corrected so that the count value of the up/down counter 6 falls within the range of "-X or more + X or less". becomes.

Furthermore, when the oscillation frequency of the voltage controlled oscillator 5 increases and the count value of the up/down counter 6 exceeds -X, the output of the ROM 7 is cumulatively added in one direction to the voltage value that was output before exceeding -X. The output of the integrator 8 decreases, the oscillation frequency of the voltage controlled oscillation S5 decreases, and the count value of the up/down counter 6 similarly decreases to "-X".
It will be corrected so that it falls within the range of "more than or equal to +X or less".

In this way, by correcting the oscillation frequency of the voltage controlled oscillator 5, that is, the frequency of the read clock, it is possible to prevent the buffer 2 from becoming empty or overflowing, so that audio, images, etc. can be processed normally. Can be played.

〔Effect of the invention〕

As explained above, according to the present invention, frequency fluctuations within a predetermined range are ignored as being non-uniform in the frequency of the write clock due to transmission factors, and when they exceed that range, they are considered to be frequency fluctuations in the read clock. Since the correction is performed, the buffer will not become empty or full, and normal real-time data such as audio and images can be output even if there are fluctuations in power supply voltage or temperature changes. be effective.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of a data receiving device that implements the method of the present invention, Fig. 2 is a graph showing the output characteristics of a ROM constituting the control signal generation circuit, and Fig. 3 is a conventional data receiving device. FIG. 2 is a block diagram of the device.

Claims (1)

[Scope of Claims] Data in which real-time input data from a communication line is written into a buffer using a write clock from its source, read from this buffer using a read clock different from the write clock, and the read data is used as output data. A basic frequency adjustment method for a receiving device, comprising: detecting a frequency difference between the write clock and the read clock; and providing a control signal in which the output remains unchanged for a detection signal representing a frequency difference within a predetermined value. A clock frequency adjustment method for a data receiving device, comprising adjusting the frequency of the read clock according to the frequency difference using a control signal from a generation circuit.