JPH02178859A - Address converter - Google Patents

Abstract

PURPOSE:To decide the stop of address conversion processing in the shortest main storage access time by storing the address of a descriptor, which causes the stop of processing, and contents of a control register of an address conversion logic at this time in a TLB (translation look-aside buffer) at the time of stopping the address conversion processing by necessity so that the processing can be restarted. CONSTITUTION:When the address conversion processing cannot be continued by the descriptor in a page descriptor register (PDR) 10, contents of an actual address register (PAR) 8 where the address of the descriptor is stored are written in a TLB 5 and contents of a page control register (PCR) 11 are written in the C field of the TLB 5. V bits of the TLB 5 are set to '10' indicating the restart mode. Thus, the stop of address conversion processing is decided in the shortest access time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address translation device, and more particularly to an address translation device that translates a virtual address into a real address.

Conventional technology Most medium-sized or larger information processing devices use virtual memory as their memory management method. However, virtual memory has two systems: virtual space, which is an ideal address space, and real space, which is the address space of main memory. The space is managed by a correspondence table (address translation table) on the main memory.

Therefore, the access time of the address translation table is added to the memory access time of an information processing apparatus that employs this virtual storage method.

For example, in an information processing device that employs a virtual memory method with an address conversion procedure as shown in FIG. address conversion table 2
The memory access time to 02 is added. Furthermore, in an information processing apparatus that employs a virtual memory system having a three-step address conversion procedure as shown in FIG. 3, three memory access times are added for each memory access.

As described above, the memory access time of an information processing apparatus that employs virtual memory is more than twice that of an information processing apparatus that does not employ virtual memory, resulting in a significant performance drop. Therefore, in order to reduce memory access, a relatively small and high-speed buffer is provided, and the address conversion table accessed for address conversion is registered in this buffer. It is supposed to perform address translation in time. This buffer is called TLB (Translation Loo).
K-side Buffer). The TLB is usually an associative memory and cannot accommodate the entire address translation table, so its contents are managed by some kind of replacement algorithm.

Also, since it is impossible to allocate a relatively large virtual space into a relatively small real space, it is possible to place only the part of the virtual memory that is needed at the moment in the real space, and then write the address translation table corresponding to that part. Sets a bit indicating that that part of ``exists in real space.'' Parts that cannot be placed in real space are usually stored in secondary storage (mainly disks)
placed on top. Access to a portion existing in secondary storage causes a page out event when an address translation table is accessed. A page is a unit for managing virtual space, and is usually 1 to 4. The size of KB is adopted. When a page-missing event occurs, secondary storage and real space are swapped. The same algorithm as when replacing the TLB is used for the real space page to be replaced.

In the multi-stage address translation process shown in FIG. 3, there is a bit in the discriminator in each table that indicates the presence/absence of the next level table. This saves space in the address translation table, and is therefore used in many information processing devices today.

The effectiveness of virtual memory and 'I'LB depends on the fact of locality of access, but there are situations in which this assumption is not valid.In those cases, much of the memory access time is spent in address translation. Particularly, in devices such as today's large-scale information processing devices that perform advance control of processing to a high degree, problems of the following nature may occur.

When advance control is performed, the advance control unit (a part of the arithmetic processing unit in the information processing device) executes the instruction itself and, in some cases, the operand (operation target) of the instruction following the currently executed instruction. Try to retrieve it from main memory as long as 6
Of course, that effort may be in vain.

For example, when there is a conditional branch instruction, the preceding control unit extracts subsequent instructions on both sides, considering the possibility that the branch condition will be met or not. When this conditional branch instruction is executed and it is determined whether the branch condition is satisfied or not, the unnecessary prefetched instruction is not used and is discarded. The efforts of those who are not used will be wasted.

Under such circumstances, it can be expected that most of the execution of a program with poor locality will be spent accessing the address translation table in main memory.

Although the TLB is effective in this case, the accessed address translation table on the main memory may end without being registered in the TLB.

If, as a result of accessing the address translation table, it is found that the next level table or the page itself does not exist in the real space, the address translation process is stopped at that point and the TLB is not updated. This absence event is stored as preemptive information regarding the instruction that caused this event,
When this command is actually executed, it will be treated as an absent event.

If an absence event is recognized, execution of the current program is normally stopped as an exception event, and replacement with secondary storage and real space is performed. At the end of the replacement process, the existence hit in the real space of the discriminator in the address translation table for the page that caused this exception is sent to Sen1. The program re-executes the instruction that caused the exception and resumes processing. Either an access to this page requires an access to the address translation table, or the address translation completes normally, unhindered by the absent event, and the result of the address translation is registered in 'r'LB. Thus. , subsequent accesses to this page can be executed at high speed using the TLB.

The above example was a case where the pre-fetched instruction was executed later. On the other hand, if an absent event occurs during prefetching on the non-branching side of the branch instruction mentioned earlier, the instruction that caused the event will never be executed, so the only thing that can be done is to replace it with secondary memory and real space. The entry in the address translation table for the page that caused the absence event continues to indicate absence, and is not registered in the TLB.

If such an instruction is in a program loop, the address translation table in the main memory will be accessed each time the instruction is accessed, resulting in a significant increase in memory access time.

In particular, in the virtual memory system that uses multi-level address translation tables that are widely used today, a page fault event is detected after accessing the address translation table many times, so performance degradation due to wasteful access is avoided. it is obvious.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an address translation device that can determine whether to discontinue address translation processing in the shortest access time when the address translation processing must be discontinued in the middle of an access.

According to the present invention, there is an address translation buffer for converting a virtual address to a real address, and when a required address is not registered in this address translation buffer,
an address translation device that executes address translation processing using an address translation table, wherein an exceptional event occurs in the address translation processing using the address translation table, making it impossible to continue the address translation processing; , the address of the disc libter in the address translation table that caused this outer event and control information for determining the state of the address translation means at that time are registered in the address translation buffer. A characteristic address translation device is obtained.

X layer side Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Here, address translation using a three-level table as shown in FIG. 3 is considered as a virtual storage system. Further, it is assumed that the level 1 address translation table starts from address O in real space. The virtual space is represented by 32 bits, and the size of one page is 4 bytes. The indexes to the address translation table at each level within the virtual page are each 4.88 bits. That is, the size of the level 1 address translation table is 16 words, and the maximum size of the level 2.3 address translation table is 256 words.

FIG. 4 (A) shows the next level table descriptor in each address translation table, and (B
) shows the descriptor of the real page, base B is 16 in both cases.
To obtain the address to the address translation table, add this base B and the index obtained from each virtual page number, and to obtain the real space address, combine base B and the address in the page. do.

Next, the operation of this embodiment will be explained. The address translation device of this embodiment is located between the arithmetic processing unit and the main storage device. That is, it receives a virtual address from the arithmetic processing unit through the signal line 101, converts it into a real address, and sends the real address to the main memory through the signal line 124.

Translation from normal virtual address to real address is performed by TLB5.
This is done using This embodiment assumes a set-associative TLB. That is, the virtual address received from the arithmetic unit through the signal line 101 is stored in the virtual address register (VAR) 1. TLB 5 is addressed with the lower virtual page number by signal line 104, and the virtual address field VA in the corresponding TLBS and the higher virtual page number in VARI are input to comparator 6 via signal lines 103 and 113 for comparison. .

The result of this comparison and the valid bit field in the TLBS ■
AND gate 7 becomes active only when both are logical 1, and a hit signal is output through signal line 128.

■A pit is composed of 2 bits: a bit that represents the validity/invalidity of the entry information in TLB 5, and a bit that represents restart/new information, which is a feature of the present invention that will be described later.
It is as follows.

00: The entry is not valid 01: The entry is not valid 10: The entry is valid and restartable 11: The entry is valid and the new hit signal is input to the input selection circuit of the real address register (PAR) 8. Ru. PAR8 has a hit signal of logical value 1
In this case, the output 115 of the real page number field PA in LB5 is set as the real page number, and the signal line 1, which is the in-page address in VARI, is set as the real page address.
05 are selected as inputs and stored. The real address for the virtual address given in this way is signal line 1.
24 to an unillustrated main storage device.

At the same time as virtual address to real address translation, TLB
The control field C of 5 is accessed and stored in the status register (SR>9 on the condition that it is a hit signal or a logical value 1.The control field C contains information about the converted real page. These pieces of information include, for example, readable, writeable, protection keys, etc. These pieces of information are included in the request code (not shown here) that is sent at the same time as the virtual address. When the request content is compared with the information, and if the requested content is contrary to the page information, the status decoding circuit 18 detects this fact and stores it in the status register 9. SR9
The output 125 of is reported as an exception event to the arithmetic unit that requested the address translation.

When there is no match between the upper virtual page number of VARI and the VA field of "I' L B 5," or when the V field of TLB5 has a logical value of 0, the TLB
5 fails, and the address translation logic on the right side of FIG. 1 operates. In this case, an address translation table on the main memory is used.

First, the level 1 address translation table is accessed. Top 4 pits of VARI are field extraction times FR
112 and is input to the adder 13 through a signal line 118. At this time, the other inputs of the adder 13 are controlled by the input selector so that O is input. The output 117 of the adder 13 is input to PAR8 via an input selector.

The page control register (PCR) 1.1 is a control register for the address translation logic and determines the operation of the address translation logic. When the address conversion logic starts, the contents of PCRll are initialized to indicate that the level 1 address conversion table is being accessed, and thereafter, the next state created by the control logic 15 is received via the signal line 123 and sequentially processed. No repeated state transitions.

The control logic 15 controls the state within the address translation logic;
Depending on the current state (PCR output 112), size check result (subtractor 14 output 119), existence bit (PDR output 110), and control field (PDR output 111), the following state B (output 123) and status ( Output 12
1), produce a valid bit (output 120).

Now, whether it is the output 117 of the adder 13 or the address of a certain entry in the level 1 address conversion table, the main memory is accessed through PAR8. Data from main memory is stored in page descriptor register PDRIO through signal line 128. This PDRI
The content of O is a level 2 address translation table distributor.

Next, from this level 1 address translation table, the address of the entry in the level 2 address translation table is determined. This operation is the same as the method of accessing the level 1 address translation table described above. The difference is that the index (bits 4 to 11) of the level 2 address conversion table is taken out from the field extraction circuit 12 or VARI, and that a size check is performed.

The size check consists of subtracting the index obtained by the field extraction circuit 12 from the discreptor's left field in the PDRIO, and checking to see if there is a pollo. When a borrow occurs, the index exceeds the page size, so access to the page table is immediately stopped, and the fact that a hollow occurs is stored in SR9.

A similar check is also performed on the presence bit P and real page control information. Regarding the existence bit P, if P of the accessed disc libter is logical 0, address translation is stopped. For control information, the TLB mentioned above
Address conversion is performed in the same way as address conversion using 5. In either case, if a situation occurs in which the processing cannot be continued, that fact is stored in SR9 and reported to the arithmetic unit as an exception event.

Just as the disk libters in the level 2 address conversion table are accessed from the information in the level 1 address conversion table, the disk libters in the next level address conversion table are accessed one after another. Finally, the real page discriminator is accessed and stored in PDRIO. At this time, various checks are performed depending on the contents of PDR10.

However, the base B passes through the adder 13 (one input is 0
8) and store it in the page write register (
PTR) 3 and is written to the PA section of the TLB. At the same time, the control field of PDRIO is passed through the control circuit 15, control transfer register (PCTR) 17, and field write register (CR) 4, and is written as 'T' L B.
In the C field of TLB5, the content of VARl is the V of TLB5.
It is written to the A field and in a similar path as the V bit or control bit.

If the address translation process described above cannot be continued, the conventional address translation device does nothing other than return the status. However, in the present invention, the following processing is performed.

If it is not possible to continue processing due to the disc libter in the PDRIO, the address of the disc libter or the contents of the PA section 8 that is stored is sent to the TL via PTR3.
Write to B5. At the same time, write the contents of PCRll to PCTR17.
, and written to the C field of TLB5 via CR4.

Furthermore, the contents of VARl are also written to the ■ field of TLB5. However, the pins 1 to 1 of TLB5 do not indicate the restart mode and are set to 10.

Next, when there is an address conversion request for the same address (same page), when TLB5 is accessed, the AND gate 19 becomes active according to the above settings of the ■ pit, and the corresponding page is the page for which address conversion was canceled. I can recognize that. At this time, the PA field of TLB5 is stored in the PA section 8, and the C field of TLB5 is stored in PCRI 1 through the signal line 116. Thus, the address translation logic can begin processing first with the access to the discreptor that caused the abort of processing. Of course, the information written in the C field of TLB5 needs to be necessary and sufficient to enable address translation or restart.

As explained above, according to the present invention, when address translation processing has to be stopped in the middle of accessing a multi-level page table due to various checks, processing can be stopped. T so that the address of the bluff ripter and the control register of the address translation logic at that point can be restarted.
By storing it in the LB, if the address translation process is canceled and the result cannot be registered in the TLB, or if there is an access during a program loop, it is possible to determine whether the address translation process is canceled with the minimum main memory access. So,
This has the effect of increasing the speed of the program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 and FIG.
The figure is a conceptual diagram of conversion processing when an address conversion table is used. Figure 4 (A) is a diagram that does not show the disc libter of the address translation table. Figure 4 (B) is a diagram that shows the disc libter of the real page. be. Explanation of symbols of main parts 1...Virtual address register (VAR) 2...
...V pit write register (VR) 3...
・Page write register (P 'T' R) 4...
...Page control register (CR) 5...TLB 8...Real address register (PAR) 9...
... Status register (SR) 10 ... Page data register (PDR) 11 ... Page control register (PCR) 12 ... Field extraction circuit 15 ...・Control logic

Claims (1)

[Claims] (1) An address translation buffer for converting a virtual address into a real address, and an address translation means that executes address translation processing using an address translation table when the required address is not registered in this address translation buffer. If an exception occurs in the address translation process using the address translation table and it becomes impossible to continue the address translation process, the address translation device that includes the address translation table that caused the exception 1. An address translation device characterized in that an address of a descriptor of the address translation unit and control information for determining a current state of the address translation means are registered in the address translation buffer.