JPH02177083A - Semiconductor memory circuit device - Google Patents

Abstract

PURPOSE:To prevent malfunction of the circuit by constituting a pulse generating circuit with a Schmitt trigger circuit, and blocking the transmission of a deformed pulse to circuits of the post-stage even if the said pulse is inputted. CONSTITUTION:A Schmitt trigger circuit 20 is used for address input as a pulse generating circuit. Even if an irregular pulse is inputted as an address signal, it is not transmitted to a self-synchronizing RAM 10. This is because a logic threshold level is set high in the input and output transmission characteristic of the Schmitt circuit 20 when an input voltage rises and set low when the input voltage is descended. Even if a pulse waveform as an address input signal is inputted, the transmission of an undesired signal is avoided by the provision of the circuit 20. Thus, malfunction of the circuit 10 is avoided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory circuit device, and more particularly to a circuit that detects a change point in an address input signal, generates a pulse, and self-synchronizes using the pulse. .

[Prior Art] Conventionally, this type of semiconductor memory circuit device, for example, a readable/writable memory circuit (hereinafter referred to as RAM) is
Pulses for precharging the common bit lines of M cells and controlling signals for driving word lines were generated by detecting changing points in address input signals. This is generally called a self-synchronous RAM or an internally synchronized RAM. By doing this, a designer who designs a circuit using a RAM does not have to design a timing for inputting a synchronization pulse from outside the RAM, which simplifies the design.

As a circuit for generating synchronizing pulses, there is a circuit as shown in FIG. Address input ADO', AD1',...
A pulse is generated by exclusive ORing a signal delayed by connecting four stages of inverting gates 32 in series and a signal not delayed by a gate 33, and further logic is determined by a gate 34. This becomes the same month pulse and is used to control each part of the RAM.

[Problems to be Solved by the Invention] The conventional semiconductor memory circuit device described above has a configuration in which a synchronization pulse is generated by a simple gate. When an address signal is input, a synchronization pulse may not be generated or an undesired intermediate potential may be output, causing the RA
There is a drawback that M may malfunction.

[Differences between the Invention and the Prior Art] The present invention differs from the conventional semiconductor memory circuit device described above in that a Schmitt trigger circuit is connected to the address input section.

[Means for Solving the Problems] The gist of the present invention is to provide a semiconductor including a pulse generation circuit that detects a voltage change point of an address human input signal and generates a pulse, and a memory cell circuit that is self-synchronized by the pulse. In the memory circuit device, the pulse generating circuit is configured with a Schmitt trigger circuit.

[Example code] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

10 is a RAM that is self-synchronized by pulses ADO', ADI', .
I, . . . Schmitt trigger circuit that shapes the waveform of ADn, W is a write enable signal, WDO9WD1...・・・
・WDm is write data, RDOlRDl,...R
Dm is read data. FIG. 2 shows a specific example in which the Schmitt trigger circuit 20 is constructed using a CMOS transistor. MOS) transistor QPI-QP3, QNI
- By appropriately determining the ratio of the gate width W and the gate length of QN3, the logic threshold voltage VT can be set to high (VT2) when the input voltage rises, and 7 when it falls, as shown in the transfer characteristic in Figure 4. Lower the knife (VT
l) Schmitt trigger circuit 20 that can be configured
is used for the address input, even if a convex pulse whose peak voltage does not reach V, T2 or a concave pulse whose peak voltage does not reach VTI enters as an address input signal, it will not be transmitted to the subsequent self-synchronous RAM circuit 10. It becomes possible to

FIG. 3 shows a Schmitt trigger circuit C according to a second embodiment of the present invention.
This is a specific example composed of transistors (MOS). QP4.
By appropriately determining the ratio of the gate aW to the gate length of QP5 and QN4 to QN6, the logic threshold voltage VT can be set such that the logic threshold voltage VT is high at the rising time and < (VT2) at the falling edge, as shown in FIG. 4, as in the first embodiment. sometimes low (
VTI) can be set. If this Schmitt trigger circuit is used in the address input section, it can be made insensitive to pulsed input voltages. The advantage of this embodiment is that it can be constructed with fewer transistors than the circuit of the first embodiment (FIG. 2).

[Effects of the Invention] As explained above, the present invention generates a pulse by detecting a change point in an address input signal, and adds a Schmitt trigger circuit to the address input of a semiconductor memory circuit device that self-synchronizes with this pulse. This has the remarkable effect of preventing the circuit from malfunctioning due to propagation of unnecessary signals even if a pulse-like waveform is input as an address input signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the semiconductor memory circuit device of the present invention, FIG. 2 is a circuit diagram showing a specific example in which the Schmitt trigger circuit of the first embodiment is configured with a CMOS transistor, and FIG. is the Schmitt trigger circuit of the second embodiment.
MOS) A circuit diagram showing a specific example configured with transistors, Figure 4 is a graph showing the input/output transfer characteristics of a Schmitt trigger circuit, and Figure 5 is used to detect changing points of address input signals and control various circuits. FIG. 2 is a block diagram of a conventional example of a synchronous pulse generation circuit. 10... , ...Schmitt trigger circuit, ...synchronous pulse generation circuit, ...inversion gate, ...delay gate, ...exclusive OR gate, ...OR gate, P-channel MOS) transistor, N-channel MOS) transistor.

Claims (1)

[Scope of Claims] A semiconductor memory circuit device including a pulse generation circuit that detects a voltage change point of an address input signal and generates a pulse, and a memory cell circuit that is self-synchronized by the pulse, the pulse generation circuit as described above. A semiconductor memory circuit device comprising: a Schmitt trigger circuit.