JPH02176914A - Constant-voltage generating circuit - Google Patents

Abstract

PURPOSE:To always generate a constant stable voltage to a power supply voltage by compensating a fluctuation caused by a variation of an ambient temperature of a forward voltage of a diode by a fluctuation of a gate source voltage of a first field effect transistor (FET). CONSTITUTION:A source follower is constituted by connecting in series a resistance R4 and a diode D between the reference potential (ground) and a negative power source Vss, and connecting in series a first FET1 which is greatly influenced by a temperature variation and a second FET2 which is scarcely influenced by a temperature variation, and the anode potential of the diode D is outputted to this source through a gate of a first FET1. A fluctuation caused by a variation of an ambient temperature of a forward voltage of the diode D is compensated due to a fact that a gate - source voltage of a first FET1 is fluctuated in accordance with a drain - source current of a roughly prescribed value of a second FET2. In such a way, a constant stable voltage is always generated to a power supply voltage without being influenced by a temperature variation of the periphery, and also, by following up a fluctuation of the power supply voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a constant voltage generation circuit, and particularly to a constant voltage circuit using a Schottky gate type IU field effect transistor (MESFET).

[Conventional technology]

Conventionally, the output section of a semiconductor circuit was source-coupled, FE
When configured with a T-logic (SCF L), a source follower, etc., the gate of the field effect transistor (FET) that serves as the current source for these transistors is, for example, shown in Figs. 6(a) and (b).
A predetermined voltage is applied by the circuit shown in
A predetermined gate-source voltage is obtained between the source connected to SS.

Figure (a) shows that the power supply voltage is resistance-divided by resistors R1 and R2 connected in series between the negative power supply VSS and the ground, and the desired voltage is obtained from the terminal OUT at the connection point of these resistors R1 and R2. This is applied to the gate of a current source FET (not shown).

Further, in FIG. 2B, a plurality of diodes D1 to D3 such as a resistor R3 are connected in series between the negative power supply VSS and the ground. Then, by using the sum of the forward constant voltages generated between the respective terminals of these diodes D1 to D3, a constant voltage of a desired value is obtained from the terminal OUT at the connection point between the diode D1 and the resistor R3, and the constant voltage of the current source FET is obtained. This is the voltage applied to the gate.

[Problem to be solved by the invention]

However, in the conventional voltage supply circuit using resistor division shown in FIG. 6(a) with the above configuration, the voltage appearing at the output terminal OUT changes due to voltage fluctuations in the negative power supply VSS, and is always constant with respect to the negative power supply VSS. The problem is that a stable voltage cannot be obtained. Furthermore, the voltage supply circuit using a plurality of diodes D shown in FIG. 6(b) is different from the circuit shown in FIG. Similarly, negative power supply VSS
However, there is a problem in that it is not always possible to obtain a constant and stable voltage.

The present invention was made to solve these problems, and it is not affected by changes in ambient temperature and can always maintain a constant and stable voltage with respect to the power supply voltage by following fluctuations in the power supply voltage. The purpose is to provide a constant voltage circuit that generates a constant voltage.

[Means to solve the problem]

The present invention includes a resistor having one end connected to a reference potential, a diode having an anode connected to the other end of the first resistor, a cathode connected to a power supply, a drain connected to the reference potential, and a gate connected to the anode of the diode. a first FET whose drain is connected to the source of the first FET, and a second FET whose drain is connected to the source of the first FET and whose source is connected to a power supply, and the drain-source current of the second FET is influenced by changes in ambient temperature. is applied to the gate, and this current is applied to the gate of the first FE.
The gate widths of the first FET and the second FET are set such that a voltage is generated between the gate and source of the first FET, so that the drain-source current of the first FET is greatly affected by changes in ambient temperature when flowing through T. Ratio to J! J has been adjusted.

[1 action] 9 cycles of diode forward voltage 11! fl Fluctuations due to temperature changes are caused by the fact that the drain-source current of the second FET hardly changes regardless of changes in ambient temperature. This is compensated for by varying the gate-to-source voltage of one FET. Furthermore, fluctuations in the power supply voltage have little effect on the voltage between the terminals of the diode and the operation of the source follower.

〔Example〕

Next, the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram representing a first embodiment of the present invention.

In the same figure, one end of the resistor R4 is grounded to the reference potential, the other end of the resistor R4 is connected to the anode of the diode D, and this cathode is connected to the negative power supply VSS. A directional voltage is applied. The voltage between the terminals of diode D caused by this forward voltage,
That is, the potential of the anode of the diode D is applied to the gate of the first Schottky gate field effect transistor FETI. The drain of FETI is grounded, and the gate potential of FETI is transmitted to the output terminal OUT connected to the source.

Further, the source of FETI is also connected to the drain of a second Schottky gate field effect transistor FET2, and the source of this FET2 is connected to the negative power supply Vss. A voltage obtained by dividing the voltage between the terminals of the diode D by resistors R5 and R6 is applied to the gate of the FET2, and the voltage Vgs applied between the gate and source of the FET2 is between 0.3 and 0.3. 5 [The resistance value of each resistor R5 and R6 is set to be about ¥1, and the threshold voltage vth of FET2 is set to be around -0.3 [V], which will be described later. Like, FET
The drain-source current Ids of No. 2 is less affected by changes in ambient temperature. Note that FET1 and FET2 constitute a source follower circuit.

FIG. 2 is a graph showing the voltage/current characteristics of the diode D shown in FIG. 1, where the horizontal axis represents the forward voltage V and the vertical axis represents the forward current ■.

In the figure, curve 1 shown by a solid line represents the characteristics when the ambient temperature is at room temperature, and curve 2 shown by a broken line represents the characteristics when the ambient temperature rises to a certain extent from room temperature.

As can be understood from the figure, when current 1a is passed through diode D in the forward direction at room temperature, the voltage that appears between these terminals becomes Va, but when the ambient temperature where diode D is placed rises, the same current 1a is passed through diode D in the forward direction. Even when current is applied in the forward direction, the voltage appearing between the terminals drops to vb.

Therefore, diode D in the circuit shown in FIG. have characteristics.

Figure 3 shows the gate-source voltage Vgs (horizontal axis) and drain-source current Ids (vertical axis) of a typical MESFET.
This is a graph showing the relationship between

In the figure, curve 3 shown by a solid line represents the characteristic when the ambient temperature is at room temperature, and curve 4 shown by a broken line represents the characteristic when the ambient temperature rises to a certain extent from the room temperature state. As understood from the figure, the drain-source current Ids of the MESFET flows when the gate-source voltage VgS is higher than the threshold voltage vth, and increases as the voltage Vgs increases. Also, the fluctuation of the current 1ds with respect to the change in ambient temperature is the voltage Vss force (voltage Vth + 0.2 to 0.4) [
V], the current 1ds increases as the temperature rises, and then the voltage Vss increases (voltage Vth+0.8 to 1.
0) Almost no change near [V]. For example, a MESFE with a voltage vth of about -0.3 [V] as shown in the figure
In the case of T, the current is 1d when the voltage Vgs is around 0 [v]
The variation in s is the largest, and the voltage VgS is 0.5 [
When the voltage Vgs is around 0.5 [V], the fluctuation of the current 1ds is the largest, and when the voltage Vgs is around 0.5 [V], it has almost no effect.

Therefore, the gate-source voltage Vds is 0.3 to 0.
The FET 2, which is set to about 5 V, is in a state where its drain-source current 1 ds is almost unaffected by changes in ambient temperature.

In addition, the structure of FETI is such that its gate width is 2 to 10 times larger than the gate width of FET2.
When the gate width of FETI 2 is 10 μm, the gate width of FETI is 40 μm. Furthermore, FET
1 has the same drain-source current as FET 2, 1 ds.
flows, and the voltage Vgs of FET2 is 0.3 to 0.5
Since it is set to about [V], the voltage of FET1 V
As shown in FIG. 3, gs is around 0 [V], where the influence of temperature changes is large.

In such a configuration, resistor R4 and diode D
A negative power supply Vss is applied to the series circuit of the diode D
A forward voltage V is applied between the terminals of , and a forward current ■ flows into the negative tti[Vss. PN of this diode D
A stable voltage is generated between the junctions, and the anode potential of diode D is transmitted to this source via the gate of FETI, so a constant and stabilized voltage is output to the output terminal OUT with respect to the negative power supply VSS. Ru.

When the ambient temperature rises, the anode potential of diode D decreases as described above (the voltage between the anode and cathode decreases), but this anode potential decreases due to the following action of the source follower composed of FETI and FET2. The decrease in voltage is compensated for, and a constant and stable voltage is always output with respect to the negative power supply Vss.

That is, a substantially constant drain-source current 16s flows through the FET 2 regardless of the rise in ambient temperature. In other words, the drain/source current 1ds of FET1 is also supplied with almost no fluctuation. For this reason, the gate of FETI
The source-to-source voltage Vgs decreases under the influence of changes in ambient temperature, and the gate potential of the FETI increases as the temperature rises, thus having positive characteristics with respect to temperature changes. Therefore, a decrease in the anode potential of diode D, which has a negative characteristic with respect to the ambient temperature, is compensated for by an increase in the gate potential of the FETI, which has a positive characteristic, and the voltage output from the output terminal OUT is always maintained regardless of changes in the ambient temperature. remains constant.

Further, a decrease in the voltage between the terminals of the diode D due to an increase in the ambient temperature is also transmitted to the gate of the FET 2 as a decrease in the voltage divided by the resistors R5 and R6. However, the decrease in the gate potential of 20FET2 is slight, and the effect is to promote the positive characteristic of the gate potential of FETI as shown below. This compensates for the negative characteristics of the anode potential.

In other words, due to a slight decrease in the gate potential of FET2, FET2
The drain-source current 1ds of ET2 also decreases slightly. This decrease in the current Ids of FET2 is caused by the current Ids of FET2.
The current Ids decreases by 1ds, and the gate-source voltage Vgs of the FET 1 decreases as the current Ids slightly decreases. Therefore, the gate potential of FET1 rises slightly, promoting this positive characteristic.

Furthermore, even if the voltage supplied from the negative power supply VsS fluctuates,
Since it does not affect the voltage generated between the terminals of diode D, and the operation of the source follower is almost unaffected by fluctuations in the power supply voltage, the voltage output to the output terminal OUT is negative [[Vss]. It follows fluctuations and is always kept at a constant 7u pressure with respect to this negative power supply VSS.

Therefore, the voltage output from the constant voltage circuit according to the above embodiment is not affected by changes in ambient temperature, and always remains constant with respect to the power supply voltage, following fluctuations in the power supply voltage.

Note that in the above embodiment, the gate-source voltage Vgs of FET2 was set to about 0.3 to 0.5 [V], but this is because the threshold voltage of MESFET is -0.3 [V].
[V], and this 0 is less affected by changes in ambient temperature.
．． It is Takara around 3 to 0.5 [V]. Therefore, it is necessary to appropriately change the gate ψ source voltage Vgs of the FET 2 depending on the threshold voltage of the FET used. Also, the FE using the gate width of FET1 for FET2
Similarly, it is necessary to change it appropriately depending on the characteristics of T.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention, and the same parts as those in FIG.

In the figure, instead of the diode D in the first embodiment, three diodes D5 to D7 are connected to a resistor R4 and a negative power supply VS.
The gate of FETI is connected to the connection point between resistor R4 and diode D5. Also, F
A voltage obtained by dividing the voltage across the terminals of the diode D7 by resistors R5 and R6 is applied to the gate of ET2, and as in the first embodiment, the gate-source voltage Vgs of FET2 is affected by changes in ambient temperature. is set to a lower voltage. Also, at this time, the ratio of the gate width of FETI to the gate width of FET2 is the drain of FET1.
The FETI is set to obtain a gate-source voltage such that the source current is greatly affected by changes in ambient temperature.

The feature of this second embodiment is that the voltage output to the output terminal OUT can be adjusted by the number of connected diodes.
The voltage obtained at the output terminal OUT when 7 is connected is
The voltage is higher than the negative power supply Vss by the forward voltage of three diodes, and a voltage three times higher than that of the first embodiment using one diode is obtained. The number of diodes connected can be selected arbitrarily. Also in this embodiment, the voltage obtained from the output terminal OUT is
Due to the action of the source follower composed of I and FET2, the current is always constant and unaffected by changes in ambient temperature. In addition, it also follows power supply voltage fluctuations, and is always constant with respect to the power supply voltage.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention, and the same parts as in FIG. 4 are denoted by the same reference numerals, and the explanation thereof will be omitted.

The figure shows FETI and FET2 in the second embodiment.
This embodiment has source followers connected in three stages, and the other circuit connections are the same as in the second embodiment shown in FIG. In other words, the source follower 2 in the second stage 11 and the source follower 3 in the third stage are configured similarly to the source follower 1 in the first stage, and the FET is connected between the ground and the negative power supply Vss.
I and FET2 are connected in series. The source of FET1, which is the output of the first stage source follower 1, is connected to the gate of FET1, which is the input of the second stage source follower 2, and the source of FETI, which is the output of the second stage source follower 2, is connected to the third stage source follower 2. It is connected to the gate of FETI which is the human power of the second source follower 3, and the source of FETI which is the output of the third stage source follower 3 is connected to the output terminal OUT of the constant voltage circuit. In addition, FET2 of each stage
The gates of the FETs are connected to each other, and a voltage divided by resistors R5 and R6 is applied equally to these gates, and the drain-source current Ids of each FET2 is set so as to be less affected by changes in ambient temperature. There is.

In such a configuration, each of the three diodes D5 to D
A forward voltage is applied to 7 by the negative power supply VSS, and the sum voltage of the stable voltages generated between each PN junction appears at the anode of diode D5.

This sum voltage is the F
It is transmitted between the gate and source of ET1, and a voltage higher than the negative power supply VSS by this sum voltage is stabilized and output to the output terminal OUT.

Moreover, when the ambient temperature rises, each diode D5 to D7
Each diode D5
The forward voltage of ~D7 decreases, and the potential appearing at the anode of diode D5 decreases significantly. This potential drop corresponds to three times as much as when one diode D is used in the first embodiment shown in FIG. However, this drop in potential due to changes in ambient temperature is compensated for by the three stages of source followers 1 to 3 as follows.

In other words, the FET 2 of the first stage source follower 1 has a constant drain-source current 1 regardless of changes in the ambient temperature.
6s flows, and this current 1ds is simultaneously applied to FET1 without any change. Therefore, the gate-source voltage Vgs of the FETI decreases under the influence of changes in ambient temperature. Therefore, the anode potential of the diode D5 is compensated by the potential drop of one diode by the FETI of the first stage source follower 1.

The potential compensated by one diode is further applied to the source follower 2, and by the similar action of the FETI and FET2 that constitute this source follower 2, this two
The gate-source voltage Vgs of the FETI in the second stage decreases, and the anode potential of the diode D5 further decreases to that of the diode 1.
The third stage source follower 3
is output to. The potential that has been compensated for the voltage drop of two diodes is further input to the third stage source follower 3.
Similarly to the first and second stage source followers 1 and 2, the voltage drop of one more diode is compensated for.

As a result, the potential drop due to the change in ambient temperature of each of the diodes D5 to D7 appearing at the anode of the diode D5 is 3
Compensated by the source followers 1 to 3 of the stage, the voltage appearing at the output terminal OUT is always constant and unaffected by changes in ambient temperature.

Further, a decrease in the voltage between the terminals of the diode D7 due to an increase in the ambient temperature is transmitted to the gates of the FETs 2 in each stage as a decrease in the voltage divided by the resistors R5 and R6. However, the decrease in the gate potential of the FET2 in each stage is slight, and the effect of the source followers 1 to 3 is to promote the positive characteristic of the gate potential of the FETI in each stage as described above. together with diode D5
This compensates for the negative characteristic of the anode potential of the output terminal OUT, and the voltage obtained at the output terminal OUT becomes more stable against changes in ambient temperature.

Further, the voltage output from the constant voltage circuit according to the third embodiment also follows the fluctuation of the negative power supply VSS, and the voltage output from the output terminal OUT
The voltage obtained is always constant with respect to the negative power supply Vss. This is because the forward voltage generated between the terminals of each of the diodes D5 to D7 is not affected by voltage fluctuations of the negative power supply VSS.

In addition, in the above embodiment, three diodes D5 to D
The temperature change of 7 was compensated for using three stages of source followers 1 to 3, but by changing the gate + R structure of each FETE and 2 that constitute source followers 1 to 3, the number of stages of source followers could be increased. The number of stages of this source follower can be arbitrarily selected.

Furthermore, the ratios of the gate widths of the FETs in each of the lease followers 1 to 3 may be different, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As explained above, the present invention connects a resistor and a diode in series between a reference potential and a power supply, and connects a first FET that is largely affected by temperature changes and a second FET that is less affected by temperature changes.
ET in series to form a source follower, and the anode potential of the diode is output to this source via the gate of the first FET. The fluctuation is the second
The drain-source current of the first field-effect transistor hardly changes due to changes in ambient temperature, and the gate-to-source voltage of the first field-effect transistor changes in accordance with this almost constant value of drain-source current to compensate for this. be done. Further, fluctuations in the power supply voltage have little effect on the voltage between the terminals of the diode D and the operation of the source follower.

For this reason, it is possible to create a constant voltage circuit that is not affected by changes in ambient temperature and that always generates a constant and stable voltage with respect to the power supply voltage by following fluctuations in the power supply voltage. have an effect.

output transistor, VSS...negative power supply, OUT...output terminal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the first embodiment of the present invention, FIG. 2 is a graph showing the voltage V-current characteristics of the diode D used in this embodiment, and FIG. 3 is a graph showing the voltage V-current characteristic of the diode D used in this embodiment. Gate-source voltage Vgs of MESFET used in
A graph showing the relationship between and drain-source current 1ds,
FIG. 4 is a circuit diagram representing a second embodiment of the present invention, FIG. 5 is a circuit diagram representing a third embodiment of the present invention, and FIG. 6(a)
, (b) are circuit diagrams showing a conventional configuration. D...Diode, R4...Resistor, FETI, FE
T2... 1st. Second Schottky gate field effect patent applicant Sumitomo Electric Industries, Ltd.

Claims (1)

[Claims] 1. A resistor whose one end is connected to a reference potential, and a diode whose anode is connected to the other end of the first resistor and whose cathode is connected to a power source that outputs a voltage lower than the reference potential. a first field effect transistor having a drain connected to the reference potential and a gate connected to the anode of the diode; a drain connected to the source of the first field effect transistor and a source connected to the power source; Second
A voltage is applied between the gate and source of the second field effect transistor so that the drain-source current of the second field-effect transistor is less affected by changes in ambient temperature; The gate width of the first field effect transistor and this second field effect transistor
The ratio of this to the field effect transistor gate width is this second
The gate-source voltage at which the drain-source current of the first field-effect transistor is largely affected by changes in ambient temperature is such that when the drain-source current of the first field-effect transistor is less affected by changes in ambient temperature,
outputs to the source of the first field effect transistor a voltage that is always stabilized at a constant level with respect to the power supply voltage by the forward voltage generated between the terminals of the diode. A constant voltage generation circuit characterized by: 2. The diode is composed of multiple series connections, and the first
2. The constant voltage generating circuit according to claim 1, wherein the voltage output from the source of the field effect transistor is adjusted by the number of diodes. 3. A claim comprising a plurality of stages of source followers each consisting of a first field effect transistor and a second field effect transistor, and compensating for ambient temperature changes in the forward voltage of one or more diodes. The constant voltage generating circuit according to item 1.