JPH02174257A - Cmos integrated circuit device - Google Patents

Abstract

PURPOSE:To enable output signal of a high-speed CMOS integrated circuit to be transmitted without any deformation of waveform by providing a resistor between the output node of the CMOS integrated circuit chip and the connection pad of an external circuit of that node. CONSTITUTION:The output buffer of a CMOS integrated circuit chip 10 consists of a p-channel MOS transistor 11 where a source is connected to a VDD wire 131 and an n-channel MOS transistor 12 where the source is connected to a VSS wire. A resistor 15 is provided between the output node of this output buffer and a connection pad 16 to the outside of the integrated circuit chip 10 corresponding to it. The resistor 15 consists of a polycrystal silicon film or a diffusion layer. The resistor 15 is set so that the sum of the resistance and the output impedance of the output buffer is equal to the characteristics impedance of signal path connected to the output terminal of this integrated circuit.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a high-speed operating CMOS integrated circuit device.

(Prior Art) Due to the demand for faster speeds of various information processing systems, there is also a demand for faster speeds of semiconductor integrated circuits used therein. S is a typical integrated circuit that performs high-speed logic operations.
There is ECL which uses i. GaAs logic integrated circuits that utilize high electron mobility characteristics are also attracting attention as capable of high-speed logic operation. Recently, much progress has been made in increasing the speed of CMOS integrated circuits.

In order to increase the speed of CMOS integrated circuits, it is necessary to increase the current driving capability of the output buffer 7 so that the load capacitance can be charged at high speed. With the increase in the current drive capability of such output buffers, reflections due to impedance mismatch with the signal line to which they are connected have become a problem. This problem will be specifically explained with reference to FIG. Figure 4(a)
, 41 and 44 are CMOS integrated circuits, which are mounted, for example, on a printed circuit board and connected via a signal line 43. 42 is an output buffer of the integrated circuit 41. If the driving capacity of the output buffer 42 of the CMOS integrated circuit 41 is sufficiently increased in order to increase the speed, the output impedance thereof becomes smaller than the characteristic impedance of the signal line 43. Then, when trying to transmit a signal from the CMOS integrated circuit 41 to 44, the signal incident on the 0 point is almost completely reflected with a positive reflection coefficient because the input impedance of the CMOS integrated circuit 44 is high.
When returning to point B, reflection with a negative reflection coefficient (that is, accompanied by phase inversion) occurs because the output impedance of the CMOS integrated circuit 41 is small. As a result of these signal reflections, as shown in FIG. 4(b), a ringing waveform as shown by a solid line is generated at the 0 point with respect to the signal (dashed line) at the input terminal A to the l-press CMOS integrated circuit 41. This signal waveform distortion is a major cause of hindering the normal logic operation of the system.

As a way to solve this problem, as shown in Figure 5,
It is conceivable to provide a matching resistor 45 at the signal receiving end. If the resistance value of the matching resistor 45 is set equal to the characteristic impedance of the signal line 43, signal reflection at two points can be prevented. However, if such a receiving end termination method is adopted, the excellent advantage of the low power consumption characteristic of the CMOS integrated circuit is lost because the DC current 7 flows here. In addition, with this method, the level of the "H° level signal manually inputted to the next stage is limited, and the advantage of a large noise margin is lost. Furthermore, with this method, a matching resistor is placed on the printed circuit board. This means that as the number of bins in integrated circuits increases, a large number of matching resistors must be placed on the printed circuit board, making it difficult to increase the mounting density on the printed circuit board.

(Problems to be Solved by the Invention) As described above, when attempting to eliminate signal transmission distortion when high-speed CMOS integrated circuits are implemented using conventional methods, CMOS
There were problems in that the low power consumption characteristics of the integrated circuit were impaired, the noise margin was reduced due to a reduction in logic amplitude, and the mounting efficiency was reduced.

An object of the present invention is to provide a CMOS integrated circuit device that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) A CMOS integrated circuit device according to the present invention includes a resistor connected in series to an output terminal of a CMOS integrated circuit chip within the chip or within a package in which the chip is mounted. It is characterized by having been established.

(Function) According to the present invention, the resistance value of the resistor inserted in series with the output terminal of the integrated circuit chip is set so that the sum of this and the output impedance of the output buffer is equal to the characteristic impedance of the signal line provided externally. By setting
Signal reflection at this output terminal section is prevented. Moreover, in this case, since a direct current path is not formed as in the termination method described in the conventional example, the low power consumption characteristics of the CMOS integrated circuit are not impaired, and the characteristics of low noise margin are also not impaired. Moreover, by incorporating the above-described resistor into an integrated circuit chip or a package that houses the chip, the mounting efficiency on the printed circuit board will not be reduced.

(Example) The present invention will be explained in detail below.

FIGS. 1(a) and 1(b) are circuits and layouts showing the main structure of an embodiment. 1o is a CMOS integrated circuit chip, and only its output section is shown in the figure. A p-channel Mos transistor 11 whose source is connected to the VOO wiring 131 and an n-channel Mos transistor 11 whose source is connected to the VSS wiring.
Output buffer 7 by channel MOS transistor 12
is configured. 14 is a common gate wiring.

A resistor 15 is provided between the output node of this output buffer and a corresponding connection pad 16 to the outside of the integrated circuit chip 10. The resistor 15 is formed of a polycrystalline silicon film or a diffusion layer.

The resistor 15 is set so that the sum of its resistance value and the output impedance of the output buffer is equal to the characteristic impedance of the signal line connected to the output terminal of this integrated circuit. Here are some specific examples. MOS that constitutes the output buffer
) Gate width/gate length of transistor 11゜12 is 512
Suppose that it is μm/1 μm. At this time, the output impedance of this output buffer is approximately 35Ω. This CMOS
If a signal line with a characteristic impedance of 75Ω is used to transmit the output signal of the integrated circuit chip, the resistance value of the resistor 15 provided at the output terminal should be approximately 40Ω.
Set to .

FIGS. 3(a) and 3(b) show how signals are transmitted in the CMOS integrated circuit according to this embodiment, corresponding to the conventional FIGS. 4(a) and 4(b). 31 and 35 are CMOS integrated circuit chips, and a resistor 33 is provided between the output node of the output buffer 32 of the integrated circuit chip 31 and the connection pad. Mounting such a chip 31.35 on a printed circuit board,
A signal line 34 connects the two. The above relationship exists between the output impedance of the output buffer 32, the resistor 33, and the signal line 34.

At this time, as shown in FIG. 3(b-), the signal (broken line) at the input terminal A of the CMOS integrated circuit chip 31 is transmitted to the integrated circuit chip 31 with a certain delay time without causing almost any waveform distortion. is transmitted to the input terminal C point (solid line).

In the method of this embodiment, unlike the conventional receiving end termination method, no direct current path is formed, so the low power consumption characteristics of the CMOS integrated circuit are not impaired, and the logic amplitude does not decrease. Since the resistor for impedance matching is formed within the chip, high-density mounting on a printed circuit board is not hindered.

FIGS. 2(a) to 2(d) are equivalent circuits and layouts showing the main structure of another embodiment. (c) and (d) are enlarged views of areas A and B in (b), respectively. Portions corresponding to those in the previous embodiment are designated by the same reference numerals as in the previous embodiment, and detailed description thereof will be omitted. In this embodiment, a CMOS integrated circuit chip 10 is mounted on a package 20 and its terminals are connected by bonding wires 17.

In this embodiment with such a configuration, a resistor 15' for output impedance matching is formed on the package 20 and inserted in series between the lead 21 and the output terminal of the chip 10. The resistor 15' can be formed in various ways depending on the package manufacturing process. The most common method is thick film printing. That is, a resistor 15' is obtained by printing a resistor paste at a predetermined position and firing it. Alternatively, a thin film resistor such as TaN or NiCr may be used.

This embodiment also provides the same effects as the previous embodiment.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to configure a system that transmits output signals of high-speed CMOS integrated circuits without waveform distortion, without impairing the advantages of CMOS integrated circuits or reducing implementation efficiency. It becomes possible.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are diagrams showing an equivalent circuit and layout showing the main part configuration of an embodiment of the present invention, and FIGS. 2(a) to (d)
3(a) and 3(b) are diagrams for explaining the characteristics of signal transmission in the embodiment of FIG. 1, and FIG. Figure 4 (a) (b)
5 is a diagram for explaining the state of signal transmission when a conventional CMOS integrated circuit is used, and FIG. 5 is a diagram for explaining a conventional receiving end matching method. 10...CMOS integrated circuit chip, 11...p channel MOS) transistor, 12...n channel MOS
Transistor, 131...vDD wiring, 132...
VSS wiring, 14... Gate wiring, 15°15'...
-Resistor, 16... Connection pad, 20... Package, 21... Lead.

Claims (2)

[Claims] (1) A CMOS integrated circuit device characterized in that a resistor is interposed between an output node of a CMOS integrated circuit chip and a connection pad of that node with an external circuit. (2) A CMOS integrated circuit chip is housed in a package, and a resistor provided on the package is connected between the output terminal of the CMOS integrated circuit chip and the corresponding lead terminal on the package. A CMOS integrated circuit device characterized by: