JPH02172316A - Clamp circuit - Google Patents

Abstract

PURPOSE:To attain clamping with high accuracy by providing a delay circuit controlling an interruption timing to match the cut-off characteristic of a bipolar transistor(TR) with a bias circuit. CONSTITUTION:When a clamp pulse level is low, an N-channel TR(NTR) being a current source of a differential amplifier section 2 is turned off and an NTR 12 of a complementary output stage 3 is turned on an a PTR 11 is turned off. However, the timing of the PTR 11 when it is turned off is slower than that of the PTR 11 and the NTR 12 of the output complementary stage 3, resulting in causing a time difference. In order to eliminate the time difference, a delay circuit 5 is inserted to the bias circuit comprising the NTR 12 to match the off-timing of the PTR 11, then no charge flow from an output terminal of the clamp circuit to a voltage storage capacitor 7 is not caused. Thus, clamping with high accuracy is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clamp circuit suitable for processing video signals of televisions, video cameras, personal computers, and the like.

2. Description of the Related Art In general video signal processing for televisions, videos, etc., clamp circuits are used to reproduce DC levels of luminance signals and color difference signals. The DC reproduction accuracy of this clamp circuit is important in determining the brightness and color reproduction performance.

One method of configuring a clamp circuit is to switch an operational amplifier (hereinafter referred to as a clamp amplifier) with an amplification factor of approximately 1 using a clamp pulse. FIG. 2 shows the configuration of this clamp circuit.

In FIG. 2, 10 is a video signal input terminal, 7 is a voltage holding capacitor, 4 is a reference DC voltage source for clamp level health, 11 is an operational amplifier, 1 is a clamp pulse input terminal for switching the clamp circuit, and 9 is a clamp pulse input terminal for switching the clamp circuit. This is a video signal output terminal.

With one of the video composite signal, video luminance signal, or video color difference signal being input to the video signal input terminal 10, a clamp pulse synchronized with this signal is input from the clamp pulse input terminal 1. The clamp circuit operates from the moment the clamp pulse is at a high level, and the DC voltage at the video output terminal 9 becomes
The voltage value of the reference voltage source 4 becomes V ref . At the same time, at the instant of the high level of the clamp pulse, the potential difference between the voltage of the input signal during the clamp setting period and the reference voltage V r e f is maintained by the voltage holding capacitor. The pedestal section during the video signal blanking period is normally used as this clamp setting period. In this case, a video signal obtained by DC reproducing the potential of the pedestal portion to the value of the reference voltage Vref is output from the video output terminal 9.

Problems to be Solved by the Invention However, when the output stage of the off-amplifier has a complementary configuration, the cutoff characteristics of the N-channel transistor and the P-channel transistor do not match. In other words, P
Since the cut-off speed of the channel transistor (hereinafter referred to as PTr) is slower than that of the N-channel transistor (hereinafter referred to as NTr), charge flows from the clamp amplifier into the voltage holding capacitor, and a sub-voltage is generated. For this reason,
There is a problem in that current flows from the capacitor to the amplifier at the instant when the clamp amplifier turns on again after being cut off, and a voltage fluctuation occurs between this current and the impedance of the input signal source.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a clamp circuit in which direct current fluctuations that occur when the clamp circuit is turned on and off are extremely small.

Means for Solving the Problems In order to achieve the above object, the clamp circuit of the present invention has the following features:
By installing an on/off delay circuit in the bias circuit of the output stage NTr, it is possible to match the on/off characteristics of the PTr.

NT that configures the output stage of the action clamp circuit in a complementary manner
r and PTr can be turned off simultaneously.

Example Embodiments of the present invention will be described below with reference to FIG.

In FIG. 1, 1 is a clamp pulse input terminal for operating the clamp circuit, 2 is a differential amplifier section within the clamp amplifier, 3 is an output section of a complementary configuration within the clamp amplifier, 4 is a reference voltage source for the set Vref voltage, 5 is upper row 2
and 3, a delay circuit that supplies bias, 6 an oscillation prevention capacitor, 7 a voltage holding capacitor, 8 a video signal source, 9 a video signal output terminal, 10 a video signal input terminal, 1
1 is the output stage PTr, 12 is the output stage NTr, 13 is the PT
r drive transistor. The operation of the clamp circuit of this embodiment will be explained below.

With the video signal input to the video signal input terminal, a clamp pulse synchronized with the video signal is input from the clamp pulse input terminal. When the clamp pulse is at a high level, a bias is applied to the present clamp pulse circuit, and the circuit is turned on and operates, and the video signal output terminal voltage, which is a complementary output, becomes the reference voltage value Vref. Also, when the clamp pulse level is low, the current source of the differential amplifier section, NTr
is turned off, and at the same time, NTr of the complementary output stage is turned off. At this time, the drive transistor of PTr is turned on and PTr is turned off. However, the timing at which PTr and NTr of the output complementary stage are turned off is
is slower and there is a time difference. To cancel this time difference, N
By inserting a delay circuit into the bias circuit of the Tr and adjusting the off timing of the PTr, no charge flows from the output terminal of the clamp circuit to the voltage holding capacitor.

As described above, according to this embodiment, by inserting a delay circuit into the bias circuit of the NTr, complementary outputs are simultaneously cut off and a highly accurate clamping operation is realized.

Effects of the Invention According to the present invention, it is possible to perform a clamp operation for highly accurate DC reproduction of a video signal, thereby enabling high-performance video signal processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a clamp circuit according to the present invention, and FIG. 2 is a block diagram of a clamp circuit using a general operational amplifier. 1... Clamp pulse input terminal, 2...
・Differential amplifier section, 3... Complementary output section, 4... Reference voltage source, 5... Delay circuit, 6... Oscillation prevention capacitor, 7・・・・・・
・Voltage holding capacitor, 8...Video signal source,
9...Video signal output terminal, 10...Video signal input terminal, 11...Output stage P channel transistor, 12...Output stage N channel transistor 13...P-channel transistor drive transistor.

Claims (1)

[Claims] In a circuit where the output stage configuration is a complementary transistor in which the potential of a voltage holding capacitor is used as a clamp potential, a clamp circuit has a delay circuit that controls the cutoff timing to match the cutoff characteristics of the bipolar transistor to the bias circuit.