JPH02168820A - Charge/discharge switching device for battery - Google Patents

Charge/discharge switching device for battery

Info

Publication number
JPH02168820A
JPH02168820A JP32109388A JP32109388A JPH02168820A JP H02168820 A JPH02168820 A JP H02168820A JP 32109388 A JP32109388 A JP 32109388A JP 32109388 A JP32109388 A JP 32109388A JP H02168820 A JPH02168820 A JP H02168820A
Authority
JP
Japan
Prior art keywords
battery
transistor
charging
voltage
microcomputer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32109388A
Other languages
Japanese (ja)
Inventor
Tatsu Morioka
森岡 達
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP32109388A priority Critical patent/JPH02168820A/en
Publication of JPH02168820A publication Critical patent/JPH02168820A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the dimension and the cost, in a charger provided with a discharging circuit, by switching between charging operation and discharging operation through a transistor circuit. CONSTITUTION:Output terminal P1 of a microcomputer has a high level during initial quick charge operation of a battery B, thereby transistors Q1, Q2 are turned ON and current flows through the transistor Q3 and a diode D thus charging the battery B. When the battery B is fully charged, the output terminal P1 has a low level thereby the transistors Q1, Q3 are turned OFF thus charging the battery B only with current flowing through the diode D. When the output terminal P2 of the microcomputer has a high level, transistors Q2, Q4 are turned ON thus discharging the battery B through the transistor Q4 and a resistor R9.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は放電回路を具備した蓄電池の充電装置に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a storage battery charging device equipped with a discharge circuit.

(ロ)従来の技術 電気機器、例えばカメラ一体型ビデオの電源として用い
られるNi−Cd電池のバッテリパックの場合、電池の
放電が進みその出力電圧がモータ等の負荷駆動闇値電圧
(1セル当り1.15〜1.18■)以下に低下すると
電池消耗の状態となり、電池を充電する必要が生しる。
(b) Conventional technology In the case of a Ni-Cd battery pack used as a power source for electrical equipment such as a camera-integrated video, the battery discharges and its output voltage increases to the load driving dark value voltage (per cell) of a motor etc. 1.15 to 1.18) or less, the battery becomes exhausted and it becomes necessary to charge the battery.

ところで負荷駆動のための閾値電圧は通常電池の放電終
止電圧よりも高めに設定されており、電池の充電時には
絶えず少量の残存容量が残っていることになる。
By the way, the threshold voltage for driving the load is usually set higher than the end-of-discharge voltage of the battery, and a small amount of remaining capacity always remains when the battery is being charged.

第4図に示すように放電終止電圧まで放電させた電池(
B、)を−置溝充電まで充電し、再び放電させるとき、
この操作を何度繰返してもその放電特性に大きな変化は
見られない。一方上述の如く残存容量のある電池(B2
)を満充電まで充電し再び残存容量が存在する程度まで
放電させるという充放電サイクルを繰返した場合にはそ
の放電特性において放電終止電圧まで放電させた電池(
B、)に比へてその端子電圧のレベルが下がる(図中破
線て示される)という現象が生じる。この現象は電池の
メモリ効果と呼ばれるものであり、端子電圧の変化によ
って電池の満充電を検出する場合において、残存容量の
ある電池の場合、予め設定された満充電状態になった以
後も更に充電が続くという問題点があった。
As shown in Figure 4, the battery (
When B,) is charged to -position charge and discharged again,
No matter how many times this operation is repeated, no significant change is observed in the discharge characteristics. On the other hand, as mentioned above, the battery with remaining capacity (B2
) is charged to full charge and then discharged again to the extent that there is residual capacity.
A phenomenon occurs in which the level of the terminal voltage decreases (indicated by a broken line in the figure) compared to B,). This phenomenon is called the battery memory effect, and when detecting a battery's full charge based on a change in terminal voltage, if the battery has remaining capacity, it will not be possible to charge it further after reaching the preset full charge state. The problem was that it continued.

また斯かる電池のメモリー効果は残存容量のある電池を
一回放電終止電圧まで強制的に放電せしめ、満充電まて
充電した後もう一回同しことを繰り返せば除去されるこ
とが経験上よく知られている。
In addition, experience has shown that the memory effect of a battery can be eliminated by forcibly discharging a battery with remaining capacity once to the end-of-discharge voltage, charging it to full capacity, and then repeating the same process once again. Are known.

尚蓄電池の充電を始める前に一旦蓄電池を放電させて全
ての蓄電池の初期容量を同じくし、均一な充電を行なう
(特公昭60−31175号公報参照)ものがあるが、
−回の放電では電池のメモリー効果は除去されないので
、電池の端子電圧検出型の充電制御方式ては正確な満充
電検出を行うことができないという問題点かあった。
In addition, before starting to charge the storage batteries, there is a system that discharges the storage batteries once to make the initial capacity of all the storage batteries the same and perform uniform charging (see Japanese Patent Publication No. 31175/1983).
Since the memory effect of the battery is not removed by - times of discharge, there is a problem in that a charging control system that detects the terminal voltage of the battery cannot accurately detect full charge.

第5図に従来の放電回路付充電回路の一例を示ず。同図
において、+IC,++は蓄電池(B)の満充電時の電
圧を検出して成るマイクロコンピユーと り(以下マイコンj称す) 、 (R1)(R1□)は
該マイコン(Ice)の−出力端子(Pl)とアース間
に介挿される分圧抵抗、(Ql)は該分圧抵抗(Rt)
(R,+□)の分圧点にベースを接続し、コレクタ側を
抵抗(R2)を介して電圧源(vll)に接続したエミ
ッタ接地のPNP型第1 ?−ランジスタ、(R4t(
Rt3)は前記マイコン(i、c、)の他の出力端子(
R2)とアース間に介挿される分圧抵抗、(Q2)は該
分圧抵抗fR4i (Rt3)の分圧点にベースを接続
し、コレクタ側をリレコイル(Ryjを介して前記第1
 t−ランジスタ(Q、)のコレクタ抵抗(R2)に接
続したエミッタ接地のPNP型第2トランジスタ、(Q
3)はそのベースをベース抵抗(R3)を介して前記第
1トランジスタ(Ql)のコレクタ端子に接続し、エミ
ッタ端子を充電電源N型第3トランジスタ、(D)は該
第3トランジスタ(Q3)のエミッターコレクタ間に抵
抗(R6)と前記リレーコイル(1’ly)の励磁によ
り閉じる常閉型第1リレースイツチ(C5)とを介して
接続される逆流防止用ダイオード、(+t、+oHn+
+)は前記電池(B)と並列に且つ前記リレーコイル(
Ry)の励磁により閉じる常開型第2リレースイツチ(
C2)を介して接続されその分圧点に該電池(B)の端
子電圧に対応した電圧を発生させる分圧抵抗、(R9)
は該分圧抵抗(RtoJ (Rz)に並列に接続される
抵抗、(R7) (R8)は前記ダイオード(D)のア
ノード端子とアース間に接続され高抵抗値を有し電池(
B)の端子電圧に対応した電圧を分圧点に発生する抵抗
、(IC2)はその入力端子(■、)を前記分圧抵抗(
R30)fRll)間に接続し、入力端子(12)を前
記分圧抵抗(R7) (88)間に接続した電圧検出用
集積回路、(S)は前記マイコン(IC,+)の入力端
子(P、)に該入力端子(113iに電池が流れて前記
電池(B)の放電がスタートする。
FIG. 5 does not show an example of a conventional charging circuit with a discharging circuit. In the figure, +IC and ++ are microcomputer (hereinafter referred to as microcomputer j) that detects the voltage when the storage battery (B) is fully charged, and (R1) (R1□) is the - output of the microcomputer (Ice). The voltage dividing resistor inserted between the terminal (Pl) and the ground, (Ql) is the voltage dividing resistor (Rt)
The first PNP type with a common emitter whose base is connected to the voltage dividing point of (R, +□) and the collector side is connected to the voltage source (vll) via the resistor (R2). -Randister, (R4t(
Rt3) is the other output terminal (
The voltage dividing resistor (Q2) is inserted between the voltage dividing resistor fR4i (Rt3) and the ground, and its base is connected to the voltage dividing point of the voltage dividing resistor fR4i (Rt3).
A second PNP transistor (Q, ) with a common emitter connected to the collector resistor (R2) of the t-transistor (Q, )
3) has its base connected to the collector terminal of the first transistor (Ql) via the base resistor (R3), and its emitter terminal is connected to the charging power supply N-type third transistor; (D) is the third transistor (Q3); A backflow prevention diode (+t, +oHn+) connected between the emitter and collector of the resistor (R6) and a normally closed first relay switch (C5) that is closed by excitation of the relay coil (1'ly)
+) is connected in parallel with the battery (B) and in parallel with the relay coil (
A normally open second relay switch (
a voltage dividing resistor (R9) that is connected via C2) and generates a voltage corresponding to the terminal voltage of the battery (B) at its voltage dividing point;
are resistors connected in parallel with the voltage dividing resistor (RtoJ (Rz), (R7) and (R8) are connected between the anode terminal of the diode (D) and the ground and have a high resistance value, and are connected to the battery (
A resistor (IC2) that generates a voltage corresponding to the terminal voltage of B) at the voltage dividing point connects its input terminal (■,) to the voltage dividing resistor (IC2).
R30) fRll), and the input terminal (12) is connected between the voltage dividing resistor (R7) (88); (S) is the input terminal ( The battery flows to the input terminal (113i) and the discharge of the battery (B) starts.

この例において、電池(B)を回路にセット/1 し、電源tv、、、) +VB)をオンすルトマイコン
(Ice)の出力端子P、は「H」 (急速充電モード
)をとり、第1トランジスタ(Ql)及び第3トランジ
スタ(Q3)が導通して電池(B)に電源(VA)より
トランジスタ(Q、)の主電流路を通った大電流及び抵
抗(R6)、ダイオード(D)を通った小電流が同時に
供給される。充電中の電池(B)の端子電圧は分圧抵抗
(R7) (Re)で検出して集積回路(IC2)の入
力端子(1□)に入力する。電池(B)の端子電圧が満
充電時の電圧に達するとマイコン(Ice)で集積回路
(IC2)の入力を演算し、出力端子(Pl)の出力を
「L」にする。このことにより第1、第3トランジスタ
(Q+) ((hiはともに非導通となる。よって電池
(B)の充電は前記抵抗(R6)、ダイオード(D>を
通路る電流によるIリクル充電に切換わる。次にスイッ
チ(S>を閉成するとマイコン(Ice)の出力端子(
Pl)はFL」のまま出力端子(Pコイル(Ry’rが
閉成してリレースイッチ(C1)を開成し、リレースイ
ッチ(C2)を閉成する。この状態において電池(B)
は放電を開始し、抵抗(R7)及び(Rho) (R1
1)に放電電流が流れる。この放電電流は抵抗(Rho
) (R+ +)の分圧点電圧として集積回路(IC2
)の入力端子(I、)に取り込まれ、該電圧と放電完了
(1セル当つ1.OVに達するまでの)時間との積をマ
イコン(ICe)で演算して放電電流量を算出し電池(
B)の劣化を判定する。
In this example, the battery (B) is set in the circuit, the power supply tv, , +VB) is turned on, the output terminal P of the microcomputer (Ice) is set to "H" (quick charge mode), and the The first transistor (Ql) and the third transistor (Q3) conduct, and a large current flows from the power supply (VA) to the battery (B) through the main current path of the transistor (Q,), the resistor (R6), and the diode (D). A small current is supplied at the same time. The terminal voltage of the battery (B) during charging is detected by a voltage dividing resistor (R7) (Re) and input to the input terminal (1□) of the integrated circuit (IC2). When the terminal voltage of the battery (B) reaches the voltage at full charge, the microcomputer (Ice) calculates the input of the integrated circuit (IC2) and sets the output of the output terminal (Pl) to "L". As a result, both the first and third transistors (Q+) ((hi) become non-conductive. Therefore, charging of the battery (B) is switched to I-recycle charging by the current passing through the resistor (R6) and the diode (D>). Next, when the switch (S> is closed, the output terminal (
The output terminal (P coil (Ry'r) is closed to open the relay switch (C1), and the relay switch (C2) is closed. In this state, the battery (B)
starts discharging and resistors (R7) and (Rho) (R1
1) A discharge current flows through. This discharge current is caused by resistance (Rho
) (R+ +) as the dividing point voltage of the integrated circuit (IC2
) is taken into the input terminal (I, ) of the battery, and the microcomputer (ICe) calculates the amount of discharge current by calculating the product of the voltage and the time to complete discharge (until reaching 1.OV per cell). (
Determine the deterioration of B).

しかし乍ら上記の如く充電と放電の切換えをリレーを用
いて行なうものはトランジスタ回路で組む場合に比べて
プリント基板の寸法で5倍の大きさとなり、また製造コ
ストも約10倍ともなる問題点があった。
However, as mentioned above, when switching between charging and discharging using a relay, the size of the printed circuit board is five times larger than when it is assembled using a transistor circuit, and the manufacturing cost is also about 10 times higher. was there.

(ハ) 発明が解決しようとする課題 本発明が解決しようとする課題は電池のメモリー効果を
取り除く為、充電装置に放電回路を設けたものにおいて
、充電と放電の切換えをトランジスタ回路で組み、充電
器としての外形寸法を縮小し、且つ製造コストの低減を
図ることである。
(c) Problems to be Solved by the Invention The problems to be solved by the present invention are, in order to eliminate the memory effect of batteries, to use a transistor circuit to switch between charging and discharging in a charging device equipped with a discharging circuit. The objective is to reduce the external dimensions of the container and reduce manufacturing costs.

(ニ)課題を解決するための手段 マイクロコンピュータの一出力端子にベースを接続され
電池の充電時に導通ずる第1トランジスタと、前記マイ
クロコンピュータの他の出力端子にベースを接続され該
第1トランジスタの主電流路に直列接続される蓄電池と
、前記第3トランジスタのコレフタルエミッタ間に抵抗
を介して接続される逆流防止用ダイオードと、ベースを
前記第2トランジスタに接続され該第2トランジスタの
導通時に導通ずる第4トランジスタとより成る。
(d) Means for Solving the Problem A first transistor whose base is connected to one output terminal of the microcomputer and is turned on when charging a battery, and a first transistor whose base is connected to another output terminal of the microcomputer are connected. a storage battery connected in series to the main current path; a backflow prevention diode connected via a resistor between the corephthal emitter of the third transistor; and a fourth transistor that is conductive.

(ホ)作用 電池の充電は第1トランジスタの導通による第3トラン
ジスタの導通によりこの第3トランジスタの主電流路を
流れる電流によって行なわれるとともに同時に第3トラ
ンジスタのコレフタルエミッタ間の抵抗及びダイオード
を介しても行なわれる。
(e) Charging of the working battery is carried out by the current flowing through the main current path of the third transistor due to the conduction of the third transistor due to the conduction of the first transistor, and at the same time via the resistor and diode between the corephthal emitters of the third transistor. It is also done.

電池の放電時には第2トランジスタの導通による第4 
hランジスタの導通により、この第4トランジスタの主
電流路を流れる電流によって行なわれる。
When the battery is discharged, the fourth transistor is turned on due to the conduction of the second transistor.
This is done by the current flowing through the main current path of this fourth transistor due to the conduction of the h transistor.

マイコンは充電時の電池の端子電圧によって満充電を判
定し、放電時の放電電圧によって放電終了時の算出をす
る。
The microcomputer determines full charge based on the terminal voltage of the battery during charging, and calculates the end of discharging based on the discharge voltage during discharging.

(へ)実施例 第1図に本発明充放電切換装置の一実施例を示す。第5
図に示した従来のものと異なる点は第2トランジスタ(
C2)のコレクタ端子は第3トランジスタ(Q、)のコ
レクタ端子に主電流路を接続してなるコレクタ接地のN
PN型第4トランジスタ(C4)のベースに抵抗(R5
)を介して接続されるとともに、該第4トランジスタ(
C4)のコレクタ端子に抵抗(R9)及び(RIOI 
(R11+を接続した点であり、その他の構成は第1図
のものと同じである。
(F) Embodiment FIG. 1 shows an embodiment of the charge/discharge switching device of the present invention. Fifth
The difference from the conventional one shown in the figure is that the second transistor (
The collector terminal of C2) is connected to the collector terminal of the third transistor (Q, ) by connecting the main current path to the collector terminal of the third transistor (Q, ).
A resistor (R5) is connected to the base of the PN type fourth transistor (C4).
), and the fourth transistor (
A resistor (R9) and (RIOI) are connected to the collector terminal of C4).
(This is the point where R11+ is connected, and the other configuration is the same as that in FIG. 1.

第2図に第1図の要部抜粋図を示す。同図において電池
(B)の最初の急速充電時(時間T + )はマイコン
(Ice)の出力端子(P、)が「H」レベルで第1、
第3トランジスタ(Ql) (C3)が導通し、第3ト
ランジスタ(ql)を通る大電流(jc+)と抵抗(R
6)及びダイオード(D>を通る小電流(jC2)の和
の急速充電電流j Q (−jc++jCz)が電池(
B)に流れる。満充電時の電池電圧は抵抗(R7)(R
8)の分圧点を介して集積回路(IC2)に取り込まれ
、マイコンCICI)はこれによって第1.3トランジ
スタ(qi) (lhiを共に非導通にして前記小電流
fjc2)のみの補充電電流j T (−jC2)を電
池に供給する。
Figure 2 shows an excerpt of the main part of Figure 1. In the figure, during the first rapid charging of the battery (B) (time T + ), the output terminal (P, ) of the microcomputer (Ice) is at the "H" level and the first,
The third transistor (Ql) (C3) conducts, and the large current (jc+) passing through the third transistor (ql) and the resistance (R
6) and a small current (jC2) passing through the diode (D>), the fast charging current j Q (-jc++jCz)
It flows to B). The battery voltage when fully charged is determined by the resistance (R7) (R
8) is taken into the integrated circuit (IC2) through the voltage dividing point, and the microcomputer CICI) thereby makes the 1.3 transistor (qi) (lhi both non-conductive and supplies the supplementary charging current of only the small current fjc2). j T (-jC2) is supplied to the battery.

時刻t、でスイッチ(S)を閉成して上記の過程で満充
電になった電池を放電する。即ちマイコン(I+C+)
の出力端子(R2)の出力がrH」となって第2.4ト
ランジスタ(C21(04)か導通する。
At time t, the switch (S) is closed to discharge the fully charged battery in the above process. That is, microcomputer (I+C+)
The output of the output terminal (R2) becomes rH, and the 2.4th transistor (C21 (04)) becomes conductive.

よって電池(B)の放電電流は第4トランジスタ(C4
)のベース電流(j B)、抵抗(R9)を通る電流(
jR)との和からダイオード(D>を通る電流(jC2
)を引いたものとなる。抵抗(R1゜)及び(R++)
は高抵抗であり、電圧VD2のみその分圧点に生じるた
けで流れる電流は無視できるほど小さい。これは充電時
において抵抗(R7)(R8)を流れる電流の場合も同
じでその分圧点に電圧VD、のみ生じる。そしてダイオ
ード<D>を流れる電流(jCz)と第4トランジスタ
(C4)のベース電流(j[l)とは殆ど同じと考えて
良いから前記放電電流は略jRの大きさに等しい。従っ
て時間T 2 (t +〜t2の間)の間電池(B)は
jRの電流で放電し、これは電池(B)の端子電圧が1
セル当たり1.○Vになるまで続けられることになる。
Therefore, the discharge current of the battery (B) is increased by the fourth transistor (C4
) base current (j B), current passing through the resistor (R9) (
The current (jC2) passing through the diode (D>
) is subtracted. Resistance (R1°) and (R++)
has a high resistance, and since only voltage VD2 is generated at the voltage dividing point, the current that flows is so small that it can be ignored. This is the same in the case of the current flowing through the resistors (R7) and (R8) during charging, and only the voltage VD is generated at the voltage dividing point. Since the current (jCz) flowing through the diode <D> and the base current (j[l) of the fourth transistor (C4) can be considered to be almost the same, the discharge current is approximately equal to the magnitude of jR. Therefore, during time T 2 (between t + and t2) the battery (B) is discharged with a current of jR, which means that the terminal voltage of the battery (B) is 1
1 per cell. ○It will continue until it reaches V.

前記マイコン(lc+)は抵抗(R+o)in++)の
分圧点電圧VD2と放電時間(tz  t+)より放電
容量を計算しその値が60%(公称容量に対して)以上
なら電池(B)はメモリー効果が生じていないものと判
断し、再度満充電になるまで(時刻t3)電池(B)を
充電する。
The microcomputer (lc+) calculates the discharge capacity from the voltage dividing point VD2 of the resistor (R+o)in++) and the discharge time (tz t+), and if the value is 60% or more (relative to the nominal capacity), the battery (B) is It is determined that no memory effect has occurred, and the battery (B) is charged again until it is fully charged (time t3).

もし60%未満なら再度満充電にした後、もう−度先程
と同様に放電させてメモリー効果を除去した後再々充電
を行って最終的に電池(B)を満充電の状態とする。
If it is less than 60%, the battery is fully charged again, then discharged again in the same manner as before to remove the memory effect, and then charged again to finally bring the battery (B) to a fully charged state.

(ト) 発明の効果 本発明は以上の説明の如く、マイクロコンピュータの一
出力端子にベースを接続され電池の充電時に導通ずる第
1トランジスタと、前記マイクロコンピュータの他の出
力端子にベースを接続され電池の放電時に導通ずる第2
トランジスタと、前記第1トランジスタの主電流路にベ
ースを接続され該第1トランジスタの導通によって導通
ずる第3トランジスタと、該第3トランジスタの主電流
路に直列接続される蓄電池と、前記第31−ランシスタ
のコレクタ〜エミンタ間に抵抗を介して接続される逆流
防雨用ダイオードと、ベースを前記第21〜ランジスタ
に接続され該第2トランジスタの導通時に導通ずる第4
1−ランジスタとより成り、蓄電池の充電と放電とを切
り換えることのできる充放電装置を提供てきてメモリー
効果が生じた電池からメモリー効果を除去することがで
き、満充電時の電池の使用時間を均一化することがてき
るどともに、トランジスタで絹んた充放電切換回路は、
プリンI・基板が小型化できるので充電装置自身を小型
化できるとともに、製造コスI・をも低減すること力1
できる効果がある。
(g) Effects of the Invention As described above, the present invention includes a first transistor whose base is connected to one output terminal of the microcomputer and is turned on when charging a battery, and a first transistor whose base is connected to the other output terminal of the microcomputer. The second conductor conducts when the battery is discharged.
a third transistor whose base is connected to the main current path of the first transistor and becomes conductive when the first transistor is conductive; a storage battery connected in series to the main current path of the third transistor; a reverse rain-proofing diode connected between the collector and emitter of the transistor through a resistor; and a fourth transistor whose base is connected to the twenty-first transistor to conductive when the second transistor is conductive.
1- We have provided a charging/discharging device consisting of a transistor that can switch between charging and discharging a storage battery, which can remove the memory effect from a battery where it has occurred, and reduce the usage time of the battery when fully charged. In addition to being able to achieve uniformity, the charge/discharge switching circuit using transistors is
Since the printed circuit board can be made smaller, the charging device itself can be made smaller, and manufacturing costs can also be reduced.
There is an effect that can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明げ蓄電池の充放電装置を示す回路図、第
2図は電流の流れを示す第1図の部分回路図、第3図は
蓄電池の充放電時の端子電圧を示す時間特性図、第4図
はメモリー効果の有無による放電特性の違いを示す図、
第5図は第1図に相当する従来の回路図である。 +IC++・・マイクロコンピュータ、(Ql)・・第
11・ ランジスタ、(B)・・電池、(Q2)・・第
2トランジスタ、(q、)・第3トランジスタ、(R6
)・・・抵抗、(D>・・ダイオード、(Q4)・・・
第47−ランシスタウ
Fig. 1 is a circuit diagram showing a charging/discharging device for a storage battery according to the present invention, Fig. 2 is a partial circuit diagram of Fig. 1 showing the current flow, and Fig. 3 is a time characteristic showing the terminal voltage during charging and discharging of the storage battery. Figure 4 is a diagram showing the difference in discharge characteristics depending on the presence or absence of the memory effect.
FIG. 5 is a conventional circuit diagram corresponding to FIG. 1. +IC++...Microcomputer, (Ql)...Eleventh transistor, (B)...Battery, (Q2)...Second transistor, (q,)...Third transistor, (R6
)...Resistance, (D>...Diode, (Q4)...
No. 47-Ransistau

Claims (1)

【特許請求の範囲】[Claims] (1)マイクロコンピュータのー出力端子にベースを接
続され蓄電池の充電時に導通する第1トランジスタと、
前記マイクロコンピュータの他の出力端子にベースを接
続され電池の放電時に導通する第2トランジスタと、前
記第1トランジスタの主電流路にベースを接続され該第
1トランジスタの導通によって導通する第3トランジス
タと、該第3トランジスタの主電流路に直列接続される
前記蓄電池と、前記第3トランジスタのコレクタ〜エミ
ッタ間に抵抗を介して接続される逆流防止用ダイオード
と、ベースを前記第2トランジスタに接続され該第2ト
ランジスタの導通時に導通する第4トランジスタとより
成る蓄電池の充放電切換装置。
(1) a first transistor whose base is connected to the output terminal of the microcomputer and which becomes conductive when charging the storage battery;
a second transistor whose base is connected to the other output terminal of the microcomputer and conducts when the battery is discharged; and a third transistor whose base is connected to the main current path of the first transistor and which becomes conductive when the first transistor is conductive. , the storage battery connected in series to the main current path of the third transistor, a backflow prevention diode connected between the collector and emitter of the third transistor via a resistor, and a base connected to the second transistor. A storage battery charging/discharging switching device comprising a fourth transistor that becomes conductive when the second transistor is conductive.
JP32109388A 1988-12-20 1988-12-20 Charge/discharge switching device for battery Pending JPH02168820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32109388A JPH02168820A (en) 1988-12-20 1988-12-20 Charge/discharge switching device for battery

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32109388A JPH02168820A (en) 1988-12-20 1988-12-20 Charge/discharge switching device for battery

Publications (1)

Publication Number Publication Date
JPH02168820A true JPH02168820A (en) 1990-06-28

Family

ID=18128737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32109388A Pending JPH02168820A (en) 1988-12-20 1988-12-20 Charge/discharge switching device for battery

Country Status (1)

Country Link
JP (1) JPH02168820A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498239B1 (en) * 2002-11-18 2005-07-01 주식회사 다내테크 A APPARATUS FOR RAPIDLY CHARGING THE NiCd/NiMH BATTERYS SERIALLY AND SIMULTANEOUSLY

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61293123A (en) * 1985-06-18 1986-12-23 松下電器産業株式会社 Battery charge-discharge switching circuit
JPS62193516A (en) * 1986-02-20 1987-08-25 キヤノン株式会社 Electronic equipment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61293123A (en) * 1985-06-18 1986-12-23 松下電器産業株式会社 Battery charge-discharge switching circuit
JPS62193516A (en) * 1986-02-20 1987-08-25 キヤノン株式会社 Electronic equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498239B1 (en) * 2002-11-18 2005-07-01 주식회사 다내테크 A APPARATUS FOR RAPIDLY CHARGING THE NiCd/NiMH BATTERYS SERIALLY AND SIMULTANEOUSLY

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