JPH02168494A - Semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To isolate a word line from noise invaded to a ground line to bring a level of each word line to a prescribed level of an opposite sign and to prevent a change in the charge stored in a memory cell by providing a word level control circuit bringing a level of a word line in inactive state and in selecting state into a level of an opposite sign to that of the level in the selection state. CONSTITUTION:Plural memory cells 31 arranged as a matrix are provided to a memory cell array 3 of a semiconductor memory, word lines WLL1... and digit lines DLL1... are connected to each memory cell 31 and a decoder circuit 1 generates a word line selection signal to select a prescribed word line. Moreover, when a word line selection circuit 2 is in the active state, a prescribed word line of the plural word lines is brought into a selection level according to a word line selection signal and the word line is brought into the selection state. Then a word line level control circuit 4 brings the level of each word line when the circuit 2 is inactive and of each word line in the non-selective state when the circuit 2 is active into a prescribed level of an opposite sign to that of the selection level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor memory circuit, and particularly to a dynamic type semiconductor memory circuit.

[Conventional technology]

Conventionally, this type of semiconductor memory circuit, as shown in FIG. A plurality of word lines (WL, -1-) and digit lines (DLs,
---), and a decoder that generates a word line selection signal (Φ1.Φ1t---) for selecting a predetermined one of the plurality of word lines (WL+, ---). When activated by circuit 1 and word line activation signal Φ2, word line selection signal Φ1. The configuration includes two word line selection circuits that set the potential ΦW of a predetermined word line WLl to a selection level in accordance with Φl to bring this word line WLl into a selected state.

Next, the operation of this semiconductor memory circuit will be explained.

The two word line selection circuits include transistors Q connected in series between the input terminal of the word line activation signal Φ2 and the ground line, and inputting the word line selection signals Φl and Φ1 to their gates, respectively.
1 and Q2.

When the word line activation signal Φ2 is at a high level and the two word line selection circuits are in an activated state, a high level word line selection signal Φ1 and a low level word line selection signal Φ1 are input from the decoder circuit l. , transistor Qs is on, transistor Q is on.

is turned off, the potential ΦW of the word line WLt is set to a high level, and the word line WL is placed in a selected state. The star Q1 is turned off, and the transistor Q2 is turned on, setting the potential ΦW of the word line WL1 to the potential of the ground line, thereby rendering the word line WL in a non-selected state.

Note that when the word line activation signal Φ2 is in an inactive state at a low level, the word line WL1 is at the potential of the ground line.

[Problem to be solved by the invention]

In the conventional semiconductor memory circuit described above, the potential ΦW of the word line WLl in the non-selected state and the non-activated state is the potential of the ground line, so noise is mixed into the ground line, and the level of this noise increases. When the threshold voltage of the transistor Q3 of the memory cell 31 is exceeded, the charge of the capacitor CI leaks to the digit line DL, and even if the noise level is lower than the threshold voltage of the transistor Q3, a subthreshold current flows. The charge on capacitor C1 is day r)
In addition, when the word line selection signal Φl goes low level and the word line selection signal Φl goes high level, the purpose of the transistor light is to put it in a non-selected state, an inactivated state, and eliminate the noise that mixes into the ground line. 9. An object of the present invention is to provide a semiconductor memory circuit that can prevent the amount of charge stored in a memory cell from changing.

[Means to solve the problem]

The semiconductor memory circuit of the present invention includes a memory cell array including a plurality of memory cells arranged in a matrix, a plurality of word lines and digit lines connected to these memory cells, and a decoder circuit that generates a word line selection signal for selecting a word line; and a decoder circuit that, when in an activated state, sets the potential of a predetermined word line among the plurality of word lines to a selection level according to the word line selection signal. A word line selection circuit that selects a word line by a lever, each of the word lines when this word line selection circuit is in an inactive state, and a non-selected state when this word line selection circuit is in an activated state. and a word line potential control circuit that sets the potential of each word line to a predetermined potential having a sign opposite to the selection level.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The difference between this embodiment and the conventional semiconductor memory circuit shown in FIG. 2 is that the selected state potential of the word line (WL, . A word line potential control circuit 4 is provided which outputs a signal with a predetermined potential of the opposite sign (minus in this embodiment), and conventionally, one end of the word line selection circuit 2 connected to the ground line is controlled by the word line potential control circuit 4. It is connected to the output terminal of the circuit 4, and each word line (WLl.

-m-) and the potential (ΦW) of each unselected word line (WLs, ---) when the word line selection circuit 2 is in the activated state, the selection of the word line (WLl, ---) The point is that a predetermined potential with the opposite sign (minus) to the state potential (plus potential) is set.

The word line potential control circuit 4 includes an oscillation circuit 41, a capacitor C2, and transistors Q4 to Q6. It oscillates between the threshold voltage of Qs T and -(power supply voltage Vcc-VT).

Transistor Q4 functions as a diode and makes the potential of the output signal of word line potential '+tIIJ control circuit 4 negative potential.

When the word line WL is in a non-selected state, the word selection signal Φi is at a high level and the transistor Q2 is in a conductive state, so the potential ΦW of the word line WL becomes a negative potential, and noise is mixed into the ground line. However, since it is isolated from this noise and has a negative potential, memory cell 3
There is no change in the amount of charge stored in 1.

Further, when the word line selection circuit 2 is in an inactive state, the word line activation signal Φ2 is at a low level, and one end of the word line selection circuit 2 is connected to the word line potential control circuit 4.
Since the word line WL has a negative potential,
Since the potential ΦW is also a negative potential, the amount of charge stored in the memory cell 31 will not change due to noise.

〔Effect of the invention〕

As explained above, the present invention provides a word line potential control circuit that sets the potential of a word line in an inactive state and a non-selected state to a potential with a sign opposite to the potential in a selected state. With this structure, the word line is separated from the noise mixed in the ground line and the potential is of the opposite sign, so that it is possible to prevent the amount of charge stored in the memory cell from changing due to noise. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional semiconductor memory circuit. l...Decoder circuit, 2,2A...°...°word line selection circuit, 3゛°゛・°゛memory cell array 4°
°°°・°Word line potential control circuit, 31... Memory cell, 41... Excavation circuit, Ql, C,...
・・・Capacitor, DL, ・・・Digital, G line, Q1 to Q6 ・・・Transistor, WL, ・・・
...word line. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] A memory cell array comprising a plurality of memory cells arranged in a matrix, a plurality of word lines and digit lines connected to these memory cells, and a memory cell array for selecting a predetermined word line from the plurality of word lines. a decoder circuit that generates a word line selection signal; and a decoder circuit that, when in an activated state, sets the potential of a predetermined word line among the plurality of word lines to a selection level in accordance with the word line selection signal to place this word line in a selected state. a word line selection circuit to select the potential of each word line when this word line selection circuit is in an inactive state, and each word line in an unselected state when this word line selection circuit is in an activated state; 1. A semiconductor memory circuit comprising: a word line potential control circuit that sets a predetermined potential to a predetermined potential with a sign opposite to the level.