JPH02166819A - Method and circuit for processing digital signal - Google Patents

Abstract

PURPOSE:To easily perform processing such as mixing and crossfade, etc., by using one multiplier by storing level information and fade information after multiplying them respectively, and adding cumulatively the stored and held multiplied results. CONSTITUTION:The circuit can process the mixing and the cross-fade. In the case of cross-fade operation, a up-down counter 15 set so as to start by control from a fade controller 16 performs both up-operation to give a 1ch source fade signal SF1 and down-operation to give a 1ch tape fade signal TF1 independently at an in-point. The outputs of the counter 15 are impressed to the Y-input of the multiplier 10, and products with the level information SL1, TL1 are calculated respectively, and the results are stored in a Co-FF 13. At the point of time when data SD1, TD1 are inputted, the multiplication and the cumulative addition of stored coefficient data and sound data are executed. Then, finally, SL1*SF1*SD1+TL1* TF1*TD1 and cross-fade result are outputted from an output register 17.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal processing method and circuit for a mixing console, recorder, etc. that performs multi-channel digital audio processing.

2. Description of the Related Art In recent years, digital audio processing that processes audio in the form of digital signals has become widespread, and digitization of mixing consoles, recorders, etc. is also rapidly becoming widespread. One of the issues in this case is that in order to realize LSI through digitalization, it is necessary to reduce the gate scale as much as possible, and to have a circuit configuration that is easy to implement, as well as the need for multi-function, high-performance, etc. Points that constantly require improvement are raised. for example,
In the case of a recorder, in order to improve the editing function, it is possible to perform cross-fade processing on the sounds before and after the editing point, and to freely change the audio channels in order to make the connection between the sounds at the editing point natural. It is a function that allows you to record the same channel or another channel again after mixing.

In particular, the former cross-fade function gradually decreases or increases the audio level in units of audio samples, and is a function that can only be accurately realized when signal processing is digitized.

Problems to be Solved by the Invention Conventionally, when implementing these functions, a mixing circuit with level control and a cross-fade circuit with a built-in multiplier have been used independently.

Furthermore, each channel has an independent configuration, and as many multipliers as the number of channels are required.

However, when attempting to implement the above configuration into an LSI, including both a mixing circuit and a cross-fade circuit increases the circuit scale, and the technical aspects of the LSI configuration
Alternatively, there was a cost problem.

The present invention has been made in view of these conventional problems, and aims to easily implement processing such as mixing and cross-fading for each channel by time-division processing using a single multiplier. Consider it a technical issue.

Means for Solving the Problems In order to solve the above-mentioned problem, the invention of claim 1 of the present application, for digitized multi-channel audio signals, sets the sampling period of the audio data according to the number of channels. dividing into time-division time slots; inserting the audio data into a predetermined time slot according to the selection result; inserting level information of the audio into a predetermined time slot; and gradual steps in cross-fade processing. inserting increasing or decreasing fade information into a predetermined time slot; multiplying the level information by the fade information; storing the multiplication result once and multiplying it by the audio data again; This is a digital signal processing method consisting of a step of cumulatively adding the results of multiplication with audio data.

Further, the invention according to claim 2 of the present application includes a dividing means for dividing the sampling period of the audio data into time-division time slots corresponding to the number of channels, and dividing means for dividing the sampling period of the audio data into time-division time slots corresponding to the number of channels, for a digitalized audio signal of a plurality of channels; a first insertion means for inserting audio data into a predetermined time slot; a second insertion means for inserting the audio level information into the time-divided predetermined time slots; The third step inserts fade information indicating a decreasing audio level into a predetermined time slot.
an insertion means for multiplying the audio data by the content of the storage means and the level information by the fade information, a storage means for temporarily storing the multiplication result, and a multiplication result held in the storage means. This is a digital signal processing circuit characterized in that it has an adding means for cumulatively adding.

According to the invention of claim 1 or 2 of the present application which develops such a feature, the audio data signals of multiple channels are divided into time-division time slots and inserted into the determined time slots, and the level information is set in the same manner. At the same time, during cross-fading, fade information indicating the audio level is inserted into a predetermined time slot. By making the time slots of the time-divided data different in this way, a predetermined channel can be transferred to any other channel or a mixing fade process can be performed. Then, the level information and fade information inserted into these time lofts are multiplied and stored once, and the audio data is multiplied again, and the multiplication results with the audio data are cumulatively added. In this way, one multiplier can be used in time-division processing to achieve addition level control during mixing and fade level control during crossfading.

Embodiments Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a processing circuit that implements a digital signal processing method according to an embodiment of the present invention.

In FIG. 1, explanation will be given by taking as an example a recording and reproducing apparatus that processes four-channel audio signals. In the figure, 1 is a digital audio input terminal, which has four channels of input from CHI to CH4 in order.

2 is a tape playback audio input terminal having input terminals for four channels. These input terminals are each given to the human power L/'/star 3 al 3 b. Input register 3a
l3b has registers and multiplexers for four channels that hold signals given from each channel at predetermined timing, and time division means that divides the audio data sampling period into time division time slots according to the number of channels. It consists of Input register aa, 3b
A time division signal given from the matrix switch 5 is given to the matrix switch 5.

A select controller 6 for selecting the switching is connected to the matrix switch 5. The selection controller θ is given a selection signal indicating that the channel is selected by a control means 4 comprising an input means such as a keyboard and a microcomputer. The matrix switch 5 can be constructed by arranging a large number of changeover switches, but since this would be complicated, it is easier to replace them by using a RAM and converting addresses for writing and reading.

The output of matrix switch 5 is given to multiplexer 7. Further, the output of the level information input terminal is given to the level register 9. The level register 9 consists of eight registers, and as will be described later, source level signals SL1 to SL4 of channels 1 to 4. Tape level signals TL1 to TL4 of channels 1 to 4 are given to each level register in a time-divided manner. is read out at a predetermined timing and applied to the multiplexer 7. The multiplexer 7 divides these outputs and applies them to the X input of the multiplier 10. The output of multiplier 10 is given to adder 11. The adder 11 constitutes an adding means that performs cumulative addition by adding the output of a P-FF (product flip-flop), which is a storage means for temporarily holding the addition output, and the multiplication output. The output is given to a Co-FF (coefficient flip-flop) 13. Control means 4 and matrix switch 5. The select controller 6 constitutes a first insertion means that inserts audio data according to the selection result into a predetermined time slot, and the control means 4 and the level register 9 insert audio level information into time-divided predetermined time slots. It constitutes a second insertion means for inserting into.

On the other hand, the fate controller 16 activates the up/down counter 15 of any channel based on the control signal from the control means 4. The up/down counter 15 includes eight independent up/down counters that provide source fade signals SF1 to SF4 for channels 1 to 4, tape fade signals TF1 to TF4 for channels 1 to 4, and a clock generator that provides a common clock to these counters. Each counter is controlled by a fade controller 16 and its coefficient output is given to a multiplexer 14.

Here, the control means 4, multiplexer 14, up/down counter 15, and fade controller 6 constitute a third insertion means for inserting fade information that gradually increases or decreases in a predetermined time slot in cross-fade processing. Multiplexer 14 outputs the fade signal and C
o-FF13 coefficient signal is selected and applied to the Y input terminal of the multiplier 10. Further, the output of the P-FF 12 is given to an output register 17. The output register 17 consists of a demultiplexer and a 4-channel register that temporarily holds the output of the demultiplexer, and divides each channel to output terminal 1.
It is output from 8. and multiplier 10, Go-
The FF 13 and the multiplexer 14 constitute a multiplication means that multiplies the audio data, the level information, and the fade information without a storage means.

FIG. 2 is an explanatory diagram of the contents of signal names used in explanation of timing diagrams, etc., and the * mark indicates any channel from 1 to 4.

Figure 3 is a waveform diagram explaining how one audio sample slot is time-divisionally used. When the sampling frequency for digitization is selected as fs, and when the period 1/fs is used for 4 channels, 32 Configure equal time slots.

Furthermore, if the 8 slots are grouped into recording channel units after channel swapping, and the first 4 slots of the channel slots are the X input of the multiplier 10 shown in FIG. In this case, it is assigned to fade coefficient information and used as a coefficient slot. The latter four slots are allocated as data slots for each channel.

FIG. 4 is a timing waveform diagram showing the mixing and switching operations of audio channels, and FIG. 5 is a timing waveform diagram showing the cross-fade operation.

Next, let's move on to an explanation of the operation. First, the mixing and channel switching operations will be explained according to the waveform diagram of FIG. 4. Whether the 4-channel audio signal input from audio input terminal 1 is serial input or parallel input,
It is input to the input register 3a. Further, a tape playback signal inputted from the tape playback audio input terminal 2 is similarly inputted to the input register 3b, held for a while, and then inputted to the matrix switch 5 at a predetermined timing. The channel switching performed by the control unit 4 and the select controller 6 is to allocate an arbitrary audio channel input to an arbitrary recording audio channel, and changes from CHI to CH2,
Any selection is possible, including CHI→CH4, as long as the destinations do not overlap.

Therefore, the #N channel slot shown in FIG. 2 is set as the destination channel number to be recorded, and the input channel audio data to be replaced is inserted into the data slot of this channel number using the matrix switch 5 according to the command from the select controller 6. If you want to perform further mixing, as shown in FIG. 4(b), use SDl, Sn2. Sn
4 is placed in the data area of the #N channel slot, the mixing outputs of CHI, CH3, and CH4 are finally recorded in the #N channel.

On the other hand, from the terminal 8, level information SL1 to SL4. TL1 to TL4 are input to the level register 9 in the form of digital data. When changing channels, this data is input to a microcomputer, etc. in a changed order, stored in the level register 9, and read out at a predetermined timing, as shown in FIG. 4(b).
L.I.

SL3. It is inserted into a predetermined coefficient slot such as SL4. M
In UX7, the timing of coefficient slot and data slot is switched, and multiplier 1 is switched as shown in FIG. 4(b).
A level coefficient and audio data are applied to the 0 X input.

On the other hand, when cross-fade processing is not performed in the edit mode, the up-down counter 15 is stopped under the control of the fade controller 16, and its output is output as a multiplication coefficient, as shown in the coefficient slot of FIG. 4(C). 1'' and is applied to the Y input of the multiplier 10 via the MUX 14. Therefore, the source level information S in FIG. 4(b)
LI to SL4 appear as they are at the P output of the multiplier 10, as shown in FIG. 4(C). Further, since the addition gate signal ADD shown in FIG. 4(f) is not applied to the adder 11, the addition gate signal ADD shown in FIG. The signal is delayed at the timing shown by the broken line between FIGS. 2(e) and 3(c), and is again applied to the Y input of the multiplier 10 via the MUX 14.

Therefore, when audio data SD1 is input, SDI and S
Multiplication of LI is performed and the result is passed through adder 11 to P
Since the next data slot of CH2 is empty and the addition gate is active, SL1*SD1 is stored in P-FF 12 again. When the multiplication of Sn2 and SL3 is executed and the result is input to the adder 11 from the P output of the multiplier 10, P-F
Addition is performed with SL1*SD1 stored in FI2.

After that, multiplication and cumulative addition are similarly performed for SD4, and the final result is SL1*SD1+SL3*SD3+SL
4*SD4 is picked up by the latch pulse of the output register 17 (shown in FIG. 4(g)), outputted from a predetermined channel output terminal 18, and sent to the recording circuit.

Therefore, if you set the level information externally and insert the input channel data into the channel slot to be recorded,
Mixing operations can be performed in any way.

The cross-fade operation during editing will be explained based on the timing waveform diagram shown in FIG. The operations other than the operations of the fade controller 16 and up/down counter 15 are basically the same as in the previous example, and the explanation will be simplified. That is,
As shown in FIG. 5(b), cross-fade in the case of channel 1 source and tape data will be described.

Cross-fade processing plays back the already recorded tape information from the point where the in-point edit point is set back in time, and gradually changes the fade coefficient from "1".
This process is a cross between a fade-out process that reduces the fade coefficient to 0'' and a fade-in process that gradually increases the fade coefficient from 0 to 1 for the source information to be recorded.
At the editing out point, perform the opposite operation.

Therefore, the up/down counter 15 (8 counters are required to independently process crossfades of 4 channels), which is set to start under the control of the fade controller 16, provides an up/down counter 15 that provides the lch source fade signal SF1 at the in point. The operation and the down operation for providing the lch tape fade signal TFI are performed independently. The output of the up/down counter 15 is applied to the Y input of the multiplier 10 via the MUX 14, and each has a level tfNsL1°T.
The product is taken with LI and the result is passed through adder 11 to Co
- Stored in FF13. Data/SDI.

When TDl is input, multiplication and cumulative addition of the stored coefficient data and audio data are executed, and finally SL 1*SF 1*SD 1+TL1*TF1*
TD1 and the cross-fade result are output from the output register 17 to the terminal 18.

Although channel switching, mixing, and cross-fade operations have been described above, it is of course possible to perform both at the same time.

In addition, although the embodiments described so far have been described as examples of four channels, the present invention is not limited to this. For example, if the sampling frequency is 48kHz and it is divided into 32 slots, one time slot is 651n5ec.
For multipliers that normally have a speed of several tens of n5ec, there is no problem in terms of speed, the number of channels can be easily expanded, and the versatility is high.

Effects of the Invention In the present invention, by time-sharing processing using one multiplier,
Addition level control during mixing and fade level control during crossfading can be realized. Therefore, this entire digital signal processing circuit is implemented as an LSI.
In this case, the gate scale can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital signal processing circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing signal names used in an embodiment of the present invention, and FIG. 3 is a diagram showing time slots according to an embodiment of the present invention. 4 is a timing waveform diagram according to an embodiment of the present invention, and FIG. 5 is also a timing waveform diagram according to an embodiment of the present invention. 3 al 3 b...input register, 4...
...control means, 5...matrix switch,
6...Matrix controller, 9...
Level register, 10... Multiplier, 11...
・Adder, 12...P-FF, 13...
...Co FF% 15...up/down counter, 16...fade controller, 17
...Output register. Name of agent: Patent attorney Shigetaka Awano and 1 other person - Eng.
p-cho + 3 SL 5D3 + 5L + MeSD 4 faction diagram

Claims (2)

[Claims] (1) A step of dividing the sampling period of the audio data into time-division time slots according to the number of channels for the digitized audio signal of multiple channels, and dividing the audio data into the determined time slots according to the selection result. inserting audio level information of each channel into the time-divided predetermined time slots; and inserting fade information indicating a gradually increasing or decreasing audio level in the cross-fade process into the time slots. inserting the level information into the divided predetermined time slot; multiplying the level information by the fade information; storing the multiplication result once and multiplying it by the audio data again; A digital signal processing method characterized by comprising a step of cumulatively adding multiplication results. (2) Time division means for dividing the sampling period of the audio data into time division time slots according to the number of channels for the digitized audio signal of multiple channels; a first insertion means for inserting the audio level information into the time slot; a second insertion means for inserting the audio level information into the time-divided predetermined time slots; a third insertion means for inserting fade information indicated into a predetermined time slot, a multiplication means for multiplying the audio data by the content of the storage means, the level information and the fade information, and temporarily storing the multiplication results. A digital signal processing circuit comprising a storage means and an addition means for cumulatively adding the multiplication results held in the storage means.