JPH0216679U - - Google Patents
Info
- Publication number
- JPH0216679U JPH0216679U JP9521488U JP9521488U JPH0216679U JP H0216679 U JPH0216679 U JP H0216679U JP 9521488 U JP9521488 U JP 9521488U JP 9521488 U JP9521488 U JP 9521488U JP H0216679 U JPH0216679 U JP H0216679U
- Authority
- JP
- Japan
- Prior art keywords
- screen
- image
- screen memory
- time
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
第1図は、本考案に係る時間差画面メモリ付テ
レビ受像機の一実施例を示すブロツク図である。
1……画像処理部、2……画面メモリ部、3…
…画像遅延回路、4……メモリ動作遅延回路、5
……メモリ制御部、6……画像切換部、7……画
像表示部。
FIG. 1 is a block diagram showing an embodiment of a television receiver with time difference screen memory according to the present invention. 1... Image processing section, 2... Screen memory section, 3...
...Image delay circuit, 4...Memory operation delay circuit, 5
. . . memory control section, 6 . . . image switching section, 7 . . . image display section.
Claims (1)
発生させる画像処理部と、 前記画像表示部と前記画像処理部との間に設置
された画像切換部と、 前記画像処理部と前記画像切換部との間に並列
に設置された複数の画面メモリ部と、 前記画面メモリ部に記憶命令を発するメモリ制
御部と、 前記複数の画面メモリ部のうちの所定数の画面
メモリ部に関連して設置され、該画面メモリ部に
記憶される画面を記憶命令が発つせられた時点よ
りも早い時点の画面とする画像遅延回路と、 前記複数の画面メモリ部のうちの所定数の画面
メモリ部に関連して設置され、該画面メモリ部に
記憶される画面を記憶命令が発つせられた時点よ
りも遅い時点の画面とするメモリ動作遅延回路と
、 を備えて構成されてなる時間差画面メモリ付テ
レビ受像機。[Claims for Utility Model Registration] An image display section that displays a television image; an image processing section that generates a television image signal to be displayed on the image display section; and between the image display section and the image processing section. an installed image switching unit; a plurality of screen memory units installed in parallel between the image processing unit and the image switching unit; a memory control unit that issues a storage command to the screen memory unit; an image delay circuit that is installed in association with a predetermined number of screen memory units among the screen memory units and makes the screen stored in the screen memory unit a screen at a time earlier than the time when the storage command is issued; A memory operation that is installed in association with a predetermined number of screen memory units among the plurality of screen memory units, and makes the screen stored in the screen memory unit a screen at a later time than the time when the storage command is issued. A television receiver with a time-difference screen memory, comprising a delay circuit and a time difference screen memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9521488U JPH0216679U (en) | 1988-07-19 | 1988-07-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9521488U JPH0216679U (en) | 1988-07-19 | 1988-07-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0216679U true JPH0216679U (en) | 1990-02-02 |
Family
ID=31319843
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9521488U Pending JPH0216679U (en) | 1988-07-19 | 1988-07-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0216679U (en) |
-
1988
- 1988-07-19 JP JP9521488U patent/JPH0216679U/ja active Pending
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