JPH0216582B2 - - Google Patents
Info
- Publication number
- JPH0216582B2 JPH0216582B2 JP58243410A JP24341083A JPH0216582B2 JP H0216582 B2 JPH0216582 B2 JP H0216582B2 JP 58243410 A JP58243410 A JP 58243410A JP 24341083 A JP24341083 A JP 24341083A JP H0216582 B2 JPH0216582 B2 JP H0216582B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- terminals
- wiring board
- integrated circuit
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 50
- 230000005540 biological transmission Effects 0.000 claims description 23
- 239000004020 conductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 11
- 230000005855 radiation Effects 0.000 description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は、半導体集積回路装置に係り、特に、
超高速半導体集積回路装置におけるパツケージの
端子と半導体チツプの端子との接続構造に関す。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular,
This invention relates to a connection structure between package terminals and semiconductor chip terminals in an ultrahigh-speed semiconductor integrated circuit device.
(b) 技術の背景
半導体集積回路装置は、情報処理機器において
主要構成要素として多用されているが、情報処理
能力の向上が望まれている状況にある現在、高集
積化と共に高速動作に対応出来るものの開発も進
められている。(b) Background of the technology Semiconductor integrated circuit devices are often used as main components in information processing equipment, and as there is a current demand for improved information processing capabilities, it is becoming more and more possible to handle high-speed operation along with higher integration. Development is also progressing.
キヤリアの移動度や飽和ドリフト速度がSi半導
体より大きいため高速動作に適したGaAs半導体
を使用することにより、10G bit／ｓ以上の速度
で動作可能な超高速半導体集積回路装置が実用化
されてきているが、100G bit／ｓ程度の動作速
度になると、半導体集積回路装置内の接続構造が
特性に影響をおよぼすので、高速動作に対応出来
る接続構造の開発が望まれている。 By using GaAs semiconductors, which are suitable for high-speed operation because their carrier mobility and saturation drift speed are higher than those of Si semiconductors, ultra-high-speed semiconductor integrated circuit devices that can operate at speeds of 10 Gbit/s or higher have been put into practical use. However, when the operating speed reaches approximately 100 Gbit/s, the connection structure within a semiconductor integrated circuit device affects its characteristics, so there is a desire to develop a connection structure that can support high-speed operation.
(c) 従来技術と問題点
第１図は従来の超高速半導体集積回路装置の一
実施例の構造を示す断面図で、１はパツケージ、
２は半導体チツプ、３はリード端子、４，５は端
子、６はワイヤ、７は蓋をそれぞれ示す。(c) Prior art and problems Figure 1 is a cross-sectional view showing the structure of an embodiment of a conventional ultra-high-speed semiconductor integrated circuit device.
2 is a semiconductor chip, 3 is a lead terminal, 4 and 5 are terminals, 6 is a wire, and 7 is a lid.
図示の超高速半導体集積回路装置は、本体が例
えばセラミツクでなるパツケージ１の内側に、例
えばGaAs基板に超高速で動作可能な集積回路を
形成した半導体チツプ２が図示のように搭載さ
れ、パツケージ１から外部に導出される複数のリ
ード端子３の個々にパツケージ１内で接続され
て、半導体チツプ２と接続するためパツケージ１
の内側に導出された複数の端子４と、前記集積回
路を外部と接続するため半導体チツプ２の表面上
に形成された複数の端子５とが、例えば金線でな
るワイヤ６を用いてワイヤボンデイングにより個
別に接続され、蓋７が被せられてなつている。な
お、半導体チツプ２の裏面は、パツケージ１の半
導体チツプ２搭載面に設けられた導体を介してリ
ード端子３の中の接地端子に接続されている。 In the illustrated ultra-high-speed semiconductor integrated circuit device, a semiconductor chip 2 in which an integrated circuit capable of operating at ultra-high speed is formed on a GaAs substrate, for example, is mounted inside a package 1 whose main body is made of, for example, ceramic, as shown in the figure. A plurality of lead terminals 3 led out from the package 1 are individually connected to each other in the package 1, and the package 1 is connected to the semiconductor chip 2.
A plurality of terminals 4 led out inside the semiconductor chip 2 and a plurality of terminals 5 formed on the surface of the semiconductor chip 2 for connecting the integrated circuit to the outside are wire bonded using wires 6 made of, for example, gold wire. They are individually connected by means and covered with a lid 7. The back surface of the semiconductor chip 2 is connected to a ground terminal in the lead terminals 3 via a conductor provided on the surface of the package 1 on which the semiconductor chip 2 is mounted.
この構成でなる超高速半導体集積回路装置にお
いては、通常、半導体チツプ２は一辺の長さが数
mmの角形でワイヤ６の長さが１〜３mm程度である
が、動作速度が100G bit／ｓ（λ／４＝0.75mm）
程度になると該集積回路装置内の線路長が１mm程
度であつても信号の輻射や伝送減衰が問題になつ
て来る。 In an ultra-high-speed semiconductor integrated circuit device having this configuration, the semiconductor chip 2 usually has a length of several sides.
The length of the wire 6 is about 1 to 3 mm, but the operating speed is 100 Gbit/s (λ/4 = 0.75 mm).
When it reaches a certain level, signal radiation and transmission attenuation become a problem even if the line length within the integrated circuit device is about 1 mm.
この問題に対処するためには、設計において、
全ての、導体、半導体、絶縁体の材料、形状、寸
法、配置などを詳細に規定することが望ましい
が、ワイヤ６に関しては、接続の空間配置を規定
することが製造のプロセスからして極めて困難で
ある。 To address this issue, in the design,
It is desirable to specify in detail the materials, shapes, dimensions, arrangement, etc. of all conductors, semiconductors, and insulators, but for the wire 6, it is extremely difficult to specify the spatial arrangement of connections due to the manufacturing process. It is.
従つて、端子４と５とを接続するワイヤ６に起
因する信号の輻射や伝送減衰は、設計での対処が
困難であつて、動作速度の向上を阻害する欠点を
有する。 Therefore, signal radiation and transmission attenuation caused by the wire 6 connecting the terminals 4 and 5 are difficult to deal with in design, and have the drawback of hindering improvement in operating speed.
(d) 発明の目的
本発明の目的は上記従来の欠点に鑑み、パツケ
ージの端子と半導体チツプの端子との接続におい
て、該接続部に起因する信号の輻射や伝送減衰に
ついて設計で対処可能な接続構造を備えた超高速
半導体集積回路装置を提供するにある。(d) Object of the Invention In view of the above-mentioned conventional drawbacks, the object of the present invention is to provide a connection between a terminal of a package and a terminal of a semiconductor chip in which signal radiation and transmission attenuation caused by the connection can be addressed by design. An object of the present invention is to provide an ultra-high speed semiconductor integrated circuit device having a structure.
(e) 発明の構成
上記目的は、半導体チツプを搭載したパツケー
ジの該半導体チツプ周辺に設けられた端子と、該
半導体チツプの表面に設けられた端子とが、絶縁
性基板の面上に伝送路を形成し該半導体チツプの
表面側に配設された配線板によつて接続されてい
ることを特徴とする半導体集積回路装置によつて
達成される。(e) Structure of the Invention The above object is to form a transmission path between terminals provided around the semiconductor chip of a package on which the semiconductor chip is mounted, and terminals provided on the surface of the semiconductor chip, on the surface of an insulating substrate. This is achieved by a semiconductor integrated circuit device characterized in that it is formed with a semiconductor chip and is connected by a wiring board disposed on the front surface side of the semiconductor chip.
前記配線板を使用することにより、前記パツケ
ージの端子と前記半導体チツプの端子とを接続す
る前記伝送路は、材料、形状、寸法、配置などを
設計で詳細に規定することが可能になり、必要な
らば該伝送路をコプレナーガイドないしストリツ
プラインにしたり、また、回路素子を含むものに
することも可能で、該接続部に起因する信号の輻
射や伝送減衰について設計で対処可能になる。 By using the wiring board, the material, shape, dimensions, arrangement, etc. of the transmission path connecting the terminals of the package and the semiconductor chip can be specified in detail in the design, and the necessary In this case, the transmission path can be made into a coplanar guide or a stripline, or it can be made to include circuit elements, and it becomes possible to deal with signal radiation and transmission attenuation caused by the connection part in the design.
(f) 発明の実施例 以下本発明の実施例を図により説明する。(f) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.
第２図は本発明の構成による超高速半導体集積
回路装置の一実施例の構造を示す断面図、第３図
〜第７図はその配線板におけるそれぞれ異なつた
実施例の断面図ａと裏面視平面図ｂで、１１はパ
ツケージ、１２は半導体チツプ、１３はリード端
子、１４，１５は端子、１６は配線板、１７は
蓋、１８は絶縁基板、１８ａは合わせマーク、１
９は伝送路、１９ａは接続線、１９ｂ，１９ｃは
接地導体、１９ｄは抵抗素子、１９ｅは回路素
子、１９aa，１９ab，１９bb，１９cbは接続部
をそれぞれ示す。 FIG. 2 is a sectional view showing the structure of an embodiment of an ultra-high-speed semiconductor integrated circuit device according to the present invention, and FIGS. 3 to 7 are sectional views a and rear views of different embodiments of the wiring board. In the plan view b, 11 is a package, 12 is a semiconductor chip, 13 is a lead terminal, 14 and 15 are terminals, 16 is a wiring board, 17 is a lid, 18 is an insulating substrate, 18a is an alignment mark, 1
Reference numeral 9 indicates a transmission path, 19a a connection line, 19b and 19c ground conductors, 19d a resistance element, 19e a circuit element, and 19aa, 19ab, 19bb, and 19cb connection parts, respectively.
第２図図示の超高速半導体集積回路装置は、基
本的には第１図図示のパツケージ１と同じで細部
寸法が本集積回路装置の組立に合わせてあるパツ
ケージ１１の内側に、第１図図示の半導体チツプ
２に後述する合わせマークを付した半導体チツプ
１２が図示のように搭載され、第１図図示と同様
にパツケージ１１の内側に導出された複数の端子
１４と、半導体チツプ１２の集積回路を外部と接
続するため半導体チツプ１２の表面上に形成され
た複数の端子１５とが、半導体チツプ１２の表面
側に被せた配線板１６によつて接続され、蓋１７
が被せられてなつている。なお、半導体チツプ１
２の裏面は、パツケージ１１の半導体チツプ１２
搭載面に設けられた導体を介してリード端子１３
の中の接地端子に接続されている。 The ultra-high-speed semiconductor integrated circuit device shown in FIG. 2 is equipped with a package 11 that is basically the same as the package 1 shown in FIG. A semiconductor chip 12 with alignment marks to be described later is mounted on the semiconductor chip 2 as shown in the figure, and a plurality of terminals 14 led out inside the package 11 as shown in FIG. A plurality of terminals 15 formed on the surface of the semiconductor chip 12 for connection to the outside are connected by a wiring board 16 placed over the surface of the semiconductor chip 12, and a lid 17
It is covered with a rustic pattern. In addition, semiconductor chip 1
The back side of 2 is the semiconductor chip 12 of the package 11.
Lead terminal 13 via a conductor provided on the mounting surface
is connected to the ground terminal inside.
配線板１６は、例えば透明なサフアイア板でな
る絶縁基板１８に、その裏面で端子１４と１５と
を接続する伝送路１９が形成されてなつており、
第３図〜第７図に伝送路１９の構成を異にする配
線板１６の実施例を示すが、伝送路１９と端子１
４，１５とは例えば半田によつて接続する。ま
た、絶縁基板１８裏面の前述した半導体チツプ１
２の合わせマークに対応した位置に、例えば＋印
である該合わせマークと同様な合わせマーク１８
ａが付してあり、配線板１６を半導体チツプ１２
に被せて前記接続を行う際の位置合わせが出来る
ようになつている。 The wiring board 16 is made up of an insulating substrate 18 made of, for example, a transparent sapphire plate, and a transmission path 19 connecting terminals 14 and 15 formed on the back surface thereof.
3 to 7 show embodiments of the wiring board 16 with different configurations of the transmission line 19.
4 and 15 are connected, for example, by solder. In addition, the aforementioned semiconductor chip 1 on the back side of the insulating substrate 18
At the position corresponding to the alignment mark 2, an alignment mark 18 similar to the alignment mark, for example a + mark, is placed.
a is attached, and the wiring board 16 is connected to the semiconductor chip 12.
It is designed so that positioning can be performed when making the connection by placing it over the surface.
第３図図示の配線板１６における伝送路１９
は、絶縁基板１８の裏面に例えば金、銀、銅など
の金属導体で形成し端子１４と１５とを接続する
接続線１９ａのみで構成した例で、平坦な接続部
１９aaを端子１４に、突起状になつている接続
部１９abを端子１５に接続する。この構成の場
合、接続線１９ａの幅、接続部１９aa，１９ab
間の通路位置、接続部１９abの突起高さ（複数
の接続部１９ab相互間で同一にする必要がある
が）および絶縁基板１８の厚さなどを設計で規定
することが可能である。 Transmission line 19 in wiring board 16 shown in FIG.
is an example in which only a connecting wire 19a is formed on the back surface of an insulating substrate 18 using a metal conductor such as gold, silver, or copper and connects terminals 14 and 15. Connect the connecting portion 19ab shaped like the terminal 15 to the terminal 15. In this configuration, the width of the connection line 19a, the connection parts 19aa, 19ab
It is possible to specify the position of the passage between the two, the height of the protrusion of the connecting portions 19ab (which must be the same among the plurality of connecting portions 19ab), the thickness of the insulating substrate 18, etc. by design.
第４図図示の配線板１６における伝送路１９
は、第３図図示のような接続線１９ａに接続線１
９ａと同様な金属導体で同一面上（合わせマーク
１８ａ部を除く）に形成した接地導体１９ｂを加
えてコプレナーガイドを形成し、電磁界を閉じ込
めて信号の輻射による減衰の防止を可能にした例
で、接地導体１９ｂの接続部１９bbは接続部１
９abと同様な突起状にし、半導体チツプ１２の
底面からスルーホールを介して表面に導出させた
接地用の端子（端子１５の一部）に接続して、接
地導体１９ｂを接地する。この構成の場合、第３
図で説明した要因を含めてコプレナーガイドとし
ての設計が可能である。 Transmission line 19 in wiring board 16 shown in FIG.
Connect the connecting wire 1 to the connecting wire 19a as shown in FIG.
A ground conductor 19b made of the same metal conductor as 9a and formed on the same plane (excluding the alignment mark 18a) is added to form a coplanar guide, which confines the electromagnetic field and makes it possible to prevent attenuation due to signal radiation. In the example, the connection part 19bb of the ground conductor 19b is the connection part 1
The grounding conductor 19b is grounded by connecting it to a grounding terminal (a part of the terminal 15) formed into a protruding shape similar to 9ab and led out from the bottom of the semiconductor chip 12 to the surface through a through hole. In this configuration, the third
It is possible to design a coplanar guide including the factors explained in the figure.
第５図図示の配線板１６における伝送路１９
は、第４図図示の接地導体１９ｂを絶縁基板１８
の表面（合わせマーク１８ａ部を除く）に形成し
た接地導体１９ｃに替えて、コプレナーガイドと
同様に機能するストリツプラインを形成した例
で、接地導体１９ｃの接続部cbは絶縁基板１８
の表面から裏面に導出させて該裏面上では接続部
bbと同様にしている。 Transmission line 19 in wiring board 16 shown in FIG.
The ground conductor 19b shown in FIG. 4 is connected to the insulating substrate 18.
This is an example in which a stripline that functions similarly to a coplanar guide is formed in place of the ground conductor 19c formed on the surface (excluding the alignment mark 18a) of the insulating substrate 18.
The connection part is led out from the front surface to the back surface and the connection part is
I am doing the same as bb.
第６図図示の配線板１６における伝送路１９
は、第４図図示のようなコプレナーガイドの接続
線１９ａと接地導体１９ｂの間に膜状の抵抗素子
１９ｄを付加接続した例で、信号の反射波による
減衰を防ぐためのインピーダンスマツチが容易に
なつている。 Transmission line 19 in wiring board 16 shown in FIG.
4 is an example in which a film-like resistive element 19d is additionally connected between the connecting wire 19a of the coplanar guide and the ground conductor 19b as shown in FIG. 4, and impedance matching to prevent signal attenuation due to reflected waves is easy. It's getting old.
第７図図示の配線板１６における伝送路１９
は、第４図図示のようなコプレナーガイドの接続
線１９ａの中間などを絶縁基板１８の裏面から表
面に導出させ、例えば波形整形回路素子や増幅回
路素子などの回路素子を付加接続した例で、積極
的な性能向上が可能になつている。 Transmission line 19 in wiring board 16 shown in FIG.
This is an example in which the middle of the connecting wire 19a of the coplanar guide as shown in FIG. 4 is led out from the back side of the insulating substrate 18 to the front side, and circuit elements such as waveform shaping circuit elements and amplifier circuit elements are additionally connected. , it is now possible to actively improve performance.
これらの実施例から明らかなように、本発明に
よる配線板１６を導入することにより、端子１４
と１５との接続部に起因する信号の輻射や伝送減
衰について設計での対処が困難であつたワイヤ接
続から脱却して、該接続部に設計で規定可能な伝
送路１９を形成することが可能になり、然も、伝
送路１９の構成は上記の実施例に留まらず多くの
応用変形が可能である。そして、少なくとも前記
接続部に起因する信号の輻射や伝送減衰について
は、動作速度が100G bit／ｓ以上になつても問
題がないよう対処することが可能になる。 As is clear from these examples, by introducing the wiring board 16 according to the present invention, the terminals 14
It is possible to break away from the wire connection in which it was difficult to deal with signal radiation and transmission attenuation caused by the connection between the wire and the wire 15 in the design, and to form a transmission path 19 that can be specified in the design at the connection. However, the configuration of the transmission path 19 is not limited to the above-mentioned embodiment, and can be modified in many ways. Furthermore, it is possible to deal with at least signal radiation and transmission attenuation caused by the connection portion without causing any problems even when the operating speed exceeds 100 Gbit/s.
(g) 発明の効果
以上に説明したように、本発明による構成によ
れば、パツケージの端子と半導体チツプの端子と
の接続において、該接続部に起因する信号の輻射
や伝送減衰について設計で対処可能な接続構造を
備えた超高速半導体集積回路装置を提供すること
が出来て、超高速半導体集積回路装置の動作速度
向上を可能にさせる効果がある。(g) Effects of the Invention As explained above, according to the configuration of the present invention, in the connection between the terminals of the package and the terminals of the semiconductor chip, signal radiation and transmission attenuation caused by the connection can be addressed by design. It is possible to provide an ultra-high-speed semiconductor integrated circuit device having a possible connection structure, which has the effect of making it possible to improve the operating speed of the ultra-high-speed semiconductor integrated circuit device.
第１図は従来の超高速半導体集積回路装置の一
実施例の構造を示す断面図、第２図は本発明の構
成による超高速半導体集積回路装置の一実施例の
構造を示す断面図、第３図〜第７図はその配線板
におけるそれぞれ異なつた実施例の断面図ａと裏
面視平面図ｂである。
図面において、１，１１はパツケージ、２，１
２は半導体チツプ、３，１３はリード端子、４，
５，１４，１５は端子、６はワイヤ、１６は配線
板、７，１７は蓋、１８は絶縁基板、１８ａは合
わせマーク、１９は伝送路、１９ａは接続線、１
９ｂ，１９ｃは接地導体、１９ｄは抵抗素子、１
９ｅは回路素子、１９aa，１９ab，１９bb，１
９cbは接続部をそれぞれ示す。
FIG. 1 is a sectional view showing the structure of an embodiment of a conventional ultra-high-speed semiconductor integrated circuit device, and FIG. 2 is a sectional view showing the structure of an embodiment of an ultra-high-speed semiconductor integrated circuit device according to the present invention. 3 to 7 are a cross-sectional view (a) and a plan view (b) of different embodiments of the wiring board, respectively. In the drawing, 1 and 11 are package, 2 and 1
2 is a semiconductor chip, 3 and 13 are lead terminals, 4,
5, 14, 15 are terminals, 6 is a wire, 16 is a wiring board, 7, 17 is a lid, 18 is an insulating board, 18a is a matching mark, 19 is a transmission line, 19a is a connection line, 1
9b, 19c are ground conductors, 19d is a resistance element, 1
9e is a circuit element, 19aa, 19ab, 19bb, 1
9cb indicates a connection part.
Claims (1)
体チツプ上の外部導出端子と該外部リード導体と
の間を相互接続する配線板とを具備し、 該配線板は、絶縁基板上に所定の伝送線路特性
を持つように信号線と接地導体とを対向配置した
伝送路を形成してなり、該信号線により前記外部
導出端子と前記外部リード導体との相互接続を行
なつたことを特徴とする半導体集積回路装置。[Claims] 1. A semiconductor chip, an external lead conductor, and a wiring board interconnecting external terminals on the semiconductor chip and the external lead conductor, the wiring board being an insulating substrate. A transmission line is formed in which a signal line and a ground conductor are arranged facing each other so as to have predetermined transmission line characteristics, and the signal line interconnects the external lead terminal and the external lead conductor. A semiconductor integrated circuit device characterized by:
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58243410A JPS60136232A (en) | 1983-12-23 | 1983-12-23 | Semiconductor integrated circuit device |
| KR1019840007835A KR900001273B1 (en) | 1983-12-23 | 1984-12-11 | Semiconductor integrated circuit device |
| DE8484402696T DE3482353D1 (en) | 1983-12-23 | 1984-12-21 | INTEGRATED SEMICONDUCTOR CIRCUIT ARRANGEMENT WITH ULTRA-HIGH SPEED WITH A MULTI-LAYER LADDER. |
| EP84402696A EP0148083B1 (en) | 1983-12-23 | 1984-12-21 | Ultra-high speed semiconductor integrated circuit device having a multi-layered wiring board |
| US06/920,938 US4751482A (en) | 1983-12-23 | 1986-10-20 | Semiconductor integrated circuit device having a multi-layered wiring board for ultra high speed connection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58243410A JPS60136232A (en) | 1983-12-23 | 1983-12-23 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60136232A JPS60136232A (en) | 1985-07-19 |
| JPH0216582B2 true JPH0216582B2 (en) | 1990-04-17 |
Family
ID=17103445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58243410A Granted JPS60136232A (en) | 1983-12-23 | 1983-12-23 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60136232A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002368156A (en) | 2001-06-11 | 2002-12-20 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
-
1983
- 1983-12-23 JP JP58243410A patent/JPS60136232A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60136232A (en) | 1985-07-19 |
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|---|---|---|---|
| EXPY | Cancellation because of completion of term |