JPH02165191A - Display controller - Google Patents

Abstract

PURPOSE:To constitute the controller so that a count value of a horizontal scanning counter is set to '0' at the time of switching ad a display timing generating function of high versatility can be obtained, while minimizing a hardware by providing a means for making a coincidence detecting signal ineffective only in a specific scanning period and initializing the count value of the scanning counter. CONSTITUTION:The controller is provided with a storage means 3 in which values of each scanning period width are stored, and scanning counters 13, 14 for deciding the end of every scanning period. Also, this controller is provided with a means for making a coincidence detecting signal ineffective in only a specific scanning period, and initializing a count value of the scanning counter. In this state, a reset operation of the counters 13, 14 for controlling a scanning time of a display device is inhibited in a prescribed period of the scanning timing. In such a way, the scanning period can be switched without resetting the scanning timing counter, and a timing control of high versatility can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image display device, and more particularly to a display control device that generates display timing for a display device.

[Conventional technology]

A raster scanning type CRT display is used as a display device, and information such as sentences (hereinafter referred to as text), figures and images (hereinafter referred to as graphics), etc., is stored in a display memory (for example, a display memory using dynamic memory). The function of displaying is one of the important functions of a display processing device.

Conventionally, in this type of display device, information to be displayed on the screen, such as text and graphics, is stored in a display memory, and is sequentially read out in synchronization with the scanning timing of the CRT, converted into a video signal, and transmitted to the CRT. A method of supply is being adopted.

In the raster scanning method, a line (raster) of consecutive points in the horizontal direction is swept from the top to form a screen due to the afterimage effect of the eye, and this sweep is repeated at regular intervals to create a stable state. An image is obtained. As shown in Figure 9, such raster scanning methods include interlaced scanning, in which - images are interlaced scanned and divided into even and odd fields, doubling the number of images on the screen and displaying them alternately. There are two methods: a method shown in FIG. 10, and a non-interlaced method which does not perform the interlaced scanning described above. In home televisions, the interlaced method is used because the more screens there are per unit time, the less flickering the screen feels. On the other hand, in the case of display devices using the above-mentioned memory, a non-interlaced method is often adopted, which is easy to control and simply scans sequentially according to the arrangement of data.

However, recently, new media-related devices such as personal computers, word processors, and the Captain System have become popular in general households, and as home televisions have become more high-definition, non-interlaced dedicated character displays or dedicated There is a desire for a function that allows not only graphic displays but also interlaced home televisions to easily display similar high-quality displays.

FIG. 8 is a block diagram showing the configuration of a display control device that generates the above-mentioned interlaced display timing signal. The device shown in FIG. 8 controls the operation of the entire system by a microprocessor 100, stores programs and processing data executed by the microprocessor 100 in a main memory 101, and interfaces with a CRT display 104 via a display control unit 103. The display data stored in the display memory 102 is then manipulated to perform desired CR1 display and realize various processing functions.

In interlaced screen scanning, as shown in Figure 9, scanning starts from the top left corner of the screen and ends at the bottom center of the screen (hereinafter referred to as even field scanning), and scanning starts from the top center and ends at the bottom right corner of the screen (hereinafter referred to as even field scanning). The display control unit 10
3 requires timing control to alternately perform even field scanning and odd field scanning, and specifically, the vertical synchronization signal generated when switching from even field scanning to odd field scanning is controlled by % of one horizontal scanning period. It must occur at the same time.

The display III control unit 103 includes a horizontal scanning counter that continuously counts the width of one horizontal scanning period, a horizontal display period,
It is equipped with a timing register that stores the value of each horizontal scanning period width such as a blanking period and a horizontal synchronization period, and the value of each horizontal scanning period width stored in this timing register is read out and used as the value of the horizontal scanning counter. They are compared sequentially, and each time a match is detected, the horizontal scanning counter is reset to 0, and the value read from the timing register is switched to the next horizontal scanning period and the counting operation is performed again. From then on, this is repeated to determine the timing of each horizontal scanning period. Generate a signal.

Here, the timing of % horizontal scanning for generating the vertical synchronization signal of interlace scanning is determined by providing timing registers that divide the horizontal display period into two periods, A period and B period, and period B is % horizontal scanning. By storing a value that occurs at the timing of a period, a timing signal for period B is generated in the same way as each horizontal scanning period described above, and the vertical synchronization signal output at the end of an even field is this B 1ul1. If the timing signal between % horizontal scans is generated at the timing of horizontal scan, and the vertical synchronization signal output at the end of odd field is generated at the start timing of one horizontal scan, then this can be repeated alternately. It is possible to generate a vertical synchronization signal that controls the timing of interlaced scanning. Also, during the vertical display period, continuous display addresses are generated using the value of the horizontal scanning counter described above and supplied to the display memory 102, and during periods other than the vertical display period, the value of the horizontal scanning counter described above is used. A continuous dynamic memory refresh address is generated and supplied to the display memory 102.

[Problem to be solved by the invention]

In the conventional display control device described above, the address of the display memory 102 is generated based on the count value of the horizontal scanning counter during the horizontal display period, and during the display period, the address of the display data stored in the display memory 102 is generated. During the non-display period, dynamic memory refresh addresses are generated sequentially. However, in order to generate the timing necessary for controlling interlaced scanning, etc., the horizontal display period is divided into multiple periods as described above. Since the count value of the horizontal scanning counter is set to 0 at the time of switching between these periods, there is a drawback that the addresses supplied to the display memory 102 become discontinuous.

Here, when the count value of the horizontal scanning counter can be used directly, there is a need for a display control device that can perform control such that the count value is not initialized even when switching between multiple periods. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display control device that improves the problems encountered in conventional display timing generation and has a highly flexible display timing generation function while minimizing hardware.

[Means to solve the problem]

The display control device of the present invention includes: a storage means in which a value of each scanning period width obtained by dividing one scan of the display device into a plurality of periods is stored; a scanning counter for determining the end of each scanning period; A display control device that generates a display timing of a display device, comprising a comparison device that reads a value of each scanning period width stored in the storage device and compares it with a value of the scanning counter to generate a coincidence detection signal. The apparatus includes means for generating an initialization signal that invalidates the coincidence detection signal only during a specific scanning period, and initializing the count value of the scanning counter.

(Function) According to the present invention, the reset operation of a counter that controls the scan timing of a display device is prohibited during a predetermined period of the scan timing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a display control device according to a first embodiment of the present invention.

In the device shown in FIG. 1, the operation of the entire system is controlled by a microprocessor 1, a program to be executed by the microprocessor 1 is stored in a main memory 2, and a multiplexer 6
to manipulate the display data in the display memory 3 to obtain the desired C.
Realizes R7 display. The display memory 3 stores character code data as display information. The character generator 8 generates a character pattern based on the character code data read from the display memory 3. This character pattern is based on the dot clock 40 generated by 03CII.
The data is transferred to the shift register 10 in synchronization with a timing clock 41 generated for each character, converted into serial display data in synchronization with a dot clock 40 generated by 0SCII, and sent as a video signal 50 to the CRT 9. Horizontal timing control circuit 4 is timing clock 4
Based on the output of the horizontal scanning counter 13, which counts by 1, a counting operation for each period of horizontal scanning is performed. Each period width and the value of the horizontal scanning counter 13 are sequentially compared and a comparison match signal 46 is generated every time they match. The horizontal scanning counter reset signal 49 is transmitted to the horizontal timing control circuit 4.
When the later-described horizontal display A period signal 45 outputted by the gate circuit 15 is in an inactive state, a comparison match signal 46 is extracted by the gate circuit 15, and the horizontal scanning counter 13 is set to 0.
Reset to . Further, the vertical timing control circuit 5 has 1
A vertical scanning counter 1 that counts each time a horizontal display A period signal 45 occurs at the start timing of horizontal scanning.
Based on the output of 4, a vertical synchronization signal 44, a vertical display period signal 47, and a comparison match signal 48 are generated in the same way as the horizontal timing control circuit 4, and the contents of the vertical scanning counter 14 are reset to 0 by the comparison match signal 48. Ru. The display address generation circuit 7 sequentially generates display addresses for the display memory 3 based on the values of the horizontal scanning counter 13 and the vertical scanning counter 14. The multiplexer 6 generates an address switching signal 51 by ANDing the horizontal display period signal 52 and the vertical display period signal 47 generated by the horizontal timing control circuit 4 in the gate circuit 16, and if the state is active, the display address generation circuit Connect the display address output of 7 to the address of display memory 3, and conversely connect the address switching signal 51.
If the state of is inactive, the address of the display memory 3 is switched to the address bus 17, allowing the microprocessor l to rewrite the display data of the display memory 3 via the data bus 18. The interlace control circuit 24 adjusts the generation timing of the vertical synchronization signal 44 to the timing of a horizontal display A period signal 45 and a horizontal display B period signal 57, which will be described later, every time the vertical display period signal 47 is generated by the vertical timing control circuit 5. The interlaced vertical synchronizing signal 56 is generated by switching alternately and output to the CRT 9.

FIG. 2 is a detailed block diagram of the horizontal timing control circuit 4 shown in FIG. 1. The horizontal timing register 62 stores the widths of five periods during horizontal scanning: an offset area period, a horizontal display area period, a right blanking period, a horizontal synchronization period, and a left blanking period. It can be rewritten from the microprocessor 1 via the microprocessor 1. Comparison circuit 63 compares the set value for each period supplied from horizontal timing register 62 and the count value of horizontal scanning counter 13, and generates a comparison match signal 46 when detecting a match between the two. The address counter 60 supplies an address starting from 0 as the selected address for each period stored in the horizontal timing register 62, and counts up by the comparison match signal 46 generated by the comparison circuit 63, thereby increasing the address for the horizontal timing register 62. Switch sequentially. If the counter value is "4", the comparison match signal 46 causes it to become 0.
, and the counting operation from "0" to "4" is repeated thereafter. The multiplexer 64 uses the address generated by the address counter 60 and the address by the address bus 17 manually, and when the state of the register write signal 53 generated when the microprocessor 1 rewrites the contents of the horizontal timing register 62 is active, the multiplexer 64 inputs the address generated by the address counter 60 and the address by the address bus 17. It is connected to the address decoder 61, and when inactive, the address output of the address counter 60 is connected. Address decoder 61 is multiplexer 6
In order to decode the address selected by 4 and select the setting value of the horizontal timing register 62, when the input address is rQJ, the horizontal display A period signal 45 is "1", and when the input address is "1", the horizontal display B period signal 57 is "2". '', a right blanking signal 59 is generated, a horizontal synchronizing signal 43 is generated when the signal is 3, and a left blanking period signal 58 is generated when the signal is 4. Furthermore, a horizontal display period signal 52 is generated by extracting the logical sum of the horizontal display A period signal 45 and the horizontal display period signal 57 in the gate circuit 65 .

FIG. 3 is a horizontal scanning timing diagram of the display control device of this embodiment, and FIG. 4 is a timing diagram of vertical synchronizing signals for interlaced scanning. Timing control of interlaced scanning will be explained with reference to FIGS. 3 and 4.

The horizontal timing register 62 contains the horizontal display area period,
Set the value of each period width of right blanking period, horizontal synchronization period, and left blanking period. Further, a value that corresponds to the total number of stations for each period of one horizontal scan is set in the offset area period. The address decoder 61 generates the horizontal display A period signal 45 based on the value of the address counter 60 and sets the offset area period of one horizontal scan in the horizontal timing register 62 to t#, and the set value read out is sent to the comparison circuit. 63, horizontal scanning counter 1
3, and when the count value reaches the value of the offset area period width, the comparison circuit 63 generates a comparison match signal 46, but since the horizontal display A period signal 45 is active in the gate circuit 15, the horizontal The scan counter 13 is not reset, and only the address counter 6° is counted up. Therefore, the address decoder 61
generates the horizontal display B period signal 57 and switches to the horizontal display area period which is the next horizontal scanning period, while the horizontal scanning counter 13 continues counting operation. When the counting operation for the horizontal display area period is completed, the horizontal scanning counter 13 is reset to 0 by the horizontal scanning counter reset signal 49 output from the gate circuit 15.
Thereafter, counting operations for a right blanking period, a horizontal synchronization period, and a left blanking period are sequentially performed while switching scanning periods in the same manner, thereby completing the counting operation for one horizontal scan.

By repeating the above series of operations, the horizontal timing control circuit 4 generates each horizontal scanning timing. By switching the output timing of the vertical synchronizing signal 44 for each field scan with the generated horizontal display B period signal 57, an interlaced vertical synchronizing signal 5 as shown in FIG.
Generate 6.

Here, the address for the display memory 3 output from the display address generation circuit 7 is the horizontal scanning counter 1.
Based on the value of 3, a continuous address is generated as a display data address during the display period and as a dynamic memory refresh address during the non-display period.

Next, as a second embodiment of the present invention, a display control device that performs vertical screen division and superimposes display on an external video signal will be described.

FIG. 5 is a block diagram of a display control device according to a second embodiment. In the apparatus of FIG. 5, the horizontal timing control circuit 20
1. Except for the vertical timing control circuit 202, external synchronization signal detection circuit 203, video output switching circuit 204, and related signals, the configuration and operation of the device are the same as those of the first embodiment, so the details will be explained below. Further explanation will be omitted.

The external synchronization signal detection circuit 203 in the device shown in Fig. A rising edge of the input is detected to generate a horizontal synchronization reset signal 205 and a vertical synchronization reset signal 206. The video output switching circuit 204 switches the external video signal separated from the aforementioned composite video signal and the internal video signal 207 generated based on the display data stored in the display memory 3 output from the shift register 10 at horizontal timing. Control circuit 20
It is switched depending on the state of the horizontal display A period signal 57 outputted by the video signal 50 and sent to the CRT 9 as a video signal 50.

FIG. 6 shows the horizontal timing control circuit 20 shown in FIG.
FIG. 1 is a detailed block diagram of FIG. Horizontal synchronization reset signal 2
05 occurs, the value of the address counter 60 is set to "3".
The horizontal synchronization period is selected via the address decoder 61 by presetting the counter clear signal 209 output from the gate circuit 208 to the gate circuit 15.
The signal is output as a horizontal scanning counter reset signal 49 via the horizontal scanning counter 13 to reset the horizontal scanning counter 13. - Other configurations and operations are the same as those of the horizontal timing control circuit 4 of the first embodiment shown in FIG. 2, so explanations will be omitted. Further, when the vertical timing control circuit 202 generates the vertical synchronization reset signal 206, it sets the vertical synchronization period in the same way as the horizontal timing control circuit 201, and
Reset the vertical scanning counter 14.

The above control allows the internal operation timing to be adjusted to the external NTS.
Synchronize with C method timing.

Here, the timing of the horizontal display A period signal 45 outputted by the horizontal scanning timing control similar to that of the first embodiment is shown in FIG. 7, and the timing control of vertical screen division will be explained.

The horizontal display B period signal 57 is input to the video output switching circuit 204 in FIG.
is selected and output to the CRT 9, and when it is "1", an external video signal is selected and output to the CRT 9. By repeating this for one field, as shown in FIG. 7, the screen can be divided in the vertical direction to display different display information 1, for example, a television screen and a text screen such as a telop, at the same time. Furthermore, the vertical division position can be changed simply by rewriting the set value of the offset area period in the horizontal timing register 62 in FIG. 6 by scanning the microprocessor 1.

Here, as in the first embodiment, the horizontal scanning counter 13 is not reset at the end of the offset area period, so the addresses for the display memory 3 output from the display address generation circuit 7 are always generated continuously. Therefore, display data such as a text screen stored in the display memory 3 can be handled as continuous coordinates on the display screen of the CRT 9, and when displayed on a television screen etc., it can be handled by scrolling, etc. Highly scannable for applications.

In the above-mentioned embodiment, an example of timing control in which the horizontal display period is divided into two was particularly shown, but it is also possible to easily realize vertical screen division control or horizontal screen division control of three or more by using the apparatus of the present invention. can be easily inferred.

〔Effect of the invention〕

As explained above, the present invention adds a simple gate circuit and makes it possible to switch the scanning period without resetting the scanning timing counter, thereby enabling timing control of interlaced scanning, vertical screen division, etc. Even complex timing control can be achieved by using the count value of the scanning timing counter to achieve highly flexible timing control, eliminating the need for a dedicated counter, sharing hardware, and providing a highly economical display control device. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a display control device according to a first embodiment of the present invention, FIG. 2 is a detailed block diagram of a horizontal timing control circuit 4 of the first embodiment, and FIG. FIG. 4 is a timing diagram of the horizontal scanning signal of the embodiment and the second embodiment. FIG. 4 is a timing diagram of the vertical synchronization signal of the interlaced scan of the first embodiment. FIG. 5 is a block diagram of the display control device of the second embodiment. 6 is a detailed block diagram of the horizontal timing control circuit 201 of the second embodiment, FIG. 7 is a timing diagram of vertical screen division of the second embodiment, and FIG. 8 is a conventional display control diagram. A block diagram of the apparatus, FIG. 9 is a timing diagram of the interlaced scanning method, and FIG. 10 is a timing diagram of the non-interlaced scanning method. 1...Microprocessor, 2...
...Main memory, 3...Display memory,
4...Horizontal timing control circuit, 5--
--- Vertical timing control circuit, 6...
...Multiplexer, 7...Display address generation circuit, 8...Axis...Character generator, 9...CRT, 10-
...Shift register 11-----0S
C, 12... Dot counter 13...
. . . horizontal scanning counter, 14 . . . vertical scanning counter, 15 ------- gate circuit,
16...Gate circuit, 17---------
-Address bus, 18...Data bus, 40.
・・・・・・・・・Dot clock, 41・・・・・・
...Timing clock, 43...Horizontal synchronization signal, 44-...Vertical synchronization signal, 45--
--------Horizontal display A period signal, 46...
・・Comparison match signal, 47−−−−−−−Le direct display period signal, 4 B−・・・・・Comparison match signal, 49
------------Horizontal scanning counter reset signal, 5
0-......Video signal, 51-...Address switching signal, 52-
------Horizontal display period signal, 53...
...Register write signal, 56--Interlaced duplex synchronization signal, 57--Horizontal display B period signal, 58-- Left blanking signal, 59...Right blanking signal, 60...Address counter, 6
1---------Address decoder, 62-...
...Horizontal timing register, 53------
---Comparison circuit, 64-----Multiplexer, 100...
... Microprocessor, +01 ... Main memory, If)2 --- Display memory, 103 ... Display control section, +04 ...
CRT, ---Light Ben, ---Horizontal timing control circuit, ---Vertical timing control circuit, ---External synchronization signal detection circuit, ---Video output switching circuit, ...Horizontal synchronization reset signal, ...-Vertical synchronization reset signal, ...Internal video signal, ...Gate circuit, ...-Counter clear signal.

Claims (1)

[Scope of Claims] 1. A storage means in which a value of each scanning period width obtained by dividing one scan of a display device into a plurality of periods is stored, and a scanning counter for determining the end of each scanning period; A display control device for generating a display timing of a display device, the display control device having a comparison device for reading the value of each scanning period width stored in the storage device and comparing it with the value of the scanning counter to generate a coincidence detection signal. . A display control device, comprising: means for generating an initialization signal that invalidates the coincidence detection signal only during a specific scanning period, and initializing the count value of the scanning counter.