JPH02162983A - Time axis correction device - Google Patents

Abstract

PURPOSE:To realize phase modulation of a sampling clock by dividing a clock being an integral number of multiple of a frequency of the sampling clock to generate polyphase clocks and selecting one of them. CONSTITUTION:A write control circuit 7 sets a memory write address based on a horizontal synchronizing signal HS to apply write to a memory 2. Then A/D conversion and memory write are applied. The control of A/D conversion and memory write is implemented based on an output clock of a phase modulation circuit 23. On the other hand, a readout control circuit 8 uses a clock having a prescribed phase to generate a memory readout address and a memory readout control signal, frequency-divides the clock to set the memory readout address for each period of a reference horizontal synchronizing signal thereby reading a data for each line from the memory 2, then a video signal data subjected to time axis correction is obtained from the memory 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a time axis correction device for removing time axis fluctuations from a video signal having time axis fluctuations such as a reproduction signal of a VTR.

[Prior art] Figure 6 is Japan Broadcasting Publishing Association - rVTR technology" P, I+8
is a block diagram shown as an example of the configuration of a time axis correction device. In the same figure, Ill is an A/D converter, (2) is a memory, (3) is a D/A converter, and (4) is a write clock. generation circuit, (5) is a read clock generation circuit, (
+01 is an input terminal for a video signal, (1:) is an output terminal for a video signal, and (12) is an input terminal for an external reference synchronization signal.

Next, the operation of the above configuration will be explained.

When a video signal with a time axis variation is inputted from a terminal (10) to a write clock generation circuit (4), a write clock matching the time axis variation is outputted. Using this write clock, the A/D converter (1) samples and converts it into PCM, and writes the sampled value to the memory (2).

On the other hand, the read clock generation circuit (5) creates a clock for reading data from the memory (2) based on the external reference synchronization signal input from the terminal (12), and synchronizes with this read clock. Data is read from the memory (2) and converted back to an analog signal by the D/A converter (3). Through the above process, time axis fluctuations are removed from the input video signal, and an output video signal whose time axis is stabilized in synchronization with the external reference signal is obtained.

There are various means for generating the write clock mentioned above.
An example of this is Japanese Patent Application Laid-Open No. 58-124385,
A method is disclosed that detects time axis fluctuations based on a burst signal included in an input video signal and quickly responds to the time axis fluctuations.

Figure 7 is a waveform diagram for explaining the principle of detecting sampling point shifts due to time axis fluctuations.If the period of the sine wave forming the burst signal is four times the sampling period, the burst signal can be sampled. , as shown in the figure, four sample points are obtained per period. The level of each sample point is (X11.(X21.(X3)iX4)
XI IIB+As
1nθX2-8+85inf o+90°l -B+A
cos θX3- 13+ 8 sin (θ 4180
° )-8-8s in θX4- B÷8 in (
θ◆270°] ・B-A cos θ. Here, the amplitude of the burst signal is (A), the DC level is (B), and the phase of the sampling point corresponding to the sampling point level (x1) is (θ).

Therefore, Xl-X3.2A sin θ

If 0, 5 a, -11 = Wataru Xl - Tomo θ·0 is used as the reference for the sampling point, the deviation of the sampling point from the reference position can be found by calculating the phase (θ) of the sampling point. Therefore, by changing the phase of the sampling clock according to the phase (θ) of the sampling point, it is possible to obtain a write clock that corresponds to time axis fluctuations.

FIG. 8 is a block diagram of a phase modulation means shown as an example of a method of changing the phase of a sampling clock in Japanese Patent Application Laid-Open No. 58-124385. - (39) are delay elements, delay elements (34) - (36) provide a delay amount of 1/4 of the period of the sampling clock, and delay element (37) provides a delay amount of 1/4 of the sampling clock period.
) to (39) are l/16 of the period of the sampling clock.
gives the amount of delay. Further, +31) and +321 are data selectors, and (33) is a buffer amplifier. The phase modulation means having the above configuration has three delay elements (34) to (36) each weighted to a delay amount of 1/4 of the period of the sampling clock connected in series, and each input/output terminal is connected to a data selector (31). ) and three delay elements (37) to (39) each weighted to a delay amount of 1/16 of the sampling clock period.
and the data selector (32) connected in the same way as Kitagi, and the reference clock is connected to the buffer amplifier (32).
3) as an input. And 1. The phase of the sampling clock can be changed by giving data corresponding to the clock delay amount determined from the phase (θ) of the sampling point obtained by the method described above to the data selectors (31) and (32) as a minute time axis error signal. Modulated.

[Problems to be Solved by the Invention] In the conventional time axis correction device configured as described above, the phase modulation means of the sampling clock that responds at high speed according to the time axis fluctuation of the human input video signal is used as a phase modulation means (C1 Fig. 8). The configuration shown in was used, but when using such a conventional sampling clock phase modulation means,
data selector +31), +321 and delay element (
37) to (39) must be precisely matched, which poses a problem in that adjustment is difficult and impractical.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a time axis correction device that can eliminate the need for adjusting a clock phase modulation means for changing the phase of a sampling clock.

[Means for Solving the Problems] A time axis correction device according to the present invention samples a burst signal included in an input video signal.

Clock phase modulation means for changing the phase of the sampling clock according to the phase of the sampling clock calculated from the sampling value; The present invention is characterized by comprising a sampling clock selection means for selecting one of the multiphase clocks.

[Operation] According to the present invention, the sampling clock is divided into multiphase clocks having a frequency that is an integral multiple of the sampling clock, and one of the multiphase clocks is selected according to the required phase shift gl. As a result, the phase modulation of the sampling clock can be performed as specified, so that there is no need to adjust the amount of delay.

[Embodiments of the Invention] Hereinafter, an embodiment of the present invention will be described based on the drawings. FIG. 1 is a block diagram of a sampling clock phase modulation circuit in a time base correction device according to an embodiment of the present invention. In, (25) is a four-phase clock generation circuit, (
z6) is one of the four phase clocks according to the select signal.
(27) is a delay line; +281 is the first select circuit (26)
This is a second select circuit for selecting the output of the delay line (27) and the output of the delay line (27) according to a select signal.

FIG. 2 is a block diagram showing the configuration of a time axis correction device according to an embodiment of the present invention, which includes the sampling clock phase modulation means. In the figure, (1) is an A/D converter, which converts a video signal input from a terminal (lO) into digital data. (2) is a digital memory that stores digital data output from the A/D converter (1). (3) is a D/A converter which converts the output of the digital memory (2) into an analog signal. (6)
1 is a synchronization separation circuit for separating the horizontal synchronization signal from the input video signal, and (7) is a write control circuit that controls data writing to the digital memory (2). (8)
is a read control circuit which controls reading from the digital memory (2).

(21) is a burst sampling circuit which samples the data of the burst signal portion. (221 is an arithmetic circuit, which calculates the phase from the burst sample value output from the burst sample circuit (21), determines the phase modulation value, and sends a selection signal to the phase modulation circuit (23). +2
31 is a phase modulation circuit that changes the phase of the sampling clock according to the time axis error of the input video signal. (24) is a reference clock generation circuit that generates a clock that serves as a reference for sampling, memory writing, and reading.

The sampling clock phase modulation means shown in FIG. 1 corresponds to the phase modulation circuit (23) in FIG. 2.

Next, the operation of the above configuration will be explained.

Here, as the input video signal (VSI), as shown in FIG. 3 as an example, it is assumed that a bust signal (BSI) is inserted every horizontal scanning period between the horizontal synchronizing signal +H3I.

The input video signal (VS) is input to the A/D converter (1), converted into digital data, and is input to the synchronization separation circuit (6). This synchronization separation circuit (6) separates the human input video signal (horizontal synchronization signal +Its from VSI) and sends it to the write control circuit (7), and also sends pulses for burst sampling positioning and burst sampling start control to the burst sampling circuit ( 21). The burst sample circuit (21
), the four consecutive samples of the burst signal, i.e., TXIl, (X2), (X3),
Hold TM01. Next, the burst sampling value is sent to the arithmetic circuit (22), which calculates the phase (θ) of the sampling point using the method described above, and determines the amount of deviation of the sampling point caused by the time axis fluctuation. This arithmetic circuit (22) further creates a selection signal to be sent to a phase modulation circuit (23) having the configuration shown in FIG. 1 in order to realize phase modulation according to the deviation of the sampling point.

In the phase modulation circuit (23), the four-phase clock generation circuit (25) has a phase modulation clock, that is, FIG.
As shown in FIG. 2, a clock having a frequency four times that of the sampling clock is supplied from the reference clock generation circuit (z4). In this four-phase clock generation circuit (25), the frequency of Hiki's human-powered clock (a) is divided by four to create fb++ in FIG.
, tbzl, (b3), (4 as shown in b4t)
Generate phase clock. To be more specific, the four-phase clock generation circuit (25) is composed of a four-frequency divider circuit (30) and a shift register (II), as shown in FIG. Then, the L input clock (at) is divided into 4 circuits (
30) and then manually input it to the data input terminal of the shift register (11). This shift register (11)
Since the original clock, which is not frequency-divided, is input to the clock input terminal of
Four-phase clocks shown in l) to (b4) are obtained.

Then, the output of the J:, 4-phase clock generation circuit (25) is input to the first selection circuit (26), and in this first selection circuit (26), the output of the four-phase clock generation circuit (25) is inputted to the first selection circuit (26). The above four-phase clock (b
One of ll to (b4) is selected and output.

One of the outputs of this first select circuit (26) is applied directly to the second select circuit (2B), and the other output is applied to the second select circuit (28) via a delay line (27). . Here, the delay amount of the delay line (27) is set to 1/8 of the output clock period, and the second select circuit (28) can be switched by the select signal output from the arithmetic circuit (22). This shifts the phase by 45°.

In this way, phase modulation of the sampling clock is realized by the select signals of the first select circuit (26) and the second select circuit (28). In the final time axis correction operation, when sampling of the previous line and writing to memory are completed, the basic phase clock for burst sampling is returned. For example, (bl) to (b4 in Fig. 4)
) is selected from among the four-phase clocks (bl), and the second select circuit (28) selects
) is selected based on the state in which the clock that is directly supplied from the clock is selected. If the burst waveform is sampled using the clock in this reference state and the phase of the sampling clock is calculated to be delayed by θ=135'' with respect to the original sampling phase using the procedure described above, the first select circuit (26)
clock (b2), and the second select circuit (28
) to select the output of the delay line (27), respectively.
-Hee Jc! A select signal is output from the arithmetic circuit (22). As a result, the phase of the sampling clock is 135
Sampling is performed at a predetermined position, since it lags behind the reference by .

By the above-described operation, it is possible to remove the time axis fluctuation component that is less than or equal to the sampling clock period.

Therefore, by starting writing the video signal data to the memory (2) at a fixed interval away from the horizontal synchronization signal fHs and reading it out at fixed intervals according to the reference read clock, fluctuations in the time axis can be avoided. This is the removed signal.

In FIG. 2, the write control circuit (7) sets a memory write address based on the horizontal synchronization signal +831, and writes to the memory (2). Here, A/D conversion and memory write control are performed. , are performed based on the output clock of the phase modulation circuit (23). On the other hand, the readout control circuit (8) uses a clock with a constant phase to create a memory readout address and a memory readout control signal, and divides the clock to perform memory readout every cycle of the reference horizontal synchronous chair signal. By setting the address, data is read line by line from the memory (2), so that time-axis corrected video signal data can be obtained from the memory (2). Therefore, by D/A converting the output of the memory (2), a video signal with n time axis correction is obtained.

Note that in the above embodiment, a four-phase clock was used in the one-phase modulation circuit (23) by manually inputting a clock with a frequency four times that of the sampling clock. Precision can be improved by creating a clock with an integer phase as an input. By adding this and another select circuit, the time resolution of correction can be improved. By adding more stages of such delay lines and select circuits, it is possible to improve the time resolution in proportion to the number of stages.

Further, in the above embodiment, the synchronization separation circuit +61 receives an analog signal as an input, but even if it is configured with a digital circuit that manually inputs A/D converted data, the same effect as in the above embodiment can be obtained.

[Effect of the Invention 1 As described above, according to the present invention, by dividing a clock having an integer multiple of the sampling clock frequency to create multiphase clocks and selecting one of them, the sampling clock Since it is possible to achieve phase modulation of 200 kHz, it is possible to greatly simplify the adjustment of the delay amount of the delay line.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a sampling clock phase modulation means in a time base correction device according to an embodiment of the present invention;
Fig. 2 is a block diagram showing the configuration of a time axis correction device according to an embodiment of the present invention, Fig. 3 is a waveform diagram showing an example of an input video signal, and Fig. 4 shows an input clock and a four-phase clock. Waveform diagram No. 5 is a block diagram showing an example of the configuration of a four-phase clock generation circuit in a phase modulation circuit, FIG. 6 is a block diagram showing the configuration of a conventional time axis correction device, and FIG. FIG. 8 is a signal waveform diagram showing the calculation method. FIG. 8 is a block diagram showing the configuration of a conventional clock phase modulation means. +251 4-phase clock generation circuit, +25)...First select circuit, (271...Delay line, (28
1...Second selection circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a time axis correction device equipped with a sampling clock phase modulation means that responds to time axis fluctuations of an input video signal, the sampling clock phase modulation means:
Multiphase clock generation means for dividing a clock whose frequency is an integral multiple of the frequency of the sampling clock to create a multiphase clock having a frequency equal to the frequency of the sampling clock, and clock selection means for selecting one of the multiphase clocks. A time axis correction device comprising: