JPH02161694A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To collectively erase memory cells by providing a means, which increases the frequencies of a time constant determining circuit to determine the leading edge time constant of a potential VPP that erases the memory cell of a semiconductor memory at the time of collective erasing. CONSTITUTION:When the frequencies, which determine the time constant to control the leading edge of the VPP in order to erase the memory cell of a memory, are collectively erased, the frequencies are set larger than those to erase the memory cell byte by byte. That is, pulses phib' and phi'b' generated from a dividing circuit (n-1) are outputted through a transfer gate, and the frequencies to determine the leading edge time constant of the VPP at the time of the collective erasing is doubled to the frequencies at the time of normal byte by byte erasing. Consequently the leading edge time constant of the VPP becomes smaller at the time of collective erasing, and the same leading edge time constant as that at the time of byte by byte writing can be obtained. Thus, the period of the output of the VPP potential becomes the same as that of the byte by byte erasing, and the collective erasing of the memory can be excellently executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an electrically programmable and erasable nonvolatile semiconductor memory device (hereinafter referred to as EEPROM).
ally Erasable and Prog
rammable Read Only Memory
(referred to as EEFROM), and in particular relates to erasing of EEFROM memory cells.

[Prior Art] FIG. 4 is a block diagram showing a generally known conventional EEFROM.

Referring to FIG. 4, this EEPROM receives a memory array 50 including EEPROM memory cells, an X address signal, and a Y address signal from the outside, and decodes these address signals to generate a word connected to a specific memory cell. X decoder 53 and X
A decoder 54, a sense amplifier/write driver 56 for reading and writing signals stored in memory cells designated by the two decoders via a Y gate 55, and a sense amplifier/write driver 56 for inputting and outputting the read signals. an output buffer 57 and a charge pump 8 for outputting V P 9 to erase individual memory cells in the memory array 50;
and a driver 9 for driving the charge pump 8.
It includes a high frequency oscillator 10 for providing a clock signal to the driver 9, and a time constant determining circuit 4 for outputting a signal CR that is provided to the driver 9 and controls the rise of the charge pump 8.

FIG. 5 shows a cross-sectional view of a memory cell of an EEPROM, and FIG. 6 is a memory array diagram specifically showing the contents of the memory array 50. One memory cell includes two transistors: a select gate transistor 39 and a memory transistor 40.

The three select gate transistors are N+ drain diffusion layers 3 formed at intervals on the main surface of the semiconductor substrate 31.
6.38 and a word line 37 formed on the main surface between the N+ drain diffusion layers 36.38 and an insulating film. Memory transistor 40 includes N+ source diffusion layers 34 formed at intervals on the main surface of semiconductor substrate 31;
An N+ drain diffusion layer 36 (shared with the select gate transistor) and a floating gate 33 formed on the main surface of the semiconductor substrate 31 and between the N+ source diffusion layer 34 and the N+ drain diffusion layer 36 via an insulating film. ,
The control gate 32 is formed on the floating gate 33 via an insulating film, and the thin insulating film between the floating gate 33 and the N+ drain diffusion layer 36 forms a tunnel oxide film 35.

The N+ drain diffusion layers 38 of the three select gate transistors are connected to the bit line 41, and the word I! 37
is connected to the output of the X decoder 53. The N+ source diffusion layer 34 is grounded via a source transistor 42, and the control gate 32 is commonly connected to memory transistors for one byte and is connected to a control gate line 43.

FIG. 7 is a graph showing voltage and current characteristics during writing and erasing of one memory cell of an EEPROM. Writing and erasing operations for one memory cell will be described with reference to FIGS. 5 to 7.

When writing (data "0") to one memory cell, the drain electrode V of the select gate transistor 39
D and gate electrode VsG with high voltage (usually 16-20V)
, a low voltage (usually OV) is applied to the control gate 32, and the source electrode V.

to a floating state. By doing so, electrons are extracted from the floating gate 33 by a tunneling phenomenon from the tunnel injection part 44 formed at the drain of the memory transistor 40 through the very thin tunnel oxide film 35 formed above. Therefore, the threshold value of the memory transistor 40 as seen from the outside drops, and becomes a depression type. In FIG. 7, VcG is a control gate voltage, and IDS is a drain current flowing between the drain and source of the memory transistor 40. In the thermal equilibrium state, VTH becomes VTMO near oV, but in the writing state, VTH drops to VT112 (<0
), and the memory transistor becomes a depression type.

When erasing one memory cell (data “1”), in FIG. 5, VD is set to a low voltage (usually OV), V,
G is set to "H" and a high voltage (usually 16 to 20 V) is applied to VoG. At this time, the source potential V is set to Ov or a floating state.

In this state, electrons are injected into the floating gate 32 through the tunnel oxide film 35, and the vo of the memory transistor 40 as seen from the outside increases, making it an enhancement type transistor. Therefore, in FIG. 7, in the erased state, V
T s + (>O), and the memory transistor becomes an enhancement type.

Next, 1-byte memory cell and chip-batch erasing will be explained.

Since the control gates 32 of the 1-byte memory cells are commonly connected, the selected byte is first erased. That is, after "1" is written into the floating gate 32, a programming operation is performed on the memory transistor 40 into which information "0" is to be written. VP
The pulse width of the P pulse is determined by a timer circuit inside the chip. This is an explanation of the normal write operation, but the EEFROM has a special operation called chip-batch erase. Next, this operation will be explained. Chip-batch erasing means erasing all the contents of the entire chip in one write, and when performing this operation, all memory cells are selected regardless of the address input signal. An erase operation is performed. In other words, the chip
Batch erasing is different from erasing only selected bytes and erasing all bytes in normal operation, but there is no other difference. The same applies to the Vrr pulse width.

FIG. 8 is a diagram showing a circuit for generating a high voltage PP when erasing a memory cell.

Referring to FIG. 8, the Vpr generation circuit includes a high frequency oscillation circuit for oscillating a high frequency, a timer circuit 11 for controlling the time during which high frequency oscillation is performed, and a timer circuit for actually generating VPP. It includes a charge pump 8, a driver for driving the charge pump 8, and a time constant determining circuit 4 for determining the rise time constant of VPF'. The driver 9 includes a two-power NOR gate 24.27 and a NOT gate 25.26.28.29, here for illustrative purposes. The two-man power NOR gate 24 receives φ, which is one of the outputs of the high frequency oscillation circuit 10. The outputs C and R of the time constant determining circuit 4 are input, and the output of the two-man NOR gate 24 is input to the NOT gate 25.
5 is input to the NOT gate 26, and the output φd of the NOT gate 26 is input to the charge pump 8. 2
The human-powered NOR gate 27 is supplied with one of the outputs of the high frequency oscillation circuit [0]d)c, and the output C of the time constant determination circuit 4.
1R is input, and the output of the two-man NOR gate 27 is N.
The output of the NOT gate 28 is inputted to the NOT gate 29, and the output φd of the NOT gate 29 is inputted to the charge pump 8.

The time constant determining circuit 4 includes a VrP dividing circuit 6, a differential circuit 7, a switched capacitor 5, a frequency conversion circuit 2, and a low frequency oscillation circuit 1. Of these, the VP-dividing circuit 6 has a capacitance of C
1 and C2. One end of the capacitor C5 is grounded, and the other end is connected to the capacitor C2 and input to the differential circuit 7. One side of the capacitor El e z is the output Vr p of the charge pump 8.
The other is connected to the capacitor C1 and input to the differential circuit 7.

The switched capacitor includes enhancement type N-channel MO3) transistors 22 and 23 (hereinafter referred to as N-type transistors) and capacitances Cz and Cm. The drain of the N-type transistor 23 is connected to Vcc, the source is connected to one electrode of the capacitor 11Ca, and also connected to the drain of the N-type transistor 22, and the gate is connected to one of the outputs of the frequency conversion circuit 2, φb. Connected. Nu) The source of the transistor 22 is connected to one electrode of the capacitor C3 and is input to the differential circuit 7, and the gate is one of the outputs of the frequency conversion circuit 2 φ. connected to. The other electrodes of capacitors C3 and C4 are grounded.

Next, the operation of the VP voltage generating circuit will be explained.

Output φc1φ of the high frequency oscillation circuit 10. is inputted to the driver 9, outputted as φd1φd with increased driving ability, and inputted to the charge pump 8. Charge pump 8
is ■c due to φd1φd. A potential VPP necessary for writing and erasing is generated from the .

Here, the rise of Vl'P used in the EEFROM is intentionally made slow in order to strongly reduce the stress applied to the memory cell. That is, as shown in Figure 9,
It takes a time of τ1 (usually several 6 μs) to rise. The time constant determining circuit 4 shown in FIG. 8 determines this time constant.

In the time constant determining circuit 4, first, the VPP dividing circuit 6
, receives vrr output from charge pump 8, and
A predetermined voltage DVrr is created by capacitance division of ct and C2.
to dismount. This dropped Vrj is inputted to the differential circuit 7, and the S output from the switched gabacitor 5 is
It is compared with C. The differential circuit 7 receives these two inputs DV.
Compare rr with the potentials of S and C, and output C and R. The outputs C and R of the differential circuit 7 have a magnitude relationship between the D V rr input to the differential circuit 7 and S and C such that DVPP≧S.
In case of C, it becomes °H# level, and DVP r <s,
In the case of C, the level is "L". The switched capacitor 5 receives the clock φa output from the low frequency oscillation circuit 1.
, φa is further converted to a lower frequency by the frequency conversion circuit 2. ,φ. is input. Here, one of the capacitors configuring the switched capacitor 5, C
Assume that the charge of s is O. Also, ff1c3 >c4
Suppose that Now, one of the clocks φ to which the switched capacitor 5 is input. If is at “H° level,”
Its inverted signal is φ. becomes "L" level. Therefore, capacitor C4 is charged by vec through N-type transistor 23. (Charge mQ4-C6·VcC). At the next timing, when φl is at −”L” level, φゎ−
Since it becomes “H”, part of the charge charged in capacitor C4 is N type! - Discharged through transistor 22 to capacitor QC8 through L7. At this time, since the N-type transistor 23 is off, the capacitor Cs is not newly charged by VCC.

Next, capacitor C4 is charged from capacitor C2 to capacitor C3.
This is the next timing when the charge is transferred. At this time, the charge Q4 charged in the capacitor RC4 is distributed to both capacitors because the capacitors C, . Therefore, the potentials of the outputs S and C of the switched capacitor 5 rise,
The potentials V, , C are as follows. Therefore, φ. ,φ. is regularly input to the switched capacitor 5, so that the potential of the output S2C of the switched capacitor 5 increases stepwise as shown by the solid line in FIG. Therefore, the magnitude relationship between the outputs S and C of the switched capacitor 5 and the output DVrr of the VF'l' dividing circuit 6 is determined by the N in the switched capacitor 5.
DVP r <s, C only during the transient period T, ~T when the type transistor 22 opens and the potentials of S and C rise.
, and DVpp ≧S,C for all other periods.

The reason for this is as follows. That is, the value of DVPP, which is the potential obtained by capacitively dividing VPP output from the normal charge pump, is approximately equal to S and C, which are the outputs of the switched capacitor 5. However, as described above, due to the action of the N-type transistor 22, the potentials of the outputs S and C from the switched capacitor 5 instantaneously rise. Therefore, at this time, S.

The potential of C>DVr The potential of r. As a result, the differential circuit 7 drives the charge pump 8 once again. That is, since there is a time delay, the differential circuit 7 can drive the charge pump 8 during that time. 1st
The dotted line in Figure 0 shows the potential change of DVPP. Due to the time delay, the S, C potentials and DVrr
The potential of is shifted. Therefore, the period (T + ~ T
Charge pump 8 is driven only when shown in 7).

Output of differential circuit 7 (i.e. output of time constant determining circuit 4)
C and R are NOR gates 24.2 that constitute the driver 9.
7, and this NOR gate 24.27 is input to C
, R-“If it is Lo, the output φ9 of the high frequency oscillation circuit 10,
φ0 is propagated to the next stage, but if C, R is “H”, the human power to the next stage is fixed at the “L” level, and the output φd1φd of the driver 9 is fixed at the “L” level. Put it away.

Therefore, charge pump 8 stops operating and VPP
does not try to rise. That is, the outputs S and C of the switched capacitor 5 determine the rise time constant of VPP.

FIG. 11 is a graph showing the relationship between the frequency fn of T, ~T, and the rise time τn of Vrr.

The VPP rise time τ is: where K is a constant. Referring to FIG. 11, the higher the frequency, the shorter the VPP rise time.

FIG. 12 is a diagram showing the contents of the frequency conversion circuit 2. Refer to FIG. 12 [7] The frequency conversion circuit 2 includes a plurality of frequency dividing circuits (1), (2), . . . (n). That is,
Clock signal φa1φ output from low frequency oscillation circuit 1
Each time a passes through the frequency dividing circuits (1), (2), . . . (n), its frequency is halved and converted into a clock signal with a long period.

[Problems to be solved by the invention] Vp for erasing memory cells of conventional EEFROM
The r generation circuit was configured as follows. Therefore, in the batch erase mode in which all memory cells are erased at once, the load applied to the charge pump increases and the charge pump does not rise within the preset rise time τ. As a result, as shown by the chain line in FIG. 9, the rise of the output voltage from the charge pump becomes larger than the predetermined set value τ1 and becomes τ2. As a result, the time (t in the figure) for which the potential vrr is maintained for erasing the memory cells becomes short, and there is a problem that batch erasing cannot be performed successfully. Also, the period during which the voltage of Vf'P is output is reduced,
In addition to the effect of reducing I/stress on the oxide film, there is a problem in that the erase characteristics of the memory cell deteriorate.

This invention was made to solve the above-mentioned problems. - An EEPROM in which the rising edge of VPP is maintained at the same value as when erasing bytes by byte even during bulk erasing.
The purpose is to provide

[Means for Solving the Problems] In the EEPROM according to the present invention, the frequency of the time constant determining circuit that determines the rise time constant of Vl'P is increased during -batch erasing.

[Function] The EEPROM in this invention has - VP during bulk erasing.
By increasing the frequency of the time constant determination circuit that determines the rise time constant of P, the rise time constant of VPP becomes smaller during bulk erase, and even though the load for erase increases, the VPr rises with the same rise time constant as during writing.

[Embodiment of the Invention] FIG. 1 is a diagram showing a part of a time constant determining circuit which is an embodiment of the invention. Referring to FIG. 1, the time constant determining circuit according to the present invention includes a low frequency oscillation circuit 1 for generating a clock signal, a frequency conversion circuit 2 for receiving the clock signal and reducing its frequency, and a frequency converting circuit 2 for reducing the frequency of the clock signal. The frequency selection circuit 3 selectively extracts two clock signals having different frequencies from the conversion circuit 2, and the selected clock signal is applied to the switched capacitor 5.

Note that the time constant determining circuit 4 according to the present invention includes a differential circuit 7 connected to the switched capacitor 5 in addition to "-2,"
It is the same as the conventional case (see FIG. 8) in that it includes a vrr dividing circuit 6 for converting VPP outputted from the charge pump 8 into a 5 volt system potential.

The frequency conversion circuit 2 receives a clock signal φ. , φa and outputs a signal having a lower frequency than the frequency dividing circuits (1), (2), . . . (n). In this invention, two types of clock signals are output from the frequency conversion circuit 2.

The other output signal is φ output from the frequency dividing circuit (n). ,φ
There is a b-fold signal, and the other output signal is a frequency divider circuit (n)
A clock signal φ output from a frequency dividing circuit (n-1) which is a frequency dividing circuit in the previous stage.

φ. ′. The frequency divider circuit (0) halves the frequency of the input clock signal, so that the frequency is φ. , <The frequency of the ISb signal is φ. J, it is half the frequency of the 4' signals.

The frequency selection circuit 3 is an N-channel MO3 connected between the output of the frequency dividing circuit (n-1) and the switched capacitor 5, and operates in response to an externally applied signal S18.
Transistor 16 and P channel MOS transistor 1
5, the output of the frequency dividing circuit (nl), and the switched capacitor 5, and a signal SSS provided from the outside.
N-channel MO8) transistor 18 which operates in response to
, P channel MO3) transistor 17, and a frequency dividing circuit (n
) and the switched capacitor 5, an N-channel MOS) transistor 19, a P-channel MOS transistor 20, a frequency divider circuit (n), and a switch that operates according to a signal S%S applied from the outside. decapacitor 5
an N-channel MOS transistor 2l-1 that operates in response to externally applied signals S and S;
P-channel MOS transistor 22.

Next, the operation of the time constant determining circuit of the present invention will be explained. Referring to FIG. 1, signals S and D applied from the outside are each “H°6
L', and the pulse φ for determining the time constant. , 1o
is φ generated from the frequency dividing circuit (n). ,φ. is output through the transfer gate I7. However, (7, - during batch erasing, the signal S, ■ becomes "L" and "H", and the pulse φ6, which determines the time constant, is the frequency dividing circuit (n).
φ generated from the frequency dividing circuit (n-1) in the previous stage. ′、＜
6D' is output through the transfer gate. Therefore, during bulk erasing, the frequency that determines the rise time constant of Vrr is twice the normal byte-by-byte frequency. Therefore, in order to erase all memory cells, the rise of Vrr can be made as large as that during normal byte-by-byte writing, even though the load increases.

This state is shown in FIGS. 2 and 3.

FIG. 2 is a diagram corresponding to FIG. 10 of the present invention, and shows the output voltage S from the switched capacitor 5.

It is a figure showing the temporal change of C. Referring to FIG. 2, compared to the conventional example, according to the present invention, - Vr
The frequency that determines the rise time constant of r is doubled. Therefore, as shown in FIG. 11, the frequencies of T to T7 become large and the rise time of vrr becomes short. As a result, as shown in FIG. 3, the rise time of VPP is faster in the embodiment than in the conventional example, and the time t during which the potential of VPP is maintained during the VPP pulse is accordingly reduced in the conventional example ( t2).

As a result, bulk erasing of memory can be performed successfully.

In the above embodiment, the case where the frequency is doubled during the -batch erasure is explained. However, it goes without saying that the same effect can be achieved even if this frequency is multiplied by another factor.

[Effects of the Invention] As described above, according to the present invention, the frequency that determines the time constant for controlling the rise of VPP for erasing memory cells of an EEPROM is erased one byte at a time when erasing all at once. I made it larger than it would otherwise be. Therefore, the rising time constant of Ver becomes smaller during batch erasing, and even though the load for erasing increases, a rising time constant equivalent to that during byte-by-byte writing can be obtained. As a result, the period during which the potential of vrr is outputted is the same as when erasing byte by byte, and there is an effect that it is possible to provide an EEPROM in which the memory can be successfully erased all at once.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a part of a time constant determining circuit according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the invention in detail, and FIG. is E E F
1 is a schematic block diagram showing the configuration of a ROM,
FIG. 5 is a sectional view showing a cross section of one memory cell,
FIG. 6 is a memory array diagram of an EEFROM, FIG. 7 is a graph for explaining write and erase states of memory cells, and FIG. 8 is a block diagram showing a VPP generation circuit for outputting Vpr. , and Figure 9 shows the conventional EEP
10 is a graph for explaining the rising state of Vrr in the ROM, FIG. 10 is a diagram showing the relationship between the time constant determining circuit and the operation of the charge pump, and FIG. 11 is a graph for explaining the rising state of Vrr in the ROM. ,φ
12 is a graph showing the relationship between the frequency of b and the rise time of ver, and FIG. 12 is a block diagram showing the contents of a conventional frequency conversion circuit. In the figure, 1 is a low frequency oscillation circuit, 2 is a frequency conversion circuit, 3 is a frequency selection circuit, 4 is a time constant determination circuit, 5 is a switched capacitor, 6 is a vrr division circuit, 7 is a differential circuit, and 8 is a charge Pump, 9 is a driver, 10 is a high frequency oscillation circuit, 11 is a timer circuit, 15.17, 20.22 are P channel MOS) transistors, 16.18, 19.2
1 is an N-channel MOS transistor. In addition, in the figures, the same symbols indicate the same or equivalent parts. Figure 5 agent Masuo Oiwa 33; 70-nai〉bu γ'-1, 34: N'' source tt scattering layer 38: rl' 4A!hvL9 398'l!Lft 7'') transristor Figure 7 potential- 91p-,. ■ PP nX Treating Depression Procedures Amendment Kei (voluntary) 2. Name of the invention Non-volatile semiconductor memory device 3. Relationship with the amendment holder case Patent Applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4, Address: Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo (7375), Patent Attorney Masuo Oiwa (4 contacts: 3 (213) 34□11. Department 1..-, In the Detailed Description of the Invention column of the specification subject to the Leno amendment, amend the content of the amendment to "strongly" and "as much as possible" on page 10, line 15 of the specification. Vs on page 12, lines 15 and 16 of the specification.・Correct "C" to v s.

Claims (1)

[Scope of Claims] A non-volatile semiconductor memory having a plurality of memory cells and capable of electrically writing and erasing the memory cells selectively in either a byte unit containing the memory cells or in the entire memory cell mode. An apparatus comprising: memory cell erasing means for erasing the memory cell in response to a predetermined potential; clock signal generating means for generating a first clock signal having a first frequency; and the clock signal. a second frequency connected to the generating means and having a second frequency lower than the first frequency;
clock signal or a third frequency lower than the second frequency.
clock signal selection means for selectively outputting one of the third clock signals having a frequency of; and a clock signal selection means connected to the clock signal selection means for selectively outputting a third clock signal having a frequency of . the clock signal selection means selectively outputs the second or third clock signal in response to the selection signal; and the memory cell erasing means receives the selection signal. An electrically programmable and erasable nonvolatile semiconductor memory device that erases the memory cell in response to a second or third clock signal.