JPH02158214A - Logic circuit device - Google Patents

Abstract

PURPOSE:To eliminate the wiring region occupying a wide area such as an LCA and to attain high density and high circuit integration by programming a data required for a readout string designation means, a gate circuit selection means and a write cell designation means in advance, and applying a desired logic circuit processing. CONSTITUTION:The circuit has constituents of a gate matrix 1 and a node data matrix 2. The gate matrix 1 is a 4 row and 4 column matrix comprising an AND gate circuit and a NAND gate circuit, and a node data matrix 2 is a RAM in which lots of memory cells each capable of writing and reading out of 1-bit information are formed as a matrix. When a combination circuit comprising gate circuits arranged in n-stage is formed, a data in response to the attained combination circuit is stored to the read string designation means, the gate circuit selection means and the write cell designation means. Thus, the wide area in the wiring region like a logic cell array(LCA) is not required and high density and high circuit integration are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit device in which combinational circuits and sequential circuits using gate circuits can be freely configured by a program.

[Conventional technology]

This type of logic circuit device (Programmable L
LogicDevlce; PLD) is a logic cell array (Logic Cell Array;
There is something called LCA (Ross H. Freeman; ``LCAJ Nikkei Electronics vol. 1.40L that bridges the gap between gate arrays and existing PLDs.
pp. 245-265, September 1986). This LCA
, programmable logic blocks CLB are arranged in a matrix, programmable input/output blocks IOB are arranged around it, and each logic block CL
Programmable interconnection is provided between the terminals B and B. And logical block CLB.

A desired logic circuit is obtained by appropriately programming the input/output block IOB and interconnections on the user side.

[Problem to be solved by the invention]

However, the wiring area of such an LCA occupies a considerable area, and there is a limit to high density and high integration. In addition, in most cases, only a small part of the large number of logic blocks CLB is used, resulting in a wasteful circuit configuration, resulting in gate arrays, ASICs (^pplic
atlon SpeclrlcInLegraLed
The price is high compared to C1rcuit).

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the logic circuit device of the present invention includes:
A node data matrix in which memory cells are arranged in a matrix, a gate matrix in which gate circuits that input data read from the node data matrix are arranged in a matrix, and transition states according to the recognized transition state. control means for outputting signals and read/write signals for the node data matrix; read column specifying means for specifying a memory cell column to be read in the node data matrix based on a transition state signal; and the read column specifying means. a means for selecting a gate circuit in the gate matrix according to a column designated by the node data matrix; A write cell designating means is provided for designating a write cell based on the generated signal.

[Effect]

For example, when attempting to achieve a combinational circuit using gate circuits arranged in n stages, data corresponding to the combinational circuit to be achieved is sent to the readout column designation means, gate circuit selection means, and write cell designation means. Memorize it in advance. When arbitrary data is input to the input terminal, the control means detects this and provides a transition state signal indicating that data has been input to the write cell designation means, and also provides a write signal to the node data matrix. As a result, the input data is written into the memory cell specified by the write cell specifying means. Thereafter, the read specifying means specifies the memory cell to which data has been written based on the state transition signal, and at the same time, the control means outputs a write signal to read data from the specified memory cell and input it to the gate matrix. At this time, the first of the combinational circuits to be achieved is
A gate circuit corresponding to the gate circuit group of the stage is selected by the gate circuit selection means. Therefore, the gate matrix outputs a signal equivalent to the output of the first stage gate circuit group of the desired combinational circuit. This output is returned to the node data matrix and written to the memory cell designated by the write cell designation means based on the transition state signal or a signal based thereon. The data written here is read out again and input into the gate matrix. At this time, the gate circuit selection means selects a gate circuit corresponding to the second stage gate circuit of the desired combinational circuit, and its output is returned to the node data matrix again. Thereafter, similar operations are repeated to obtain the output of the final stage.

Note that when trying to achieve a sequential circuit with a feedback loop, the control means monitors the state of the feedback loop and outputs a transition state signal according to the state, so it is possible to maintain the feedback loop in a stable state. You can get the final output.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing the internal configurations of a gate matrix 1 and a node data matrix 2, respectively, which are the constituent elements of this embodiment. It is.

The gate matrix 1 is a matrix of 4 rows and 4 columns composed of AND gate circuits and NAND gate circuits, and as shown in FIG. 2, the gate circuit arranged in the m-th row and n-th column is
> n and mm nm1.2 is a NAND gate circuit, and m < n and m = n-3, 4 is an AND gate circuit. Each gate circuit is powered by four people, and wiring data decoded by the decoder 3 is input to the first and second input terminals of each gate ON path.

Node data from the sense circuit 4.5 is input to the third and fourth input terminals of each gate circuit.

Note that the node data given from the sense circuit 4.5 is based on the output of the node data matrix 2 and always has the same content. Further, the wiring data decoded by the decoder 3 is programmed into the wiring data code matrix 16. The outputs of the gate circuits of the gate matrix 1 are grouped for each column and given to the latch circuit 6.

The node data matrix 2 is a random access memory (random access memory) in which a large number of memory cells capable of writing and reading 1-bit information are arranged in a matrix.
RAM). The data to be written to the node data matrix 2 is provided from the input buffer 7, and its addressing is based on the data scrambling code programmed into the data scrambling code matrix 8. Note that the decoder 9 decodes the data scramble code.

Reading of data from the node data matrix 2 is performed by a read signal from the control circuit 12, and designation of a memory cell to be read is performed based on an instruction microcode programmed in the instruction microcode memory 10. That is, the count value of the up/down counter 11 is determined by the instruction microcode, the column of the node data matrix 2 is specified by its output, and the node data is read from the memory cell of the specified column by the read signal of the control circuit 12. It will be done. The read data is applied to sense circuits 4 and 5.

Sense circuits 4 and 5 convert the signal level of data applied from node data matrix 2 to a level corresponding to gate matrix 1.

Control circuit 12 provides read and write signals to node data matrix 2 and appropriate instructions to instruction microcode memory 10.

Note that 13 is an input terminal, 14 is an output latch circuit having a buffer function, and 15 is an oscillator that provides drive timing. In addition, data scrambling code matrix 8
, instruction microcode memory 10 and wiring data code matrix 16 are
It is composed of a rewritable ROM such as EPROM.

Next, the operation of this embodiment will be explained in the case of a combinational circuit and in the case of a sequential circuit.

First, a case will be described in which the device of this embodiment is a combination circuit consisting of a NAND gate circuit 21, a NOR gate circuit 22, and an AND gate circuit 23 as shown in FIG. 4(A). First, a desired circuit is replaced with a circuit using only a NAND gate circuit, an AND gate circuit, and a NOT gate circuit (inverter). Noah gate circuit 2
2 can be decomposed into a combination circuit of two inverters 24 and 25 and a NAND gate circuit 26, as shown in the broken line area in FIG. Therefore, the circuit shown in FIG. 3B is substantially the same as the circuit shown in FIG. Note that data indicating the state of the input/output terminal of each gate is called node data, and data indicating the gate circuit to be selected is called wiring data. Also, the nth column of the node data matrix 2 is called address n,
In this example, addresses 1 to 4 are respectively shown in Figure 4 (
Corresponds to ■ to ■ in B).

FIG. 5 is a state transition table when the circuit shown in FIG. 4(B) is configured, and states of addresses 1 to 4 (AD1 to 4),
The output (latch) of the latch circuit 6, the state of the read/write signal (W/R) from the control circuit 12, and the address (AD) of interest at that time are shown.

Assume now that the node data from addresses 1 to 4 are as shown in step 0, and that rooolJ is input to the input terminal 13 from this state. Control circuit 12
detects this input change and outputs a transition state signal to the instruction microcode memory 10 indicating the change. The instruction microcode memory 10 outputs an instruction microcode signal based on the transition state signal to the up/down counter 11, and based on this signal, the up/down counter 11 sets its count value to "1". This count value is given to the data scrambling code matrix 8 as an addressing signal.

The data read from the data scramble code matrix 8 by this addressing is decoded by the decoder 9, and the write position in the first column of the node data matrix 2 is designated.

At this time, a write signal is applied to the node data matrix 2 from the control circuit 12, and rooolJ is written to the node data matrix 2. The above is the operation of step 1.

Note that the writing position specified by the data scramble code is specified by the wiring data code matrix 16.
It is determined according to the gate circuit selected in the first and second input terminals 27. of FIG.
28 manual data "00" is written in the 3rd row and 4th row of the 1st column, respectively, and the input data "01" of the 3rd and 4th input terminals 29.30 is written in the 1st row and 2nd row of the 1st column, respectively. It looks like this. Therefore, from the first row to the fourth row of the first column of the node data matrix 2, ro 10
0J is written.

In step 2, the data written to address 1 is r010.
0J is read out and applied to sense circuit 4.5. At this time, the wiring data hood matrix 16 is. 1 row 1 column, 2 rows 2 columns and 3 rows 4 according to the program content
Three NAND gate circuits in the column are selected. Selection of the NAND gate circuit in the 1st row and 1st column means the inverter 24,
The selection of 2 rows and 2 columns of NAND gate circuits means inverter 25. Further, the selection of the NAND gate circuits in the 3rd row and 4th column means the NAND gate circuit 21. That is, the outputs of the first, second, and third columns of the node data matrix 2 correspond to the outputs of the inverter 24, the inverter 25, and the NAND gate circuit 21, respectively, and are temporarily stored in the latch circuit 6 as rl 01J in this example. Ru. In addition, in the table of FIG. 5, the data contents are written in the order based on the node positions of the circuit diagram shown in FIG. The same is true.

In step 3, the data in the latch circuit 6 is written into the second column of the node data matrix 2 via the input buffer 7. At this time, in which row of the second column each data is written is determined based on instructions from the data scrambling code matrix 8, as in step 1. Here, data corresponding to the outputs of the inverters 24 and 25 are written in the first and second rows, respectively, and data corresponding to the output of the NAND gate circuit 21 is written in the third row. That is, rlolJ is written in order from the first row to the third row of the second column. As already mentioned, the state transition table in FIG. 5 is based on the node position in FIG. 4(B), so it is displayed as rllOJ.

In step 4, the data in the second column of node data matrix 2 is read out and applied to gate matrix 1 via sense circuit 4.5 as in step 2. At this time, based on the data from the wiring data code matrix 16, the NAND gate circuits in the 1st row and 2nd column and the AND gate circuits in the 3rd row and 3rd column are selected. 1 line 2
The NAND gate circuits in the columns correspond to the NAND gate circuits 26 in FIG. 4(B), and the AND gate circuits in the 3rd row and 3rd column mean a simple bus. Therefore, in this example, the second and third outputs of the latch circuit 6 become the outputs of the NAND gate circuits 26 and 21, respectively, and their value becomes "11".

In step 5 this value is fed back and written to the first and second rows of the third column of gate matrix 1. Then, in step 6, the third column of gate matrix 1 is read out and node data matrix 2 is read out.
given to. Here, AND gate circuits arranged in two rows and one column are selected by the wiring data code matrix 16, and the output of the first column is latched by the latch circuit 6.

In this example, it is "1".

This latch data is transferred to gate matrix 1 in step 7.
is written in the appropriate row of the fourth column of
This data is read out and applied to the output latch circuit 14. The output latch circuit 14 latches this as the final output.

This means that this combinational circuit has been achieved.

Next, the operation when a circuit having a feedback loop, that is, a sequential circuit is constructed using the apparatus of this embodiment will be described. FIG. 6 is an example of a sequential circuit, and NAND gate circuit 3
This is a flip-flop circuit constructed with 1.32. The operation to achieve this sequential circuit will be described below based on the state transition table shown in FIG. In addition, in the state transition table, ADI and AD2 are node data matrix 2.
The contents of addresses 1 and 2 are shown, and AD2' shows the latch data of the latch circuit 6. Also, MATCH
indicates a flag that is set in the control circuit 12. If the contents of the latch circuit 6 change when reading data at address 1, "1" is set, and if there is no change, "0" is set.
” stands.

Now, in the circuit of FIG. 6, if the initial state is that "1" is input to both input terminals 33 and 34 and output terminals 35 and 36 are rOj rlJ, then the steps of FIG. 1 represents a state equivalent to this initial state.

From this state, the input signal to the input terminal 33 in FIG.
The signal change equivalent to changing from ``1'' to ``0'' is human power 1.
3, the control circuit 12 detects this, puts the node data matrix 2 into the write state, and writes the memory contents of the first column of the node data matrix 2 to rl 10.
1J is rewritten to rololJ (step 2).

In step 3, the data in the first column of node data matrix 2 rewritten in step 2 is read out and applied to gate matrix 1 via sense circuit 4.5.

At this time, the wiring data code matrix 16 selects the NAND gate circuits in the 1st row and 2nd column and the 3rd row and 4th column of the gate matrix 1, and these outputs are rlJ, respectively.
rlJ and is latched by the latch circuit 6. By this read operation, the latch contents of the latch circuit 6 become "0", "
1'' to rlJ rlJ, this change is detected by the control circuit 12 and the MATCH flag is set to ``1''.
stands. The MATCH flag "1" means that the feedback loop of the sequential circuit is activated, and the data in the latch circuit 6 is not only written to address 2 according to the normal steps, but also written to address 1. It works like this. The operation of writing to address 2 is step 4, and the operation of writing to address 1 is step 5. Note that in step 5, the output of the NAND gate circuit in the 3rd row and 4th column is written in the second row of address 1, and the output of the NAND gate circuit in the 1st row and 2nd column is written in the third row of address 1. At this time, the first and fourth lines of address 1 are not rewritten. The data scramble code matrix 8 specifies this writing position.

Next, in step 6, the data at address 1 written in step 5 is read. The read data is given to the NAND gate circuits in the 1st row and 2nd column and the 3rd row and 4th column as in step 3, and the output is sent to the latch circuit 6.
latched to. At this time, since the latched contents of the latch circuit 6 have changed from rlJ rlJ to rlJ rOJ, the MATCH flag "1" is set in the control circuit 12. Therefore, the feedback loop is activated again, and the latch data of the latch circuit 6 is written to addresses 1 and 2 of the gate matrix 1 in the same manner as step 4.5 (step 7.8).

Next, address 1 of node data matrix 2 again
The data at address 1 is read out and applied to gate matrix 1 via sense circuit 4.5 (step 9). At this time, the data at address 1 is rollJ, and the output of gate matrix 1 is rlJ rOJ. This output is given to the latch circuit 6, but since it is equal to the data latched in the latch circuit 6, the control circuit 1
2, the MATCH flag is set to "0". This indicates that the feedback loop has stabilized, in other words that data processing is complete. therefore,
The result can be obtained by reading the data at address 2 at this time and latching its contents in the output latch circuit 14.

In the above embodiment, the MATCH flag is set based on the change in the latch data in the latch circuit 6, but the MATCH flag is set based on the result of comparing the latch data with the node data stored at the address corresponding to this latch data. M.A.T.
A CH flag may be set.

〔Effect of the invention〕

As explained above, according to the logic circuit device of the present invention,
Desired logic circuit processing can be performed simply by preprogramming necessary data in the read column designation means, gate circuit selection means, and write cell designation means. Moreover, L.C.A.
There is no wiring area that occupies a large area like in
High integration becomes possible. In addition, since the gate matrix is configured to be used repeatedly when executing one logic process, gate circuits are used efficiently, and there is less wastage in terms of area and price, and the cost is low. becomes.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a detailed circuit diagram of a gate matrix, Fig. 3 is a detailed circuit diagram of a node data matrix, and Fig. 4 is a detailed circuit diagram of the present embodiment. A circuit diagram showing an example of the combinational circuit to be achieved, FIG. 5 is a state transition table showing its operation, and FIG.
FIG. 7, a circuit diagram showing an example of a sequential circuit to be achieved in this embodiment, is a state transition table showing its operation. DESCRIPTION OF SYMBOLS 1... Gate matrix, 2... Node data matrix, 3... Decoder, 4.5... Sense circuit, 6... Latch circuit, 7... Input buffer, 8...
...Data scramble code matrix, 9...
Decoder, 10... Instruction microcode memory, 11... Up/down counter, 12...
- Control circuit, 13... Input, 14... Output latch circuit, 15... Oscillator, 16... Wiring data code matrix. Figure 4

Claims (1)

[Claims] 1. Recognition of a node data matrix in which memory cells are arranged in a matrix, and a gate matrix in which gate circuits for inputting data read from the node data matrix are arranged in a matrix. control means for outputting a transition state signal and a read/write signal for the node data matrix according to the transition state that has been detected; and a read column designation that designates a memory cell column to be read in the node data matrix based on the transition state signal. means for selecting a gate circuit in the gate matrix according to the column specified by the read column specifying means; and means for selecting a gate circuit in the gate matrix according to the column specified by the read column specifying means; A logic circuit device comprising write cell designating means for designating a write cell based on a state signal or a signal created based on this signal. 2. In the gate matrix, the gate circuits of m rows and n columns satisfying m<n are composed of NAND gate circuits, the gate circuits of m rows and n columns satisfying m>n are composed of AND gate circuits, and m=n 2. The logic circuit device according to claim 1, wherein the gate circuit satisfying the following is comprised of a NAND gate circuit and an AND gate circuit. 3. The logic circuit device according to claim 1, wherein the control means outputs a transition state signal based on a change in the output of the gate matrix based on data read from the node data matrix.