JPH02156536A - Film formation, sputtering apparatus used therefor and manufacture of highly integrated semiconductor device using same - Google Patents

Abstract

PURPOSE:To enable a uniform metallic film to be formed on the whole surface of a sample by providing an erosion region produced by double magnetic poles on a target while creating a magnetic filed controllable such that magnetic lines of force from the target side act on the whole surface of the sample. CONSTITUTION:An erosion region is produced on a target 6 by dual magnetic poles 7 consisting of a pair of magnetic pole sources having different polarities and both controllable in magnetic intensity generated thereby, while a magnetic field is created by magnetic poles 11A and 11B, the magnetic filed being controllable such that magnetic lines of force from the target side act on the whole surface of a sample 10. Since the direction along which atoms fly to the surface of the sample 10 can be varied by controlling the erosion region, a metal film can be deposited in a reliable manner particularly in through holes. Further, local difference in thickness of the metal film can be prevented by creating the magnetic field controllable such that lines of magnetic force from the target side act on the whole surface of the sample 10. In this manner, the metallic film can be formed on the surface of the sample 10 with uniform thickness and with high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique suitable for improving coverage characteristics and forming a uniform film thickness over the entire surface of a sample in a sputtering apparatus, particularly a bias sputtering apparatus.

[Conventional technology]

An example of this type of technology described is “Ultra L
SI Manufacturing/Testing Equipment Guidebook” P111-P117
There is.

As described in the above-mentioned literature, in a semiconductor wafer processing process, a sputtering apparatus is generally used as a method for forming a metal thin film on a wafer surface.

In this type of sputtering equipment, an AA gold alloy target is set as the cathode electrode, and argon gas ions generated by plasma discharge between this and the anode electrode are made to collide with the target, and the kinetic energy of the ions due to this collision is In this method, metal atoms emitted from a target are made to fly and adhere to the masked wafer surface.

Among such sputtering apparatuses, a so-called planar magnetron type sputtering apparatus is commonly used, in which a magnetic field is formed perpendicular to an electric field in order to efficiently collide ions with a target.

[Problem to be solved by the invention]

As a sputtering method using such a magnetic field, there is a double magnetic pole method in which a magnetic pole source is placed on the cathode side as shown in Figure 9, and a double magnetic pole method in which a magnetic pole source is placed on both the cathode side and anode side as shown in Figure 10. A cusp magnetic pole system has been proposed.

Both types will be explained in more detail below.

Figure 11 shows the planar configuration of the magnetic pole source (magnet coil) used in the above-mentioned double magnetic pole system, and Figure 12 (a
) to (d) respectively show changes in the erosion region (region blocked by magnetic lines of force) due to the way the magnetic poles are applied.

As shown in FIG. 11, the magnet coil 81 is composed of an inner annular magnet (81A) and an outer annular magnet (81B), which are connected to a target 82 of He-1 alloy or the like.
It is arranged inside the cathode electrode 83 that holds the.

In such an arrangement of the magnet coil 81, the erosion region also changes as shown in FIGS. 12 and 12) by controlling the strength of the magnetic force generated in the inner circumferential annular magnet 81A and the outer circumferential annular magnet 81B. Due to such changes in the erosion area, the sputtered portion of the target 82 also changes.

In the double magnetic pole method, by controlling the position of this erosion region, it is possible to control the direction of the metal atoms flying toward the wiring formation portion of the wafer 84 on the anode electrode 85, thereby preventing the formation of a metal film in the wiring formation portion. This has the advantage that the condition can be made uniform.

However, when this is captured on the entire surface of the wafer 84, an erosion region is formed near the periphery of the target 820, so that the wiring layer near the periphery of the wafer 84 and the wafer 82
There was variation in the wiring film thickness with respect to the central wiring layer of wafer 84, making it difficult to form highly reliable wiring over the entire surface of the wafer 84.

Regarding this point, according to the cusp electrode method, as shown in FIG. 10, magnet coils 86A, 86B, and 86C are arranged within the cathode electrode 83, between the wafer 84 and the target 82, and at the anode electrode 8503, Since the erosion area on the target 82 is designed to be uniform, there is an advantage that a uniform wiring film thickness can be ensured over the entire surface of the wafer 84.

By the way, as the degree of integration in semiconductor devices increases, the diameter of the contact hole between the silicon (Si) substrate and the aluminum (Aβ) wiring and the through hole between the A1 wiring become smaller, resulting in a phenomenon in which the so-called aspect ratio increases. There is. This will be explained using FIG. 13.

In the figure, 91 indicates a semiconductor element substrate;
Reference numeral 2 indicates a through hole formed on the surface thereof, and reference numeral 93 indicates an AA wiring layer. On the right side of the figure, the ratio between the depth h of the through hole 92 and the through hole diameter l is the aspect ratio. As this aspect ratio gradually approaches 1 as semiconductor devices become more integrated, the step coverage characteristic, which indicates interconnect reliability, generally tends to decrease.

In the same figure, the step coverage characteristic is t/TX1
It is shown as 00(-%). That is, when the step coverage characteristic becomes a small value, the wiring resistance in the Al wiring layer 93 increases and disconnection due to electromigration is likely to occur.

In the sputtering apparatus using the cusp magnetic pole method, sufficient consideration has not been given to deterioration of step coverage characteristics due to this high aspect ratio, and metal atoms are difficult to enter into the narrowed through holes 92.

In order to improve this step coverage characteristic, a technique has been proposed in which the inner wall surface of the through hole is made into a tapered shape to promote the adhesion of metal atoms. is also becoming difficult.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technology that improves step coverage characteristics in sputtering processing and enables formation of a uniform deposited film over the entire surface of a sample. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a target is placed on one side of a pair of electrodes facing each other in a fluid atmosphere, and a sample to which a predetermined film is to be deposited is placed on the other side, and a high voltage is applied between the two electrodes to generate plasma discharge. ion is used to generate ions, and when these ions collide with the target, specific atoms are released, and when a specific film is formed by depositing the specific atoms on the sample surface, ions with different polarities are generated on the target. An erosion region is formed by a double magnetic pole made up of a pair of magnetic pole sources whose intensity of magnetic force can be controlled, and a controllable magnetic field is formed so that the lines of magnetic force from the target side act on the entire surface of the sample. This is how it was done.

[Effect]

According to the above-mentioned means, ′! In J1, by forming an erosion region with double magnetic poles and controlling this erosion region, the direction of flying atoms to the sample surface, especially into the through hole, can be varied, so it is particularly effective for depositing a metal film inside the through hole. can be done reliably.

Second, by forming a controllable magnetic field such that lines of magnetic force from the target side act on the entire surface of the sample, local variations in the thickness of the film formed on the sample surface can be prevented.

The first and second effects described above make it possible to form a uniform and highly reliable film on the sample surface.

In addition, by applying the above to the formation of multilayer aluminum wiring on a wafer in the manufacturing process of semiconductor devices,
It becomes possible to realize a highly integrated semiconductor device.

〔Example〕

FIG. 1 is a schematic diagram showing the configuration of a sputtering apparatus according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the state of sputtering processing according to this embodiment, and FIGS. An explanatory diagram showing the flying direction of metal atoms and the formation state of metal wiring due to fluctuations, FIG. 6 is an explanatory diagram showing the directionality of magnetic lines of force in the processing chamber according to this embodiment, and FIG. 7 is an explanatory diagram showing the direction of magnetic lines formed through this embodiment. FIG. 8 is an explanatory diagram showing the multilayer wiring structure of a semiconductor element, and FIG. 8 is an explanatory diagram showing the structure of a semiconductor device obtained by this example.

As shown in FIG. 1, the sputtering apparatus 1 of this embodiment has a processing chamber 3 spatially connected to a negative pressure generating means 2 such as an exhaust pump, and the processing chamber 3 is filled with argon gas. A fluid supply port 4 for supplying a processing fluid Gs such as the like is provided.

In the figure, a cathode electrode 5 constituting a stage is formed in the lower part of the processing chamber 3, and a plate-shaped A1 alloy serving as a target 6 is disposed on the cathode electrode 5. A magnet coil 7 having a double magnetic pole structure is arranged inside the cathode electrode 5 . Such a magnet coil 7 has a double structure similar to that shown in FIG. 11, with an inner annular magnet 7Δ and an outer annular magnet 7Δ
It consists of a pair with 7B. In this example, both of these magnets? A and 7B are cathode electrodes 5
The inner circumferential annular magnet) 7A is N against the upper target 5.
On the pole side, the outer peripheral annular magnet 7B is arranged on the S pole side. Therefore, the magnetic field on the surface of the target 6 is formed in a loop from the N pole of the inner annular magnet 7A to the S pole of the outer annular magnet 7B, and the ions of the processing fluid Gs are confined within this magnetic field. , it is possible to concentrate high-density plasma.

In the processing chamber 3, an anode electrode 8 is vertically installed near the ceiling above the cathode electrode 5, and a wafer 10 as a sample is held on the electrode surface with its circuit forming surface facing downward. ing.

The anode electrode 8 is provided with a magnet coil 11A as a control magnetic pole source. This magnet coil IIA is arranged with its S pole facing the wafer 10 side. Further, directly below the anode electrode 8, a magnet coil IIB having approximately the same diameter as the outer circumferential annular magnet 7B described above is arranged.

In the apparatus configuration as described above, when the pressure inside the processing chamber 3 is reduced to about IQ-''Pa by the negative pressure generating means 2, the processing fluid Gs containing argon gas as a main component is supplied from the fluid supply port 4, and 3 is filled with the atmosphere of this processing fluid Gs.

Subsequently, the wafer 10 on the anode electrode 5 is heated to about 200 to 300°C using a heating source such as a heater (not shown).
Fluid components are removed from the surface of the wafer 10.

Next, a predetermined voltage is applied to each of the magnet coils 7A, 7B, and 11A11B to form a magnetic field inside the processing chamber 3.

At this time, the effect of the magnetic field formed by the inner circumferential and outer circumferential annular magnets 7A and 7B in the cathode electrode 5 is
This will be explained using FIGS.

In this embodiment, each magnet in the cathode electrode 5.

Depending on the strength of the magnetic force generated by the coils 7A and 7B,
The flying direction of the metal atoms 9 (A1 atoms) sputtered from the target 6 is controlled.

That is, the flying direction of the gold atoms 9 relative to the wafer 10 depends on the strength of the north and south poles of the magnet coils 7A and 7B, as shown in FIG. 3(a), FIG. 4(a),
As shown in FIG. 5(a), they are different. If the flying direction of the metal atoms 9 is constant,
As a result, the film thickness of the AN wiring 12 formed also deviates, and as shown in FIG. 3(b), FIG. 4(b), and FIG. 5, etc.), wiring defects ( (points indicated by X in the figure).

Regarding this point, according to this embodiment, a pair of magnet coils? Since the strength of the magnetic force generated by A and 7B is changed over time, it is possible to form the Aβ wiring 12 with a uniform thickness in the recess or through hole shown in each of the above figures.

On the other hand, the uniformity of the film thickness over the entire surface of the wafer 10 is ensured by the magnet coils IIA and IIB as control magnetic pole sources arranged on the anode electrode 8 side.

That is, the directionality of the magnetic lines of force formed by the respective magnet coils IIA and IIB is controlled so that they act approximately uniformly on the entire surface of the wafer IO placed on the anode electrode 8, as shown in FIG. has been done. Note that it is also possible to control the magnetic force of the magnet coils 11A and IIB on the anode electrode 8 side.

Subsequently, -400 to -500V is applied to the cathode electrode 5.
When a relatively high voltage is applied, plasma discharge is generated between the cathode electrode 5 and the anode electrode 8. The processing fluid Gs is ionized by this plasma discharge, and the ions collide with the target 6. At this time, the ions are in the magnet coil 7A.

Since the plasma is confined in the magnetic field on the target 6 formed by the target 7B, plasma is concentrated in this region at high density, and sputtering efficiency can be increased. Due to the collision of the ions, metal atoms 9 of A1, which are constituent atoms of the target 6, are ejected from the target 6. The metal atoms 9 emitted in this way are scattered into the processing chamber 3 and fly to the surface of the wafer 100 by the action of magnetic lines of force induced by the magnet coils 11A and IIB, which function as control magnetic pole sources on the anode electrode 8 side. to adhere to.

At this time, with respect to the surface of the wafer 10, -50 to -20
By applying a bias voltage of about 0 V (so-called bias sputtering), it is possible to more efficiently deposit the metal atoms 9 into the recesses or through holes.

Note that in normal cases, the surface of the wafer 10 on the anode electrode 8 is covered with a mask (not shown) that has openings only in the wiring forming portion, and the AA wiring 12 is covered in other areas on the wafer 10.
The structure is such that it is not formed.

FIG. 7 is a sectional view of a main part of a bipolar LSI manufactured according to this embodiment.

As shown in the figure, in the bipolar LSI of this embodiment, for example, an n+ type buried layer 42 is provided on the surface of a semiconductor chip (semiconductor substrate) 41 made of, for example, n-type silicon. An epitaxial layer 43 of n-type silicon is provided. A field insulating film 44, such as a Si film, is provided at a predetermined portion of the epitaxial layer 43, and these provide isolation between each element and each characteristic portion within the element. Below the field insulating film 44, for example, p
A type channel stopper region 45 is provided.

Further, in the portion of the epitaxial layer 43 surrounded by the field insulating film 44, a p-type intrinsic base region 46 and a p-type graft base region 47, for example, are provided. An n-type emitter region 45 is provided in the intrinsic pace region 46 . The emitter region 45, the intrinsic base region 46, and the collector region composed of the epitaxial layer 43 and the buried layer 42 below the intrinsic base region 46 constitute an npn type bipolar transistor.

Further, in the figure, reference numeral 49 is an h-type collector extraction region connected to the buried layer 42. Reference numeral 50 denotes an insulating film such as a 5102 film which is connected to the field insulating film 44, and this insulating film 50 has the following regions: Through hole 508~
50c is drilled. This through hole 508~5
A base extraction electrode 51 made of a polycrystalline silicon film is connected to the graft base region 47 through 0C, and a polycrystalline silicon emitter electrode 52 is provided on the emitter region 48 through a through hole 41b. Note that the code 53.54 is, for example, S10
．． It is an insulating film such as a film.

The above-described sputtering technique can also be used to form the base extraction electrode 51.

Reference numerals 558 to 55c indicate first-layer wiring made of an Af film. Among these, wiring 55a is connected to the base extraction electrode 51 through a through hole 54a provided in the insulating film 54, and wiring 55b is connected to the base lead electrode 51 through the through hole 54b. The wiring 55C is connected to the crystal silicon emitter electrode 52 through the through hole 5.
4C and the collector extraction region 49 through the through hole 50c. Also, code 5
6 is a SiN film, a spin-on glass (SOG) film, and a Si
This is an interlayer insulating film consisting of an O2 film, and the above films constituting this are formed by plasma CVD. A second layer wiring 57 made of, for example, an A1 film is provided on the upper layer of this interlayer insulating film 56.
7 is a through hole 56 opened in the interlayer insulating film 56.
It is connected to the wiring 55c through a. Note that this through hole 56a has a stepped shape, and by using this shape and the above-mentioned sputtering technique, the step coverage characteristics of the wiring 57 in the through hole 56a are improved. Reference numeral 58 is an interlayer insulating film similar to the interlayer insulating film 56, and the upper layer of the interlayer insulating film 58 includes:
Third layer wirings 59a to 59C made of Aβ film are provided. Among these, the wiring 59a is connected to the interlayer insulating film 5.
The wiring 5 is connected through the through hole 58a opened in 8.
It has a structure connected to 7. Reference numeral 60 denotes an interlayer insulating film similar to the interlayer insulating films 56 and 58, and a fourth layer wiring 61 made of A1 film is provided on the upper layer of the interlayer insulating film 60.
a to 61c are arranged.

These wirings 613 to 61c are configured to have a larger layer thickness than the lower layer wirings described above, and the wirings 61a to 61C can supply a large current. For example, in this embodiment, the layer thickness is 2 μm, and the groove width between each wiring 6, 11, 61b, 61c is 2 μm, so the aspect ratio of this groove (groove depth/groove width) is 1, which is a relatively large value.

Reference numeral 62 is an insulating film for surface flattening, such as a 5102 film.
It is formed by a combination of D and sputter etching. Through this insulating film 62, the wiring 61a,
Since the groove between 61b and 61c is buried, the insulating film 6
The surface of No. 2 is almost flat. Note that the insulating film 62 is made of, for example, PSG (Phosph) formed by a combination of normal pressure CVD and sputter etching.
o-3ilicate Glass) membrane, B S G
(Boro-3ilicate Glass) membrane, B
P S (Boro-Phospho-3ilica
It is also possible to use silicate glass films such as teGlasS) films. An SiN film 63 formed by plasma CVD is provided on the upper layer of this insulating film 62. Here, the surface of the insulating film 62 is connected to the wiring 61.
Since the grooves between a to 61C are also flattened, the surface of this SiN film 63 is also flattened. For this reason,
The thickness and quality of the SiN film 63 are also relatively uniform. Therefore, the uppermost protective film 65, which will be described later, is also in a relatively flat state, resulting in a highly moisture-resistant semiconductor chip structure that is difficult to infiltrate with moisture. Therefore, LSI
It is now possible to use a non-hermetically sealed package as the package.

The SiO2 film 64 formed on the upper layer of the SiN film 63 is formed by plasma CVD method, and both films 6
3 and 64 constitute a protective film 65 for chip protection. In this case, the SiO□ film 64 ensures the adhesion of the chromium (Cr) film 66, which will be described later, to the protective film 65, and also prevents the SiN film 63 from being etched during dry etching of the Cr film 66. It also functions as a protective mask.

A through hole 65a is formed in a part of the protective film 65, and the wiring 6 is passed through the through hole 65a.
A Cr film 66 is formed on 1b. Furthermore, the C
On the upper layer of the r film 66, solder bumps 68 made of a lead (Pb)-Sn alloy are provided with a copper (Cu)-tin (Sn) based intermetallic compound layer 67 as a pedestal.

FIG. 8 is a sectional view showing a pin grid array (PGA) type package in which the bipolar LSI shown in FIG. 7 is sealed.

As shown in the figure, in the PGAI package,
For example, a semiconductor chip 41 is connected to a chip carrier 69 made of mullite (3,1203.2SiO3) using the solder bumps 68 described above. Further, a cap 70 made of silicon carbide (SiC) is placed above the semiconductor chip 41 with a brazing material 71 made of solder interposed therebetween. It has a structure in which the semiconductor chip 41 is sealed by being filled with resin 72. The above cap 70
is directly bonded to the back surface of the semiconductor chip 41 (the side on which no elements are formed) by the brazing material 71, so that the structure allows for effective heat dissipation from the semiconductor chip 41 to the cap 70. It has become. Incidentally, when such a package is mounted on a module substrate (not shown) or the like, a structure may be provided in which a heat dissipation fin or the like is further provided on the upper surface of the cap 70. In the figure, the input/output bins indicated by the reference numeral 73 protruding from the bottom surface of the chip carrier 69 are connected to the solder bumps 6 by multilayer wiring (not shown) formed inside the chip carrier 69.
8 and is electrically connected.

Therefore, the semiconductor chip 41 has the input/output pin 7
The structure allows for human output of drive power and signals through 3.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, although the control of magnetic lines of force has been described using a magnet coil, the present invention is not limited to this, and other magnetic force control means may be used.

In the above explanation, the invention made by the present inventor was mainly applied to the field of application, which is a spackle device for forming so-called Af wiring, but the invention is not limited to this, and the present invention is not limited to this. It can also be applied to sputtering equipment used for forming insulating films.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, according to the present invention, it is possible to form a uniform and highly reliable metal film on the surface of a sample.

Moreover, the above makes it possible to realize a highly integrated semiconductor device.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing the configuration of a sputtering apparatus according to an embodiment of the present invention, Fig. 2 is an explanatory diagram showing the state of sputtering processing according to the above embodiment, and Figs. An explanatory diagram showing the flying direction of metal atoms and the formation state of metal wiring due to fluctuations. FIG. 6 is an explanatory diagram showing the directionality of magnetic lines of force in the processing chamber according to the above embodiment. FIG. 7 is an explanatory diagram showing the direction of magnetic lines formed through the above embodiment. FIG. 8 is an explanatory diagram showing the structure of a semiconductor device obtained by the above embodiment; FIG. 9 is an explanatory diagram showing the double magnetic pole system in the prior art; FIG. 10 11 is an explanatory diagram showing the cusp magnetic pole method, FIG. 11 is a plan view showing the configuration of the magnetic pole source (magnet coil) used in the double magnetic pole method, and FIGS. 12 (a) to (d)
) is an explanatory diagram showing changes in the erosion region (occluded region by magnetic lines of force) in accordance with the manner in which the magnetic poles are applied in the magnetic pole source, and FIG. X3 is a diagram for explaining the aspect ratio and step coverage characteristics. 1... Sputtering device, 2... Negative pressure generating means, 3...
・Processing chamber, 4... Fluid supply port, 5... Cathode electrode, 6... Target, 7... Magnet coil, 7
A...Inner circumference annular magnet, 7B...Outer circumference annular magnet, 8...Anode electrode, 9...Metal atom, 1
0... Ueno\11A, IIB... Magnet coil, 12... Al wiring, 41... Semiconductor chip (semiconductor substrate), 42... Buried layer, 43... Epitaxial layer, 44...・Field insulating film, 45...
Channel stopper region, 46... Intrinsic base region, 4
7... Graft base region, 48... Emitter region, 49... Collector extraction region, 50a to 50C.
... Through hole, 51 ... Base extraction electrode, 52
...Polycrystalline silicon emitter electrode, 53.54...
Insulating film, 553~55C"' wiring (first layer), 56.
...Interlayer insulating film, 57... Wiring (second layer), 58.
... Interlayer insulating film, 59a to 59c... Wiring (third layer), 60... Interlayer insulating film, 61a to 61c... Wiring (fourth layer), 62... Insulating film, 63 ...SiN film, 64...S102 film, 65...protective film, 65a
...Through hole, 66...Chromium (Cr) film, 6
7... Intermetallic compound layer, 68... Solder bump, 69
...Chip carrier, 70...Cap, 71...
・Brazing metal, 72... Resin, 73... Input/output pin,
81... Magnet coil, 81A... Inner circumference annular magnet 7), 81B... Outer circumference annular magnet, 82...
- Target, 83... Cathode electrode, 84... Wafer, 85... Anode electrode, 86A, 86B, 86
C... Magnet coil, 91... Semiconductor element substrate, 92... Through hole, 93... Aβ distribution mFj,
GS...Processing fluid. Agent Patent Attorney Dai Kazu Tsutsui Figure 1 7B = Outer circumferential annular magnet Figure ■ Figure Figure 2

Claims (1)

[Claims] 1. With a target placed on one side of a pair of electrodes facing each other in a fluid atmosphere and a sample to be coated with a prescribed film placed on the other side, a high voltage is applied between the two electrodes. When forming a predetermined film by depositing the predetermined atoms on the sample surface, the predetermined atoms are emitted by the collision of the ions with the target, and the predetermined atoms are deposited on the sample surface. At the same time, an erosion region is formed by a double magnetic pole consisting of a pair of magnetic pole sources with different polarities and the strength of the generated magnetic force can be controlled, and the magnetic field lines from the target side are controlled so that they act on the entire surface of the sample. A film forming method characterized by forming a magnetic field. 2. The above erosion region is formed by arranging a pair of annular magnet coils with different polarities, and the above erosion region can be changed by controlling the voltage applied to each magnet coil. let me,
2. The film forming method according to claim 1, wherein the direction in which the predetermined atoms fly toward the sample surface can be controlled. 3. The film forming method according to claim 1, wherein a bias voltage is applied to the surface of the sample when applying the high voltage to both of the electrodes. 4. The above sample is a wafer made of silicon semiconductor,
2. The film forming method according to claim 1, wherein the predetermined film deposited on the wafer is an aluminum wiring. 5. In a processing chamber that maintains a negative pressure state, a pair of electrodes face each other at a predetermined interval, a target placed on one of the electrodes, a sample placed on the other electrode, and one A pair of erosion magnetic pole sources are placed on the electrode side and have mutually different polarities and can control the strength of the generated magnetic force, and a pair of erosion magnetic pole sources are placed on the other electrode side and control the passage position on the sample surface of the lines of magnetic force from the erosion magnetic pole source. A sputtering device consisting of a controlled magnetic pole source. 6. The sputtering apparatus according to claim 5, wherein the erosion magnetic pole source and the control magnetic pole source are magnetic coils whose magnetic force can be controlled by varying the strength of applied voltage. 7. A target made of aluminum alloy is placed on one side of a pair of electrodes facing each other in an argon gas atmosphere, and a wafer is placed on the other side, and a high voltage is applied between the two electrodes to generate plasma discharge. The argon gas ions are used to generate argon gas ions, and when the argon gas ions collide with the target, aluminum atoms are released, and when the aluminum atoms are deposited in the wiring area and through holes on the wafer, two Forming an erosion region generated by a heavy magnetic pole and forming a controllable magnetic field so that the magnetic lines of force from the target side act on the entire surface of the wafer to form through-hole wiring and aluminum wiring on the wafer, A method for manufacturing a highly integrated semiconductor device, which comprises forming a multilayer wiring structure on a wafer by repeating these processes. 8. The highly integrated semiconductor device according to claim 7, wherein when applying the high voltage, a bias voltage is applied to the surface of the wafer to accelerate the induction of aluminum atoms into the through holes. manufacturing method.