JPH0215486A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of false data caused by a mismatching with an equalizing signal by receiving the output of a differential amplifier with a differential type buffer circuit and driving an output buffer circuit. CONSTITUTION:A differential amplifying circuit 23 inputs output data (c) and the inverse of (c) and a data equalizing signal (b) from a differential amplifying circuit 1, amplifies them, and outputs data (d) to a data bus 2. While the threshold of a NOT circuit 21 to input the data (d) is set higher than an intermediate level, the threshold of a NOT circuit 22 to also input the data (d) is set lower than the intermediate level. Thus, an output buffer never operates until the output (d) exceeds either the threshold of the circuit 21 or that of the circuit 22, and data (g) are made into a high impedance state. Consequently, even when data (a) and the inverse of (a) from a memory cell are inputted after the data equalizing signal is turned off, only time up to a point where a buffer 23 starts its operation changes, and the output data never become the false data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that does not output false data when outputting data.

[Conventional technology]

FIG. 5 shows a diagram of the output system of a conventional semiconductor memory device. In the same figure, 11) is a differential amplifier circuit which inputs the data +a+, +a+ (!: nib-equalization signal fbl) output from the memory cell. (241 is the output data (0) from the differential amplifier circuit +11). : is an input, and outputs data +dl, which is an inversion of data to+, to the data bus 121. ω is an N-channel MO8 transistor for equalizing data to+ and data+ (11?).

- is a NOT circuit which inputs the data Jdl on data bus) 21, and inputs the inverted data telif of data ldl to the gate of all P-channel MO8) transistors 11υ and N-channel MO8) transistors (121). The terminal is a data output terminal for outputting output data tg). Also, C(υ is NOT circuit 24
1. Bay, forehead and N-channel MO8) transistor Aiwo-containing pre-output buffer, (to) P-channel MO8)
Langistaro 11t N channel MO8) Langista u2
It is a covered sofa including 1 ton.

The operation of the circuit of the output system of the conventional semiconductor memory device configured as described above will be explained with reference to the drawings. FIG. 6 is a timing chart when the timing of each 1g signal in FIG. 5 is normal, and FIG. 7 is a timing chart when there is a mismatch between the readout from the memory cell and the equalization signal in FIG. 5.

When the semiconductor memory device enters the read state, data tJLl t″iL1 is output from the memory cell. Before the data ta+ and G+ are input to the differential amplifier circuit Il+, the data equalization signal 1b+ is input to the differential amplifier circuit II+.
As shown in FIG. 6, the level of data +01 is equalized to the intermediate level, and at the same time, the N-channel MO! 9) The transistor L is turned on and the data IDl becomes an intermediate level. When the data equalization signal 1bl is input to the differential amplifier circuit..., the data lal, t
When al is input, the data equalize signal fbl becomes 0.
' Immediately after FF, the level of data (0) begins to change from the intermediate level. At the same time, the N-channel Mas transistor μs is turned off, and the level of data +41 also begins to change from the intermediate level. After that, Cheetah+a+y>z
s t tv N OT times FIII2e% 271 is input, and data tel, ff+ are output. This data
+, (f) levels, the O of P-channel MOS transistor αυ and N-channel MO8) transistor 021 is
N.OF'F is determined, and finally the output data igl is outputted to the data output terminal HK.

However, as shown in FIG.
Data fal from memory cell after b+ turns OFF
, tal are output, there is a delay in changing the level of data +O1, and finally the output data 1g1 becomes normal data after a period t.

During the period t, the output data (&; is false data).

[Problem to be solved by the invention]

What is the output system circuit of a conventional semiconductor memory device?

Since the output of the differential amplifier circuit is configured to receive the output of the differential amplifier circuit with a single signal input output buffer circuit and drive the output buffer circuit, if the reading from the memory cell is delayed and a timing mismatch with the equalization signal occurs. , there was a problem with the generation of false data, and countermeasures were an issue.

This invention was made in order to solve the above-mentioned problems, and its purpose is to obtain a semiconductor memory device that does not generate false data even if a timing mismatch with an equalization signal occurs due to a delay in reading from a memory cell. That is.

[Means to solve the problem]

The output system circuit of the semiconductor memory device according to the VC of the present invention is configured so that the output of the differential amplifier circuit is received by a multi-signal input pre-output buffer circuit to drive the output buffer circuit.

[Effect]

The multi-signal input gray output buffer circuit of the present invention outputs a signal that does not operate the output buffer circuit when a timing mismatch with the equalization signal occurs due to a delay in reading from the memory cell. Prevent this from occurring.

〔Example〕

An embodiment j of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an output system of a semiconductor memory device according to an example of the present invention. In this figure, the same reference numerals as in FIG. 5 indicate the same parts, and the differences from the conventional output system circuit diagram are shown below. The difference amplifier circuit 1]
This is a differential amplifier circuit that receives output data 10i, lδ) from the 10i, lδ) and a data equalization signal tbl, and outputs the amplified data ldl to the data bus (21).

FIG. 4 shows an example of circuit stealing of the differential amplifier circuit n. 2B
, t22H data bus (data on 21) is input to the T circuit.

The threshold voltage v1 of the NOT circuit 1211 is set higher than the intermediate level, as shown in FIG. N
The threshold voltage v2 of the OTtgl path (to) is set lower than the intermediate level, as shown in FIG.

Next, the operation of the above e-harm example will be explained. When the semiconductor memory device enters a read state, data +a+ and tal are output from the memory cells. data + aa,
Before Tit is input to the differential amplifier circuit 111, the data equalize signal 1br is input to the differential amplifier circuit 111, and as shown in FIG. 2, the level of the data loi, +01 is equalized to an intermediate level. At the same time, the data equalization signal fb+ is input to the differential amplifier circuit 2, and the data l
The level of dl is also at an intermediate level.

When the data equalize signal 1b+ is input to the differential amplifier circuit and the data lal and tELl are input, the data equalize signal fbl is turned off and immediately the level of the data lot and 101 changes from the intermediate level. start. At the same time, the data ldl amplified by the differential amplifier circuit DI also begins to change from the intermediate level. after that.

Data 1 (11 is input to two NOT times 91υ, (company) and data tel, +f+ is output. Data (
The level of el is 1H1 until the level of data +dl reaches the threshold voltage v1, and becomes 1L1 when the level of data ldl exceeds the threshold voltage v1. The level of data (fl is 1L'' when the level of data tal is higher than the threshold voltage v2,
(When the level of 11 is lower than the threshold voltage v2, 1
It becomes H1. data (ei level is “al” and data +
When the level of 51 is lLl, the output buffer (to)
does not operate and data llJ+ becomes a high impedance state. (--dotted chain line portion in FIG. 2(g)). After that, the data tel level changes from 1Hf to lLl (
When the level of fl changes from ILl to 1H1, P channel MO8) transistor Uυ or N channel MO
S transistor 02) is ONL, and output data (') is output to data output terminal 04.

As shown in FIG. 3, the data equalize signal ib+ is
Data from the memory cell (al.

Even if 11Ll is output, only the time until the output buffer (to) starts operating changes, and the output data (g)
is never false data. That is, by using the output system circuit of the present invention, it is possible to prevent false data from occurring even if a timing mismatch with the equalization signal occurs due to a delay in reading from the memory cell.

In the above embodiment, the differential amplifier circuit sieve has [i5] shown in FIG.
], but the P-channel MoS transistor 44, the N-channel MOEI transistor 〇 ratio, and the P-channel M
O8) P-channel M! with the same ratio of transistor d and N-channel MOS transistor). J S Transistor (6) size: Make it smaller than the ftP channel MOS transistor, and make the size of the N-F-Yanel MO8) transistor ■ the same as the N-channel MOS transistor (c).
If it is made smaller, a differential amplifier circuit with low current consumption can be obtained, and this low current consumption differential amplifier circuit can be used as a differential amplifier circuit.
It may also be used for β, producing the same effect as the above embodiment.

Furthermore, although the differential amplifier circuit dK is used in the embodiment described above, other types of differential amplifier circuits may be used and the same effects as in the embodiment described above can be obtained.

〔Effect of the invention〕

As described above, since the semiconductor memory device according to the VC of the present invention is configured so as not to output false data, it is possible to prevent the phenomenon that when false data is output, it takes time to recover and the access time becomes abnormally slow. In addition, a method that latches output data not only slows down the access time but also has the effect of avoiding the problem of latching false data and causing malfunction.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a circuit Ia of an output system of a semiconductor memory device according to an embodiment of the present invention. FIG. 3 is a timing chart when the timing of each signal in FIG. 1 is normal. A timing chart of each signal when a mismatch occurs between the readout from the memory cell and the equalization signal, FIG. 4 is a circuit configuration diagram showing an example of the differential amplifier circuit of FIG. 1, and FIG. 5 is a conventional semiconductor memory device. Fig. 6 is a timing chart when the timing of each signal in Fig. 5 is normal, Fig. 7 Vi is a diagram of the output system Ω circuit configuration diagram of Fig. 5. 2 is a timing chart of each signal. In the figure, 11+, TS is a differential amplifier circuit, 12) is a data bus, 111%), ■ is a P-channel MO8) transistor, α-1) is an N-channel MOS transistor, and 031 is an N-channel MOS transistor. Data output terminal, starvation (to) is NO
T circuit, C31) is the pre-output buffer, and C31) is the output buffer %Ial, tELl, tel, lol
, ldl , te′, (f) is data, (bl
is a data equalization signal, and (g) is output data. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] A semiconductor memory device characterized in that an output buffer circuit is driven by a differential type buffer circuit.