JPH02154516A - Output circuit - Google Patents

Abstract

PURPOSE:To reduce the chip size and to obtain a stable switch characteristic by controlling a gate level of a MOS transistor (TR) for output pullup and a gate level of a MOS TR for output pulldown separately. CONSTITUTION:A control circuit controls a gate level of a MOS TR DM1 for output pullup and a gate level of a MOS TR DM2 for output pulldown separately. Then it is possible to set the MOS TR DM1 for output pullup and the MOS TR DM2 for output pulldown for high dielectric strength to ON selectively or OFF respectively by using a low voltage signal. In such a case, since a voltage by constant voltage elements 21, 22 is applied between the gate and source of the output MOS TR, each drain current is increased and it is almost independently of the dispersion in the threshold level due to the dispersion in the process. Thus, a stable switching characteristic is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a high-voltage output circuit that level-shifts a low-voltage signal and outputs it as a high-voltage output signal.

(Prior art) Generally, electroluminescence (EL) displays and plasma display panels (FDP)
The integrated circuit (IC) for driving light-emitting displays such as
Since a high driving voltage is required, a driving IC with a high breakdown voltage is used. The output circuit of this high-voltage driving IC is required to shorten switching time and reduce current consumption in addition to high voltage resistance. For this reason, CMO8
(complementary insulated gate type) devices and high voltage devices, e.g. DM
An OS (Double Diffused MO8) element is mounted on one chip, and a high voltage signal obtained by level-shifting a CMOS level input signal is output from a push-pull type output stage.

FIG. 4 shows a conventional output circuit used in the above-mentioned driving IC. That is, the drive signal input (In) node is connected to the input terminal of the CMOS inverter IV and the gate of an N-channel DMOS transistor DM3 whose substrate and source are connected to the ground potential Vss. The CMOS inverter IV has a P-channel MO8 transistor P between the low voltage power supply Vdd and the ground potential VSS.
1 and an N-channel MOS transistor N1 are connected in series, and their gates are connected to the drive signal node. The drain of the N-channel DMOS transistor DM3 is connected to the base and first collector of a PNP transistor P2 having a two-collector structure.
The emitter of this PNP transistor P2 is connected to the high voltage power supply Vcc. PNP l-transistor P2
Between the second collector of the substrate and the ground potential Vss, there is a substrate
An N-channel DMOS transistor DM2 for output pull-down whose sources are connected to each other is connected, and the gate of this N-channel DMOS transistor DM2 is connected to the CMOS transistor DM2.
Connected to the output terminal of MOS inverter IV.

Furthermore, the gate of an N-channel DMOS transistor DM for output pull-up is connected to the second collector of the PNP transistor P2.
The drain of the OS transistor DMI is connected to the high voltage power supply vCC
The substrate and source are connected to each other and the drive signal output (Out
) connected to the node. The quad anode of a Zener diode Z1 is connected between the gate and drain of this output pull-up N-channel DMOS transistor DMI.

In the output circuit with the above configuration, when the CMOS level drive signal input In is at a high level "H", the DMOS transistor DM3 is turned on, and this on current causes the PNP
Transistor P2 turns on. The on-current of this PNP transistor P2 generates a Zener voltage Vz in the Zener diode Z1, and the output pull-up DMOS
A required gate-source voltage is applied to the transistor DMI, and this DMOS transistor DMI is turned on, charging the capacitive load of the Out terminal, etc., and pulling up the potential of the output Out to the high voltage power supply level (Vcc level). do.

At this time, the "H" level of the drive signal input In turns the P-channel MO3 transistor P1 and the N-channel MOS transistor N1 of the CMOS inverter V off and on, and the output signal of the CMOS inverter V at the VSS level. Therefore, the output pull-down DMOS transistor DM2 is turned off.

Contrary to the above, when the CMOS level drive signal input In is low level "L", the DMOS transistor DM3 is turned off, the PNP transistor P2 is turned off, and the DMOS transistor DMI for output pull-up is turned off. . On the other hand, the "L" level of the drive signal input In turns on and off the P-channel MO8 transistor P1 and the N-channel MO8 transistor N1 of the CMOS inverter IV, and the output signal of the CMOS inverter IV at the Vdd level. The DMOS transistor DM2 for output pull-down is turned on, discharging the charge of the capacitive load of the Out terminal, and reducing the potential of the output Out to V.
Pull down to SS level.

However, in the output circuit having the above configuration, since the output pull-down DMOS transistor DM2 is driven by the CMOS level output from the CMOS inverter IV, there are problems as described below. That is, this DM
If the drain current of the OS transistor DM2 is Id, the gate-source voltage is VCS, and the threshold voltage is VTH1, the constant is A, then Id = A (VGS-VTH) 2
----------- There is the relationship (1). Here, the threshold voltage VTR is, for example, 1.4V, and the gate-source voltage VGS of the DMOS transistor DM2 for output pull-down is at the CMOS level H'' level (for example, 3.5V).
~5V), its drain current Id largely depends on the threshold voltage VTH, and the drain current Id varies due to variations in the threshold voltage VT) due to process variations, making it difficult to obtain stable switching characteristics. There was a problem.

In addition, a DMOS transistor DMI for output pull-up
is the gate-source voltage of the Zener diode Z
Since a Zener voltage VZ of 1 is applied, if the threshold voltage is VTll and the constant is A, then the drain current Id'
is I d' -A (Vz -VTH) 2- (2)
It is expressed as If this Zener voltage Vz is 10V, for example, the gate-source voltage vGS of the DMO8 transistor DM2 for output pull-down is very small compared to this, so it is Id (Id'), or the change in Id with respect to the change in the VTR. becomes less.

On the other hand, in order to improve the usability of the driving IC, it is required that the rising and falling edges of the waveform of the driving signal output Out be aligned. This is possible by making the outflow current and inflow current of the Out terminal equal (Id'=Id). In the conventional circuit, the relationship between Id (Id') is corrected so that Id'=Id, and the channel width W of the DMOS transistor DM2 for output pull-down is changed to the channel width W of the DMO8 transistor DMI for output pull-up. This can be achieved by designing it to be sufficiently larger than ', but there is a problem in that the chip size increases accordingly.

(Problems to be Solved by the Invention) As described above, in the conventional output circuit, in order to equalize the outflow current and inflow current of the drive signal output terminal, the channel width of the DMO8I transistor for output pulldown is The channel width of the DMO5 transistor for output pull-down must be designed to be sufficiently larger than the channel width of the DMO5 transistor, which increases the chip size accordingly.Furthermore, the drain current of the DMO8 transistor for output pull-down is subject to variations in threshold voltage due to process variations. There is a problem that the switching characteristics cannot be stably obtained because the switching characteristics vary depending on the switching characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems by designing the channel width of the DMO8 transistor for output pull-down to be the same as the channel width of the DMOS transistor for output pull-up. It becomes possible to equalize the current and the inflow current, and the output M
The drain current of the O8I-transistor becomes almost independent of threshold voltage variations due to process variations,
It is an object of the present invention to provide an output circuit that can obtain stable switching characteristics and reduce the chip size.

[Structure of the Invention] (Means for Solving the Problems) The output circuit of the present invention includes an output pull-up MOS transistor whose drain and source are inserted between a first power supply potential and an output terminal; MOS for this output pull-up
A first constant voltage element connected between the gate and source of the transistor, and an output pull-down MOS having a drain and a lath inserted between the output terminal and a second power supply potential.
a second constant voltage element connected between the gate and source of the MOS transistor for output pull-up, and the gate potential of the MOS transistor for output pull-up and the gate of the MO8I-transistor for pull-down of the output; It is characterized by comprising a control circuit that separately controls the potentials.

(Function) By separately controlling the gate potential of the MOS transistor for output pull-up and the gate potential of the MOS transistor for output pull-down by the control circuit, the MOS transistor for output pull-up for high voltage and It becomes possible to selectively set the output pull-down MOS transistors to an on state or an off state. In this case, voltages are applied by constant voltage elements between the gate and source of the output MOS transistors, so each drain current increases and becomes almost independent of threshold voltage variations due to process variations. , stable switching characteristics can be obtained.

In addition, when making the outflow current and inflow current of the output terminal equal, by making the voltages of the first constant voltage element and the first constant voltage element almost equal, the output pull-up MOS
MO for transistor drain current and output pulldown
The drain currents of the S transistors become almost the same, and even if the channel widths of the respective MOS transistors are designed to be the same, the drain currents of the respective MOS transistors become approximately equal, so that the chip size can be reduced.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Figure 1 shows a CMO8 element and a high voltage element, such as a DMO8 element.
This figure shows an output circuit in a high-voltage driving IC in which elements are mixed on one chip. That is, the first control signal input (B) node has an N-channel D whose substrate and source are mutually connected to the second power supply potential (for example, ground potential Vss).
The gate of MOS transistor DM3 is connected.

The drain of this DMOS transistor DM3 is a PNP with a multi-collector structure (three-collector structure in this example).
The base and first collector of transistor P3 are connected, and the emitter of this PNP l-transistor P3 is connected to a first power supply potential (eg, high voltage power supply Vcc). The third collector of the PNP transistor P3 is connected to the gate of an N-channel DMOS transistor DMI for output pull-up, and this DMO8
The drain of the transistor DMI is connected to a high voltage power supply VCC, and the substrate and source are connected to a drive signal output (Out) terminal. There is a substrate between the gate of this DMOS transistor DMI and the ground potential VSS.
An N-channel DMO3 transistor DM4 whose sources are connected to each other is connected, and the gate of this DMO8 transistor DM4 is connected to the second control signal input (A) node.

Further, the second collector of the PNP transistor P3 is connected to the gate of an output pull-down N-channel DMOS transistor DM2 whose substrate and source are connected to the ground potential VSS, and the drain of this DMO8 transistor DM2 is connected to the drive signal output ( Out) terminal. An N-channel DMO3 transistor DM5 is connected between the gate of this DMO8I transistor DM2 and the ground potential Vss, and the gate of this DMOS transistor DM5 is connected to the third control signal input (A) node. It is connected.

In addition, a DMOS transistor DMI for output pull-up
A first constant voltage element, for example, between the cathode and anode of a Zener diode Z1 is connected between the gate and drain of the DMOS transistor DM2 for output pull-down, and a second constant voltage element is connected between the gate and drain of the DMOS transistor DM2 for output pull-down. As a voltage element, for example, the cathode of Zener diode Z2
The anodes are connected.

Next, the operation of the output circuit shown in FIG. 1 will be explained. For example, low-voltage control signals B and A at the CMOS level and A complementary thereto are input to each control signal input node, and a voltage sufficiently higher than the CMOS level is used as the high-voltage power supply Vcc. Now, when the control signals B and A are at a high level "H" and the control signal A is at a low level "L", the DMO8I transistors DM3 and DM5 are turned on and the DMOS transistor DM4 is turned off. Therefore, the on-current of the DMOS transistor DM3 turns on the PNP transistor P3, and the on-current of the PNP transistor P3 generates a zener voltage in the zener diode Z1, and the required gate and source voltage is applied to the DMO3 transistor DMI for output pull-up. A voltage is applied to this DMO3
The transistor DMI turns on and charges the capacitive load etc. of the Out terminal, and the potential of the output Out becomes the high voltage power supply level (
Vcc level).

Note that at this time, the DMO8 transistor DM5 in the on state
Since the drain potential is low, the output pull-down DMO5 transistor DM2, whose gate is given this drain potential, is turned off.

Contrary to the above, control signal A or low level "L" control signal B
When and A are at high level "H", the DMO5 transistor DM5 is turned off, and the DMO5 transistors DM3 and DM4 are turned on. Therefore, this on-state DMO
Since the drain potential of the S transistor DM4 is low, the output pull-up DMO8 transistor DMI, whose gate is given this drain potential, is turned off, but the Zener voltage is applied to the Zener diode Z2 due to the current from the PNP transistor P3. The required gate and
A source voltage is applied to this DMO5 transistor D
M2 turns on, discharges the charge of the capacitive load of the Out terminal, and pulls down the potential of the output Out to the VSS level.

According to the output circuit of FIG. 1, a high voltage signal obtained by level-shifting a CMOS level control signal input can be output from the push-pull type output stage. In this case, a Zener voltage VZ of, for example, IOV is applied not only to the DMOS transistor DMI for output pull-up but also between the gate and source of the DMOS transistor DM2 for output pull-down. The drain current is also expressed by the above equation (2). Therefore, the drain current of the DMOS transistor DMI for output pull-up and the drain current of the DMOS transistor DM2 for output pull-down almost no longer depend on variations in threshold voltage due to process variations, and stable switching characteristics can be obtained. become.

In addition, when making the outflow current and inflow current of the Out terminal equal, the output pull-up DMOS transistor DMI
DMO8 for gate-source and output power down
By applying approximately the same Zener voltage Vz between the gate and source of the transistor DM2, the drain current of the DMOS transistor DM2 for output pull-down becomes almost the same as the drain current of the DMO8 transistor DMI for output pull-up, and its On-resistance between drain and source is reduced. Therefore, even if the channel width of DMO8I-transistor DM2 for output pull-down is designed to be the same as the channel width of DMOS transistor DM1 for output pull-up, DMO3 for output pull-up
Since the drain current of the transistor DMI and the drain current of the output pull-down DMO8 transistor DM2 are approximately equal, the chip size can be reduced.

FIG. 2 shows an output circuit according to another embodiment, and compared to the output circuit of FIG. 1, the DMO8 transistor DM3
A first constant current (11) source 21 and a second constant current (I2) between the substrate-source interconnection point of and the ground potential VSS.
The difference is that a switching circuit 20 for selectively connecting a power source 22 is provided, and the switching operation of this switching circuit 20 is controlled by, for example, a control signal B.The other points are the same, so FIG. The same reference numerals as inside are given. Here, 11 times I2.

The basic operation of the output circuit in Figure 2 is the same as the output circuit in Figure 1, or when the drive signal output Out falls from the VCC level to the VSS level, the output pull-down DMO
Zener between the gate and source of 3 transistor DM2
Since it is sufficient to change the gate-source voltage from the Vss potential to the Zener voltage Vz by flowing a constant current through the diode Z2, the constant current 11 causes the PNP l-transistor P3
is driven to supply a predetermined on-current.

On the other hand, when the drive signal output Out rises from the VSS level to the Vcc level, the output pull-up DMO
Zener between gate and source of 8 transistor DMI
A constant current is applied to diode Z1 to change the gate-source voltage from VSS potential to Vcc potential, and O
Since it is necessary to charge the capacitive load of the ut terminal, the PNP transistor P3 is driven by a constant current (2) to supply a predetermined on-current.

FIG. 3 shows an output circuit according to still another embodiment, and compared to the output circuit of FIG.
The anode and cathode of a diode D for high withstand voltage for preventing reverse current is connected between the substrate-source interconnection point of the MO8 transistor DMI and the drive signal output (Out) terminal, and instead of the control signal A. The difference is that a control signal C is applied, and the other parts are the same, so the same reference numerals as in FIG. 1 are given.

In the output circuit of FIG. 3, the drive signal output Out is ve
If the control signal C is set in the same manner as the control signal A, the operation when the drive signal output Out falls from the c level to the Vss level and the operation when the drive signal output Out rises from the VSS level to the Vc'c level will be as shown in the output circuit of FIG. The same operation is performed. Furthermore, the control signal B is set to "L" level, and the control signals A and C are set to "L" level.
When set to “H” level, DMO8 transistor DM
4 and DM5 are respectively turned on, the DMO8 transistor DMI for output pull-up and the DMO8 transistor DM2 for output pull-down are respectively turned off, and the Out terminal becomes a high impedance state. At this time, the diode D prevents the current from flowing backward from the Out terminal side to the DMOS transistor DM4 side.

Note that the present invention can be implemented in various modifications; for example, in each of the above embodiments, the high voltage bipolar transistor P3 is used as the level shift circuit, but instead of this, a high voltage MOS transistor can be used. Good too.

[Effects of the Invention] As described above, according to the output circuit of the present invention, the channel width of the MOS transistor for output pull-down is designed to be the same as the channel width of the MO5+- transistor for output pull-up, and the width of the drive signal output terminal is It is possible to equalize the outflow current and inflow current, and moreover, the drain current of the output MOS transistor is almost independent of variations in threshold voltage due to process variations, so stable switching characteristics can be obtained. At the same time, the chip size can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the output circuit of the present invention, FIGS. 2 and 3 are circuit diagrams showing other embodiments of the output circuit of the present invention, and FIG. 4 is a conventional output circuit. FIG. A, A, B, C... Control signal input, vcc...
...First power supply potential (high voltage power supply) Vss...
...Second power supply potential (ground potential) DMI to DM
5...DMOS transistor, P3...
・PNP transistor, Out... Drive signal output, Zl... First constant voltage element, Z2...
... Second constant voltage element, D... Diode. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) An output pull-up MOS transistor whose drain and source are inserted between the first power supply potential and the output terminal;
a first constant voltage element connected between the sources; an output pull-down MOS transistor whose drain and source are inserted between the output terminal and a second power supply potential; and the output pull-down MOS transistor. gate of
A second constant voltage element connected between sources, and a control circuit that separately controls the gate potential of the output pull-up MOS transistor and the output pull-down MOS transistor. output circuit. (2) The output circuit according to claim 1, wherein a reverse current prevention element is inserted between the source of the output pull-up MOS transistor and the output terminal.