JPH02154470A - Memory cell of nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To put a control control gate between a drain and a floating gate and prevent the floating gate from rising, a suppressing the capacitive coupling between the floating gate and the drain, by prolonging one end of the control gate in the drain direction and bringing it into contact with the first gate insulating film. CONSTITUTION:A part of a control gate 2 is prolonged in the drain direction 5 and touches the first gate insulating film 10 directly. By this, the control gate 2 is put between the drain and a floating gate 3, and excludes the capaci tive coupling between the drain 5 and the floating gate 3 of a nonselective cell. Accordingly, it becomes possible to suppress the channel leak owing to the rising of the floating gate 3 and prevent the lowering of digit line potential at the time of writing operation. Besides, it also becomes possible to prevent the discharge of the charge of a having-been-written cell owing to stress being applied to the drain 5, as the drain 5 and floating gate 3 are isolated from each other in structure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a floating gate type volatile MO3 semiconductor device, and more particularly to a nonvolatile memory that can be electrically written to and erased all at once.

[Prior Art] Conventionally, the structure shown in FIGS. 2A and 2B has been most commonly used in this type of floating gate type nonvolatile MOS semiconductor device, in which the floating gate and the control gate are formed in a self-aligned manner. The floating gate has a structure in which both sides of the floating gate overlap with the source and drain by the lateral inward expansion of the diffusion layer. The write method includes applying a positive write voltage to the control gate and simultaneously applying a positive drain voltage.
This is done by injecting some of the hot electrons generated near the drain into the floating gate, and erasing is done by exciting the electrons in the floating gate by irradiating UV light to increase the barrier height of the silicon/silicon dioxide interface. 2
This is done by applying energy exceeding eV and emitting it outside the floating gate.

[Problems to be Solved by the Invention] However, as the above-mentioned conventional floating gate type volatile MO3 semiconductor devices have become larger in capacity and thinner in recent years, the following problems have become impossible to ignore.

Ru. That is, although the equivalent circuit of the memory element is shown in FIG. 3, when the gate length of the memory cell is long, there is a relationship between the capacitances in FIG. 3 as CI, C2 >> C3, C32,
Moreover, if the impurity in the source/drain diffusion layer is arsenic, etc., which has a small diffusion coefficient, the overlap capacitances C3 and C3'
However, with the recent trend toward shorter channels, the influence of C3, that is, the floating gate-drain overlap capacitance, can no longer be ignored. That is, as shown in FIG. 4, word line xi, digit line Yj
When attempting to write a data hit to memory MIJ by selecting , Yj is common in unselected Mi-1j or Mi+Ij, so Mij is placed on each drain.
The same positive applied voltage is applied.

At this time, the floating gate floats due to the influence of C3, and Mi-1j and Mi+1j, which should be in the off state, are weakly reversed and a current flows, so Yj raises MiJ to a writeable potential.
This will cause problems when writing. As the number of memory cell transistors hanging from Yj increases, this capacity jlc
3 has a big influence.

On the other hand, if we consider the case where Mij has already been written and Mi-1j or Mi+IJ hanging from another identical Yj is being written, at this time the write voltage is applied only to the drain of Mij. Among the hot carriers generated near the drain due to this stress, holes are attracted to the floating gate, which is at a relatively lower potential than the drain potential, and are injected, canceling out the electrons in the floating gate.
It also has the disadvantage of lowering the writing level. In this case as well, the more memory cell transistors that hang from one digit line, the more serious the effect will be.

[Differences between the invention and the prior art] Compared to the above-mentioned conventional floating gate type volatile MO5 semiconductor device, the present invention has one end of the control gate aligned in the drain direction ζ4.
By extending and contacting the first gate insulating film,
A control gate is interposed between the drain and the floating gate, and for unselected cells, capacitive coupling between the floating gate and the drain is suppressed to eliminate floating gate floating, and the drain and floating gate are isolated. , the difference is that it is not affected by hot carriers generated by the voltage applied to the drain.

[Means for Solving Problems] The gist of the present invention is to provide a source region and a drain region of a second conductivity type formed on a semiconductor substrate of a first conductivity type and separated from each other; a first gate insulating film formed on a semiconductor substrate between the regions; a non-floating gate provided on the first gate insulating film and having one end located above an end of the source region; a second gate insulating film formed, and a control gate formed on the second gate insulating film and the first gate insulating film so as to partially overlap the floating gate, and having one end located above an end of the drain region. In a memo cell of a nonvolatile semiconductor memory device comprising: applying a first polarity write voltage to the control gate and simultaneously applying a first polarity drain voltage, between the source region and the drain region; Writing is performed by injecting a portion of hot electrons accelerated in the channel direction into the floating gate by utilizing the difference in surface potential between the bottom of the control gate and the bottom of the floating gate in the inversion channel region. It is.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

1A and 1B are a plan view and a cross-sectional view of a first embodiment of the present invention, respectively, and FIG. 1B is an A in FIG. 1A.
- It is a sectional view cut along the A' line. As shown in FIG. 1B, the channel region between the source 4 and the drain 5 is formed so that the floating gate 3 directly defines the source side and the control gate 2 directly defines the drain side through the first gate insulating film 10. The structure is such that a part of the control gate 2 extends above the floating gate 3 via the second gate insulating film 11, as shown in the figure.

Next, its operation will be explained. The source 4. An inversion region is formed between the drains 5, and at this time, the potential of the floating gate 3 is determined by the capacitance ratio determined by the film thickness and area of the first gate insulating film 10 and the second gate insulating film 11. Assuming that the film thickness is 300 and the second gate insulating film is 400, the potential of the floating gate is approximately 0. 60VCG (V
CG: control gate voltage) is 7.5V to 11. It becomes OV. Therefore, the control gate 2 is inverted weaker than the channel region directly in contact with the first gate insulating film, and its surface potential is also relatively high. When electrons, which are channel carriers, pass through this channel region, they are accelerated in the horizontal direction with the channel due to this potential difference, resulting in a barrier height of 3 at the silicon/silicon dioxide interface.
．． Hot electrons exceeding 2 eV are generated and injected into the floating gate 3 to perform writing. Figure 6 shows VCG
=17. It shows the write characteristics of this example when OV was performed.

FIG. 7 shows the effect of improving the lifting of the floating gate 3. Figure 7 shows the VDS-IDS characteristics (with the control gate grounded) of the conventional type (the type shown in Figures 2A and 2B) and this embodiment (Figure 1), each with a floating gate length of 1.2 μm. As is clear from this figure, VDS
In the <8.4V region, the effective channel length is longer due to the overlap of the control gate in the drain direction, and the DS is also lower; in the VDS>8.4V region,
The effect of suppressing lifting can be clearly seen.

FIG. 5 is a sectional view of a second embodiment of the invention.

The plan view of this embodiment is similar to FIG. 1A of the first embodiment. In this embodiment, the control gate 2 is different from the first embodiment.
A channel doping region 12 is formed in the channel region where the floating gate 3 is in direct contact with the first gate insulating film 10 so as to be easily inverted in self-alignment with the floating gate 3 after the floating gate 3 is formed.

By doing this, when a positive write voltage is applied to the control gate 2, the difference in surface potential between the channel doped regions under the floating gate and the control gate becomes even larger than in the first embodiment, and the channel electrons are further reduced. This has the effect of efficiently accelerating and increasing writing efficiency.

[Effects of the Invention] As explained above, the present invention allows the control gate to be interposed between the drain and the floating gate by extending a part of the control gate in the drain direction and directly contacting the first gate insulating film. Since capacitive coupling between the floating gate and the drain of unselected cells is eliminated, channel leakage due to floating of the floating gate can be suppressed, and a drop in digit line potential during write operation can be prevented. Furthermore, since the drain and the floating gate are separated from each other, it is possible to prevent the charge in the written cell from dissipating due to stress applied to the drain.

Generally, due to its structure, the end of the floating gate is covered with a control gate, so by applying a certain positive voltage to the control gate, electrons in the floating gate can be tunneled to the control gate at this end. Since it is possible to inject and electrically erase all at once, there is no need for a package with a window for irradiating ultraviolet rays as in the conventional case, and it can be written and erased many times even if it is enclosed in an inexpensive plastic package. It also has the effect of making erasing possible.

-10~

[Brief explanation of the drawing]

Figure 1A is a plan view of the first embodiment, Figure 1B is a sectional view taken along line A-A'' in Figure 1A, and Figure 2A is a non-volatile MO5
A plan view showing a conventional example of a semiconductor device, FIG. 2B is a sectional view taken along line BB' in FIG. 2A, FIG. 3 is an equivalent circuit diagram of the conventional example, and FIG. 4 is a single digit in the conventional example. 5 is a sectional view of the second embodiment of the present invention, FIG. 6 is a graph showing the write characteristics of the first embodiment, and FIG. 7 is a graph showing the write characteristics of the first embodiment. 7 is a graph illustrating a difference in channel leakage current due to floating between the invention and a conventional example. 1 ・ 3 ・ 4 ・ 5 ・ 6 ・ 7 φ ・Field insulating film, ・Word line (control gate), ・Floating gate, ・Source diffusion layer, ・Drain diffusion layer, ・Drain contact, ・Digit line, 8 ・ ・9 ・ ・ 10 ・ 11 ・ 12 ・

Claims (1)

[Claims] A source region and a drain region of a second conductivity type formed on a semiconductor substrate of a first conductivity type and separated from each other; and a first gate insulating film formed on the semiconductor substrate between the source region and the drain region. , a floating gate provided on the first gate insulating film and having one end located above an end of the source region; a second gate insulating film formed on the floating gate;
A memory for a non-volatile semiconductor memory device comprising the second gate insulating film and a control gate formed on the first gate insulating film so as to partially overlap the floating gate and having one end located above an end of the drain region. In the cell, a first polarity write voltage is applied to the control gate and a first polarity drain voltage is simultaneously applied to the control gate and the floating gate in the inverted channel region between the source region and the drain region. A memory cell of a nonvolatile semiconductor memory device, characterized in that writing is performed by injecting a portion of hot electrons accelerated in a channel direction into the floating gate using a difference in surface potential between the two.