JPH02148979A - Solid-state image pickup element driving device - Google Patents

Abstract

PURPOSE:To attain the start and end of exposure in an optional timing by applying reset by a PG pulse after the end of exposure and generating a vertical synchronizing signal (VSYNC). CONSTITUTION:When the first PG pulse after the end of exposure is outputted from a recorder 3, the PG pulse passes through a gate 23 and the edge of the PG pulse is detected by an edge detection circuit 24, an H reset pulse is generated by an H reset generating circuit 25 and a V reset pulse is generated by a V reset generating circuit 26. The H reset pulse is fed to a frequency divider 14 and an H shifter 18, and the V reset pulse is fed to a V counter 15, a V shifter 16 and a decoder 17 and then reset. Thus, the signal charge stored by the exposure is read and the charge is processed by a signal processing circuit 2 and the resulting signal is fed to a recorder 3. Thus, the start and end of exposure is attained in a desired timing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a solid-state image sensor driving device used in an electronic still camera.

(Background of the Invention) Solid-state imaging devices such as COD are used as light-receiving devices in electronic still cameras. This type of electronic still camera is
Optical information is converted into electrical signals and further stored on an information recording medium such as a video floppy. Therefore, unlike a silver halide film camera, there is no need for development, and furthermore, there are advantages such as image information can be transferred to a remote location.

(Problems to be Solved by the Invention) Incidentally, there are cases in which such an electronic still camera is used to take snapshots at high speed. However, exposure and recording time were required, and there was a limit to the improvement in snapshot speed. It is also necessary to match the drive timing of the solid-state image sensor with the rotation of the video floppy, which also takes time.

FIG. 3 is a timing diagram showing the drive timing of a solid-state image sensor drive device used in a conventional electronic still camera. Note that this timing is when a frame interline CCD is used. Here, a case will be described in which exposure is first performed and then signals obtained by the exposure are read out.

In order to synchronize the rotational phases of the solid-state image sensor drive device and the video floppy, a vertical synchronization signal (V 5YNC) appears 7H (horizontal scanning period) after the rising edge of the PG pulse, which is the rotation reference signal of the video floppy. Reset (H reset (horizontal synchronization signal reset)
and V reset (vertical synchronization signal reset)) (Figure 3 (d), (e), and ■). Then, when the start of exposure is instructed by the fall of the trigger signal (Fig. 3 (a) ■), a high-speed transfer pulse is generated at the φ■ times signal (Fig. 3 (b)) immediately after, and solid-state imaging is performed. Sweep out unnecessary charges on the vertical transfer section of the device. Thereafter, a sensor signal (SG) pulse (FIG. 3 (b) (2)) is generated in the φl signal to sweep out unnecessary charges on the light receiving element of the solid-state image sensor. Also,
Immediately after the rise of the trigger signal instructs to stop the exposure (FIG. 3(A) 2), a φI times signal high-speed transfer pulse is generated to sweep out the charges generated on the vertical transfer path of the solid-state image sensor. Thereafter, the signal charge accumulated in the light receiving element is transferred to the storage section by the sensor gate pulse (FIG. 3(b) 2). Therefore, the period from ■ to ■ becomes the actual exposure period. Thereafter, the reset using the PG pulse is performed again (FIG. 3 (d), (e) (2)), and at the timing (2), reading out of the charge generated by exposure from the solid-state image sensor is started.

Even when the above-mentioned timing operations are performed, there is a problem that if the exposure is completed during the V5YNC period, an image cannot be output from the solid-state image sensor. Therefore, the microcomputer for system control of the electronic still camera must constantly monitor the 5YNC signal and control the exposure so that it does not end during the VSYNC period. Therefore, depending on the timing of the operation, a waiting time may occur, and exposure starts at the desired timing.

The problem is that it cannot be terminated. Another problem is that the continuous shooting speed cannot be increased due to the waiting time.

Furthermore, there is also the complexity of having to perform a reset first to align the rotational phases of the solid-state image pickup device drive device and the video floppy.

The present invention has been made in view of these points, and
The purpose is to provide a solid-state image sensor driving device that can start and end exposure at desired timing.

(Means for Solving the Problems) The present invention, which solves the above-mentioned problems, provides a solid-state image sensor driving device that generates timing signals and synchronization signals for the exposure operation of the solid-state image sensor and the readout operation of charges generated by the exposure. A synchronizing signal generating means for generating a horizontal synchronizing signal and a vertical synchronizing signal, a timing signal generating means for generating a timing signal for exposure operation and readout operation of the solid-state image sensor, and a reference signal applied from the outside. resetting means for resetting the synchronizing signal generating means, the resetting means resetting the synchronizing signal generating means after the completion of exposure of the solid-state image sensor, and the synchronizing signal generating means generating the vertical synchronizing signal after the reset is performed. The horizontal synchronizing signal is generated during the rest of the period, and only the horizontal synchronizing signal is generated during the other periods.

(Function) The reset means resets the synchronization signal generation means after the exposure of the solid-state image sensor is completed, and the synchronization signal generation means generates a vertical synchronization signal after this reset. During the other periods, only the horizontal synchronizing signal is generated.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of an embodiment of the present invention together with peripheral parts. In this figure, 1 is a solid-state image sensor that generates an image signal by exposure, and 2 is a solid-state image sensor l.
The image signal from 5YNC.

A signal processing circuit that converts the video signal into a video signal according to a synchronization signal such as BLK, a recording device 3 that records the video signal on a video floppy according to the REC gate pulse, and a recording device 4 that controls all parts in accordance with the operation of the shutter button 5. trigger pulse.

This is a system control circuit that generates PG agatelus, etc. Reference numeral 11 denotes a solid-state image sensor driving device that applies driving pulses to the solid-state image sensor 1. 12 is an oscillator that generates a reference signal, 13 is a drive pulse generation circuit that creates a drive pulse from the reference signal, 14 is a frequency divider that creates a horizontal scanning frequency (f o ) signal from the reference signal, and 15 is a vertical scanning circuit from fl+. a V counter that creates a frequency (fv) signal;
16 is a V shifter that creates a plurality of fv multiplied signals having different phases from the fV multiplied signal; 17 is a decoder that creates a synchronization signal;
8 is an H shifter that creates a plurality of f and signals with different phases from the fN signal; 19 and 20 are HS shifters and HS counters that create high-speed transfer (H3) signals for the solid-state image sensor 1 from the reference signal, respectively; 21 is an HS counter; It is an HS decoder. Note that the terminals 14 to 18 indicated as HR or VR are the terminals to which the H reset signal and the ① reset signal are applied, respectively. Of these, the H reset signal and the V reset signal are given when synchronizing with the rotation of the video floppy of the recording device 3. 22 is PC pulse.

A reset circuit that generates an H reset signal when a trigger pulse is applied; 23 is a gate that allows only the first PG pulse after exposure to pass; 24 detects the edge of the PG pulse that has passed through gate 23; an edge detection circuit; 25 is an H reset generation circuit that generates an H reset signal from the edge or trigger of a PG pulse;
26 is a V reset generation circuit that generates a V reset signal. Although the connections to which the H reset signal and V reset signal are supplied are omitted in FIG. 1, they are applied to the above 14 to 18 as described above. 27 is a shutter control circuit that creates a shutter control signal to control exposure based on the trigger pulse given from the system control circuit 4; 28 and 30 are signals for driving the solid-state image pickup device based on the Is multiplied signal fH scratch signal fv multiplied signal, respectively. 29 is a φSG decoder that generates exposure start and end signals (SG pulses) to the solid-state image sensor based on the above fl (signal, fv multiplied signal shutter control signal); 31
28 is a drive circuit that amplifies the output signals of 29 and 30 and supplies the amplified signals to the solid-state image sensor 1 as drive signals for the solid-state image sensor.

FIG. 2 is a timing chart showing an example of the above-described image sensor drive circuit 11 and signals around it. In this timing chart, (a) shows the trigger pulse given to the shutter control circuit 27 from the system control circuit 4, and (b) shows the φ■ pulse generated by the φ■ system decoder 28 and the SG pulse generated by the φSG system decoder 29.
A combination of pulses, (c) is a φS decoder 30
(d) is the PG pulse given from the recording device 3, (e) is H5YNC+ vSYNC
A composite synchronization (C3YNC) signal consisting of a composite synchronization (C3YNC) signal, (f) a composite blanking (CBLK) pulse, and (g) a PG agate pulse for passing the PG pulse at the PG gate 23. Note that when this PG agate pulse is at a high level, only the first PG pulse after the end of the exposure operation is valid. (H) is the REC gate pulse indicating the timing at which the recording device 3 performs recording, (S) is the H reset pulse generated by the H reset generation circuit 25, and (NU) is the V reset generated by the V reset generation circuit 26. It's a pulse.

The operation will be explained below with reference to the timing charts shown in FIGS. 1 and 2. The system control circuit 4 is waiting for the shutter button 5 to be pressed. Even if a PC pulse appears in this state (before the shutter 5 is operated) ((i) in FIG. 2), the reset (2) is not performed. That is, at this time, the PG pulse is at a high level (FIG. 2 (g)) and the exposure operation has not yet ended, so the PG pulse cannot pass through the gate 23.

Therefore, neither H reset nor ■ reset is performed, and C3
V5YNC is not generated in the YNC signal either.

If the shutter button 5 is pressed here, the trigger signal from the system control circuit 4 falls and the shutter control circuit 27 is instructed to start exposure (FIG. 2(a) 2).

At this timing, the H reset pulse HR is generated from the H reset generation circuit 25 (see FIG. 2), and the H reset for the horizontal synchronizing signal H5YNC is executed. Immediately after that, the φI pulse from the φI decoder 28 (see FIG.
(b)) A high-speed transfer pulse is generated to sweep away unnecessary charges on the vertical transfer section of the solid-state image sensor 1. And then φI
A pulse of the double signal SG (FIG. 2 (b) ①) is generated to sweep out unnecessary charges on the light receiving element of the solid-state image sensor 1. Also,
When a predetermined exposure time has elapsed or a proper exposure amount has been reached, a trigger signal rises and an instruction to stop the exposure is given (FIG. 2(A) 2). At this timing, the H reset pulse HR is generated from the H reset generation circuit 25 (see Fig. 2), and the H reset pulse HR is generated for the horizontal synchronizing signal H3'/NC.
A reset is performed.

Immediately thereafter, a φI-times signal high-speed transfer pulse is generated (FIG. 2 (b) (2)) to sweep out the charges generated in the light receiving element of the solid-state image sensor 1. Therefore, the period from ■ to ■ is the actual exposure period. After this, H reset and ■ reset are performed using the PG pulse from the recording device 3 (Fig. 2 (d), (
), (nu)■), V 5 7H after the rising edge of the PG pulse, which is the video floppy rotation reference signal.
Reset so that YNC appears.

That is, the first PG pulse after exposure is
When the PC pulse is output from A reset generation circuit 25 generates an H reset pulse, and a V reset generation circuit 26 generates a V reset pulse. Among these, the H reset pulse is sent to the frequency divider 14 and the H shifter 18, and the reset pulse is sent to the V counter 15,
It is applied to the V shifter 16 and decoder 17 and reset. Therefore, by this reset, the solid-state image sensor driving signal generated by the solid-state image sensor driving device 11 is transferred to the recording device 3.
The rotation of the video floppy is synchronized with the rotation of the video floppy.

Then, at the subsequent timing (2), reading out of the signal charges accumulated by exposure is started. Then, the read signal is subjected to signal processing by the signal processing circuit 2 and then supplied to the recording device 3. At the same time, an RFC gate pulse is applied to the recording device 3. Thereby, the recording device 3 records on the video floppy. In the past, this REC gate pulse was managed by a microcomputer within the system control circuit 4, but sufficient accuracy may not be obtained depending on the performance and clock frequency of the microcomputer. Therefore, in this embodiment, the shutter control circuit 27 in the solid-state image sensor driving device 11 manages the image sensor. Therefore, accuracy is improved compared to the conventional method.

When the recording by the recording device 3 is completed, the magnetic head of the recording device 3 is moved to the next track in preparation for the next operation. The drive pulse for this purpose (plunger drive pulse,
Step motor drive pulse) is also solid-state image sensor drive device 1
Make it occur on the first side. This drive pulse is the RF
It is best to output it immediately after the C pulse is turned off. By managing this on the image sensor drive circuit 11 side, the system control circuit 4 can control the next shutter operation during this time, which has the advantage of increasing the speed of snapshots.

As described above, by performing the V reset only after the end of exposure, the vertical synchronization signal (V 5YNC) is generated after the end of exposure, so the exposure start/end timing and V 5YNC no longer overlap. The conventional waiting time at the start/end of exposure no longer occurs. Therefore, exposure can be started and ended at any timing. Therefore, there is no need to worry about missing a photo opportunity. Furthermore, since this waiting time is eliminated, there is also the effect of increasing the speed of quick shooting.

(Effects of the Invention) As explained in detail above, in the present invention, after the exposure is completed, reset is performed using the PG pulse, and the vertical synchronization signal (VS
YNC). Therefore, the exposure start and end timings do not overlap with V5YNC, and the conventionally bundled waiting time at the time of exposure start and end does not occur. Therefore, it is possible to realize a solid-state image sensor driving device that can start and end exposure at any timing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing signal waveforms during operation of the present invention, and FIG.
The figure is a time chart showing an example of a conventional case. 1... Solid-state image sensor 2... Signal processing circuit 3...
-Recording device 4...System control circuit 5...Shutter button 11...Solid-state image sensor drive device 12...Oscillator 13...Drive pulse generation circuit 14...Frequency divider 15...V Counter 16・
...V shifter 17...Decoder 18...H shifter 19...HS shifter 20...HS counter 21...HS decoder 22...Reset circuit
23...Gate 24...Edge detection circuit 25...H reset generation circuit 26...V reset generation circuit 27...Shutter control circuit 28...φI system decoder 29...φSG system decoder 30 ...φS system decoder 31...drive circuit

Claims (1)

[Scope of Claims] A solid-state image sensor driving device that generates timing signals and synchronization signals for an exposure operation of a solid-state image sensor and a readout operation of charges generated by the exposure, the device generating a horizontal synchronization signal and a vertical synchronization signal. a timing signal generating means for generating a timing signal for the exposure operation and readout operation of the solid-state image sensor; and a reset means for resetting the synchronizing signal generating means using a reference signal applied from an external source. The reset means resets the synchronization signal generation means after the exposure of the solid-state image sensing device is completed, and the synchronization signal generation means generates a vertical synchronization signal after this reset, and only generates a horizontal synchronization signal during other periods. What is claimed is: 1. A solid-state image sensor driving device, characterized in that it is configured to generate.