JPH02148940A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To suppress increase in a ripple and to keep a line quality by varying scramble processing to an input binary signal which increases the ripple of an output of a multi-level QAM signal. CONSTITUTION:Six output codes P1-P3, P4-P6 from a PN pattern generator 11 to plural prescribed variable signals I1-I3, Q1-Q3 inputted and subjected to code processing in EX-OR1 - EX-OR6 of an exclusive OR circuit 13 of a signal processing section 1 are made variable and two comparison codes to apply EX-OR processing to high-order binary signal inputs I1, Q1 especially are selected by selecting two outputs of proper combination from high-order output P1, P2 and low-order outputs P7, P8 among output codes P1-P8 of the PN pattern generator 11. Then a selection signal SEL and an output ripple p are com pared to obtain the control signal C of a comparison control section 10. Thus, the increase in the ripple p is suppressed and the deterioration in the line quality is prevented.

Description

[Detailed Description of the Invention] [Summary] The output of a PN pattern generator that inputs a binary signal for multilevel QAM modulation for digital multiplex wireless communication as a predetermined plurality of parallel signal sequences and generates a pseudo-random pattern for each sequence. Regarding a digital signal processing circuit that obtains a multi-value QAM signal by sending it to the quadrature amplitude modulation section of the multi-value QAM after performing scrambling processing, an increase in the ripple Δp of the scrambled multi-value QAM signal output due to a change in the content of the input binary signal. A comparison/control unit that compares and detects the ripple Δp of the multi-value modulated output signal and generates the control signal C, and the output of the comparison/control unit. A selection circuit is provided which uses the control signal C as the selection signal SEL and selects an appropriate combination of two signals from the upper and lower outputs of the output code of the PN pattern generator, and the output signal of the selection circuit and the output signal of the selection circuit are provided in an exclusive OR circuit. 2 of the plurality of series
The configuration is configured to perform an exclusive OR with the higher order signal of the value signal input, and then perform an exclusive OR between the remaining output from the PN pattern generator and the intermediate and low order signals of the binary signals of the plurality of series, and output the result. .

[Industrial application field]

TECHNICAL FIELD The present invention relates to digital multiplex wireless communication, and in particular,
A binary digital signal for QAM modulation is subjected to speed conversion, etc., and inputted as a predetermined plural series of parallel data signal sequences,
The present invention relates to a digital signal processing circuit that performs scrambling processing using the output codes of respective PN pattern generators and sends them to a multi-value QAH quadrature amplitude modulation unit to obtain scrambled multi-value QAM signals.

[Conventional technology]

Conventionally, a digital signal processing circuit on the transmitting side of a multilevel QAM signal performs speed conversion (not shown) on an input binary digital signal to generate a predetermined plurality of data signal sequences, e.g., as shown in FIG. For 64-value QA, 6 series of 3 columns each (8 series of 4 columns for 256-value QAM) parallel data signal strings are input to the signal processing unit IA as Ig, 'Iz, Q+, Qz, Q, respectively. , a PN that generates a pseudo-random pattern ρ, ~p, with the same period as the input signal, in order to prevent malfunctions due to a succession of the same code “O” or “1”.
Six output codes p, ~[ of the output of the pattern generator 11A
At 16, each EX-OR gate of the exclusive logic circuit 13A performs code processing and scrambling processing, and sends the processed 6-series binary signal string to the orthogonal amplitude modulation section 2, which converts it into a 64-value QAM signal. Six binary signal sequences scrambled by the signal processing unit IA 1.12. I3. Ql,Q
Z and Q3 are two 3 rows each (7) D/A i converter 21.
22, convert them into the L channel analog signal A I and the Q channel analog signal A, respectively, and mixers 31 and 32
At , the carrier waves are branched from the carrier wave oscillator 4 into the orthogonal hybrid 5 and mixed with carrier waves having a mutual phase difference of π/2, and are frequency-converted and amplitude-modulated by IP times the center frequency fo.
The hybrid circuit 6 generates two amplitude modulated waves IPI, IP
, and outputs it as a multi-level QA) i multiplied signal.

Center frequency f synthesized and output by the hybrid circuit 6
The multi-level QAMed output signal IF of o contains ripple Δp as shown in Fig. 3(a), but normally the ripple Δp of the second output signal is minute and does not cause deterioration of line quality. .

[Problem to be solved by the invention]

However, depending on the content of the binary digital signal to be transmitted, the input signal to the signal processing unit 1 may be
The same code continues in +Ql+Q2+, which is the output code of a fixed pattern from the conventional PN pattern generator 11A.
l-1) In the scrambling process by b, multi-level QAM
The ripple Δp of the modulated output signal becomes so large that it cannot be ignored, as shown in Figure 3), which adversely affects carrier wave regeneration and clock regeneration in the demodulator on the receiving side (not shown), and becomes a factor that deteriorates line quality. There was a problem. That is, in the conventional example, the pseudo pattern pl from the PN pattern generator 11A used for scrambling processing in the signal processing unit IA is
Since -p& was fixed, there was a problem in that it was impossible to process a change in the ripple Δρ of the multi-value QAM signal output due to a change in the content of the input binary signal. An object of the digital signal processing circuit of the present invention is to suppress an increase in the ripple Δp of the scrambled multilevel AM signal output due to a change in the content of the input binary signal.

[Means to solve the problem]

This problem is solved by the ripple Δ of the 64-value QAM signal output.
p is the extracted code p1~ from the PN pattern generation circuit 11^
Although it varies depending on p, the conventional PN pattern generator 11
Since the extraction codes p1 to p from A were fixed and input to each IEX-OR of the exclusive OR circuit 13A and subjected to EX-OR processing, the output multi-valued due to the content change of the input binary signal. It was impossible to deal with the increase in the ripple Δp of the QAM signal, which adversely affected the line quality, and the output ripple Δp was 1, and the upper output code of both Q channels was II' + Ql'. Focusing on the large influence of Signal, h, Is, Q+, Qz
6 from the PNN butter generator 11 for each of , Ch.
The output codes p1 to ps+ ρ4 to pb are made variable, and especially the upper binary signals 1. ．． The selection circuit 12 selects an appropriate combination of two comparison codes for EX-ORing Q1 from the upper output p++ pz and the lower output p71 pIl among the output codes p1 to pe of the PNN butter generator 11. By using the selection signal SEL as the control signal C of the comparison/control unit 10 that compares the ripple Δρ of the output and generates the control signal C, the selection circuit 12 selects the output signal SEL and selects the remaining intermediate output 93. ~p b is fixed and corresponds to EX-OR2, EX-OR3, EX-ORs,
Output to EX-ORb and input signal IZ+13+12+0
3 (7) This problem is solved by the configuration of the present invention in which exclusive OR is performed on each of them and output.

In the principle diagram of FIG. 1 showing the configuration of the digital signal processing circuit of the present invention, 1 is a predetermined number of parallel binary digital signal inputs for multi-level QAM modulation of the input binary signal, for example, 64-level QAM.
In the case of modulation, six binary signals 1. ．． I2+ 1
3+Ql+口2,0. This is a signal processing unit that inputs the signals in parallel, performs an exclusive OR with each of a predetermined number of six output phases from the PNN butter generator 11, performs scrambling processing, and outputs the result.

11 is a binary signal 11+lff input to the signal processing unit 1
1+ 13+Q, , Qg, clock period of Q3 22・8
A pseudorandom code with a period equal to bits 1) l-pe
This is a PN pattern generator that generates .

12 is the output code p l-p of the PNN butter generator 11
Of e, upper output pt+ pz and lower output p”L p
Select a suitable combination of 2 outputs from the 4 outputs of s using the signal SEL.
This is a selection circuit that selects by.

13, by the two outputs of the selection circuit 12, the upper two signals I, Q, (7) of the input signals 1+, Iz, Is, Q+, Qg, Qs of the signal processing unit 1 are EX-ORed, respectively.
,,[! X-0R, take the disjunction and get 11' +Q
At the same time as outputting I', the remaining intermediate outputs ρ3 to p of the output of the PNN butter generator 11 are fixed and the corresponding E is output.
X-OR1, EX-OR3, EX-OR8゜EX-OR
, and input signals 1z, Is, Qz, Q+ (exclusive OR with each D and output signal 1!' +13 tQ
This is an exclusive OR circuit that outputs Z'+Qff' in parallel.

2 is a predetermined number of 6 parallel digital signals I+', t, '+F output from the exclusive OR circuit 13 of the signal processing unit 1.
+ g, l tQZ '+03' is converted into multi-value I channel analog signal AI by two El/A converters 2L22.
, into a Q channel analog signal, amplitude modulates the outputs of the carrier wave oscillator 4 with a mutual phase difference of π/2 using two amplitude modulators 31 and 32, and sends the two amplitude modulated waves to a hybrid synthesizer. This is a quadrature amplitude modulation section that synthesizes signals from the QAM signals 6 and 6 and outputs a multilevel QAM signal.

Reference numeral 10 denotes a comparison/control unit that compares and detects the bias ripple Δp of the multilevel QAM signal output from the quadrature amplitude modulation unit 2 and outputs a control signal C.

The control signal C output from the comparison/control section 10 is configured to be the selection signal SEL of the selection circuit 12.

[Effect]

The PNN butter generator 11 generates a pseudorandom code P at a period equal to the clock period of 23.8 bits of the input binary signal l1lIZII31Qll ports 2 and 03 of the signal processing unit 1.
l-1) A circuit 12 which generates a and selects the upper output p+, pz and the lower output p71 pH among the generated codes p, ~p8.
BX-O sends the remaining output codes p3 to p to the BX-O, which directly processes the middle and low order signal inputs of the exclusive OR circuit 13.
R2, EX-OR: 1. EX-ORs, EX'ORb
Send to.

The selection circuit 12 selects the output sign p of the PNN butter generator 11.
, ~p, the upper output pl+ pz and the lower output 1)?
1. Compare the appropriate combination of 2 outputs from the 4 pH outputs.
Selected by the selection signal SEL which is the control signal C output from the control section 10, and inputs the upper signal of the exclusive OR circuit 13! ,
, Q, are sent to EX-OR and EX-OR4, which perform code processing.

The exclusive OR circuit 13 is (7) EX-ORI, E
With X-OR<, the two selected outputs of the selection circuit 12 and the input signal 1 of the signal processing section l. , It, h, Q, Qz, Qz upper 2 signal human power 1. ．． At the same time, the EX-O
R2, EX-OR3, EX-ORs, EX-OR&, the intermediate output p3 of the remaining output of the PNN butter generator 11
~Input signal 1 due to p6! +13+Q2+Q3, respectively, and the output signal 1. ' , 13 +Q
ffi'IQ3' is sent in parallel to the orthogonal amplitude modulation section 2, and the multi-level QAM signal is output from the orthogonal amplitude modulation section 2. 1. is the upper signal of the exclusive OR circuit 13. , Q, are code-processed EX-ORI (
7) Output 1.1 is roughly determined by the output g, l of EX-OR, EX-OR, +71 output I, f and EX-
OR4 (7) Output Q.

' is determined by the two selected outputs of the selection circuit 12, so the selected output of the selection circuit 12, that is, the upper output 1 of the output phases p, ~p of the PNN butter generator 11; l++
pm and lower output ρ1. By selecting an appropriate combination of two outputs from the four outputs of p8 using the selection signal SEL,
Input signal 11112113101+Q2 of signal processing unit 1
Even if the content of +03 changes and the ripple Δp of the multi-level QAM signal output is about to increase, it is possible to suppress the increase in the ripple Δp, thereby maintaining the line quality and solving the problem.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a digital signal processing circuit according to an embodiment of the present invention, and FIG. 3 is a spectrum diagram of a multilevel AM signal output for explaining its operation.
FIG. 4 is a signal point constellation diagram for a multi-value QAM signal, and both are examples in which the multi-value QAM signal is a 64-value QAM signal. In the block diagram of the embodiment shown in FIG. 2, circuits and symbols having the same numbers as in the conventional example shown in FIG. 5 have the same configuration and function.

There is a relationship between the ripple Δp in FIG. 3, which represents the spectrum of the output IF of the 64-value QAM signal output from the quadrature amplitude modulator 2 in FIG. 2, and the arrangement of signal points in FIG. When 64 signal points exist with approximately equal probability as shown in Figure (a), the ripple Δp is small as shown in Figure 3 (a), but it becomes as shown in Figure 4 (°C). If the probability of existence of a signal point at a specific point becomes large (or the signal points are arranged unevenly), the ripple Δp becomes large as shown in FIG. 3(b).
The size of a point in FIG. 4 represents the probability of existence of a signal point. ) and I for the bias of the 64-value QAM signal point
The influence of the channel signal power 11+h+I:It and the Q channel signal power Q, , Q2, is largely influenced by the upper bits I1+I of the I channel and the Q channel. Therefore, the signal input IZ of the middle and lower bits of the I channel and Q channel
+13+ and signal input Q2. The output phases p3 to p of the PNN butter generator 11 with respect to Q:l are fixed, and the upper bits 1. and Q, only the output phase of the PNN butter generator 11 is made variable, and its upper output 11t+pg and lower output 1)? +98 outputs, an appropriate combination of two outputs is selected and output by a selection signal SEL.

The comparison/control unit 10 is composed of a comparison unit 10cI that compares and detects an input ripple value Δp with a reference value Δp3, and a control unit 10o2 that generates a control signal C based on the detection signal, and the comparison unit 10c1 is a quadrature amplitude modulation unit. If the ripple value Δp of the 64-value QAM signal output IF of the output of 2 is detected, and the ripple value Δp is larger than the reference value Δp,l, the selection circuit 1
In the 4-man powered 2-output selector of 2, the upper output p++ pz and lower output fh+ pa of the PNN butter generator 11
An appropriate combination of two outputs is selected from the four outputs of
The scrambled binary signal 11 is sent to EX-OR4 and scrambled.
'+QI' is output. And exclusive OR circuit 13
) other, EX-ORZ and IEX-OR, + and EX-
OR, and EX-OR & (7) Processing output 1! 'lI3
' + Q2'Q! ' together with the quadrature amplitude modulator 2 to suppress an increase in the ripple value Δp of the output IF of the 64-value CAM signal output from the quadrature amplitude modulator 2. Therefore, in the digital signal processing circuit of the embodiment shown in FIG.
Even when the ripple value Δp is about to increase, the increase in the ripple value Δp is suppressed, so the line quality is maintained and there is no problem.

〔Effect of the invention〕

As explained above, according to the present invention, for an input binary signal that increases the ripple value Δp of a multilevel QAM signal output, by changing the scrambling process, the increase in the ripple value Δp is suppressed, The effect of maintaining line quality by reducing the adverse effects on clock recovery and carrier recovery on the receiving side can be obtained.

FIG. 1 is a principle diagram showing the configuration of a digital signal processing circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of a digital signal processing circuit according to an embodiment of the present invention, and FIG. 3 is an operation diagram of the embodiment of the present invention. Multivalued Q to explain
FIG. 4 is a spectrum diagram of an AM signal output, FIG. 4 is a signal point arrangement diagram of a 64-value QAM signal for explaining the operation of an embodiment of the present invention, and FIG. 5 is a block diagram of a conventional digital signal processing circuit.

In the figure, 1 is a signal processing section, 10 is a comparison/control section, 11 is a PN pattern generator, 12 is a selection circuit, 13 is an exclusive OR circuit, and 2 is a quadrature amplitude modulation section.

[Brief explanation of the drawing]

Claims (1)

[Claims] A transmitting side for performing multi-level QAM modulation on an input binary signal.
Speed conversion etc. are performed on the value digital signal to create a predetermined plurality of data signal sequences (in the case of 64-value QAM, 6 signal sequences of 3 sequences each, I_1, I_2, I_3, Q_1, Q_2, Q
_3) is input in parallel and scrambled by a circuit (13) that takes an exclusive OR with the output code of the PN pattern generator (11), which generates a pseudo-random code at the cycle of the input signal to prevent the same code from continuing. A predetermined number of processed signal sequences are converted into an I-channel analog signal (A_I) and a Q-channel analog signal (A_Q) by two D/A converters (21, 22), respectively, and then sent to mixers (31, 22). 32)
The carrier wave oscillator (4) is branched from the carrier wave oscillator (4) at the orthogonal hybrid (5) and mixed with the input carrier waves with a mutual phase difference of π/2, frequency converted to a signal with a constant center frequency, amplitude modulated, and the hybrid (6) In a digital signal processing circuit (1) that outputs a synthesized multi-value QAM modulated signal, the ripple (Δ) of the amplitude of the multi-value QAM modulated output signal is
a comparison/control unit (10) that compares and detects p) and generates a control signal (C), and uses the control signal (C) output from the comparison/control unit (10) as a selection signal (SEL) to generate the PN pattern. The upper outputs (p_1, p_2) of the output codes (p_1 to p_8) of the device (11)
) and lower outputs (p_7, p_8) in an appropriate combination.
A selection circuit (12) for selecting a signal is provided, and the selection circuit (12) is provided in the exclusive OR circuit (13).
) and the plurality of series of binary signal inputs (I_
1, I_2, I_3, Q_1, Q_2, Q3) with the upper signal (I_1, Q_1) and the remaining intermediate output (p_3) from the PN pattern generation circuit (11).
~p_6) and the plurality of series of binary signal inputs (I_1, I
_2, I_3, Q_1, Q_2, Q_3) lower signal (
A digital signal processing circuit characterized in that it performs an exclusive OR with I_2, I_3, Q_2, Q_3) and outputs the result.