JPH02148485U - - Google Patents
Info
- Publication number
- JPH02148485U JPH02148485U JP5759589U JP5759589U JPH02148485U JP H02148485 U JPH02148485 U JP H02148485U JP 5759589 U JP5759589 U JP 5759589U JP 5759589 U JP5759589 U JP 5759589U JP H02148485 U JPH02148485 U JP H02148485U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- signal line
- phase reference
- under test
- boards
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第1図はこの考案の一実施例を示す接続図、第
2図はこの考案によつて付加した信号線路とコネ
クタを用いてパフオーマンスボードに実装した位
相基準信号伝送路の可変遅延素子の遅延時間を調
整する方法を説明するための接続図、第3図は従
来の技術を説明するための接続図である。
10A〜10N……パフオーマンスボード、1
1……駆動回路、12……信号取込回路、13,
18……リレー接点、14……入出力端子、15
……分配器、16,17……可変遅延素子、20
……被試験IC、30……位相基準信号入力点、
31……信号線路、32……コネクタ。
Figure 1 is a connection diagram showing an embodiment of this invention, and Figure 2 shows the delay time of the variable delay element of the phase reference signal transmission line mounted on a performance board using the signal line and connector added according to this invention. FIG. 3 is a connection diagram for explaining a conventional technique. 10A~10N...Performance board, 1
1... Drive circuit, 12... Signal acquisition circuit, 13,
18... Relay contact, 14... Input/output terminal, 15
...Distributor, 16, 17...Variable delay element, 20
...IC under test, 30...Phase reference signal input point,
31...Signal line, 32...Connector.
Claims (1)
験ICから出力される信号を取込む信号取込回路
とが複数実装された複数のボードと、 B この複数のボードの各駆動回路及び信号取込
回路の接続点に位相基準信号を与える分配器と、 C 上記複数のボードのそれぞれに設けられ、各
ボードの位相基準信号入力点に与えられる位相基
準信号を直接取出すための信号線路及びこの信号
線路から位相基準信号を取出すコネクタと、 を具備して成るIC試験装置。[Scope of Claim for Utility Model Registration] A. A plurality of boards on which a plurality of drive circuits for supplying to the terminals of the IC under test and a plurality of signal acquisition circuits for receiving signals output from the IC under test are mounted, and B. The plurality of boards. A distributor that provides a phase reference signal to the connection point of each drive circuit and signal acquisition circuit; An IC testing device comprising: a signal line for the signal line and a connector for extracting a phase reference signal from the signal line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5759589U JPH0714929Y2 (en) | 1989-05-19 | 1989-05-19 | IC test equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5759589U JPH0714929Y2 (en) | 1989-05-19 | 1989-05-19 | IC test equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02148485U true JPH02148485U (en) | 1990-12-17 |
JPH0714929Y2 JPH0714929Y2 (en) | 1995-04-10 |
Family
ID=31582447
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5759589U Expired - Fee Related JPH0714929Y2 (en) | 1989-05-19 | 1989-05-19 | IC test equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0714929Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005091108A (en) * | 2003-09-16 | 2005-04-07 | Advantest Corp | Jitter generator and testing apparatus |
-
1989
- 1989-05-19 JP JP5759589U patent/JPH0714929Y2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005091108A (en) * | 2003-09-16 | 2005-04-07 | Advantest Corp | Jitter generator and testing apparatus |
Also Published As
Publication number | Publication date |
---|---|
JPH0714929Y2 (en) | 1995-04-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |