JPH02145852U - - Google Patents
Info
- Publication number
- JPH02145852U JPH02145852U JP5566589U JP5566589U JPH02145852U JP H02145852 U JPH02145852 U JP H02145852U JP 5566589 U JP5566589 U JP 5566589U JP 5566589 U JP5566589 U JP 5566589U JP H02145852 U JPH02145852 U JP H02145852U
- Authority
- JP
- Japan
- Prior art keywords
- output circuit
- voltage
- line monitoring
- monitoring circuit
- fax line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例を示す回路図であ
る。第２図は従来のフアツクスの回線監視回路を
示す回路図である。
図において、１２および１４……電話回線端子
、１６および１８……フアツクス端子、２０……
全波整流ブリツジ、２２……直流増幅器、３２，
３８および５２……比較器、４４……信号端子、
６０……ブランチ信号端子を示す。
FIG. 1 is a circuit diagram showing an embodiment of this invention. FIG. 2 is a circuit diagram showing a conventional fax line monitoring circuit. In the figure, 12 and 14... telephone line terminals, 16 and 18... fax terminals, 20...
Full-wave rectifier bridge, 22...DC amplifier, 32,
38 and 52... comparator, 44... signal terminal,
60... indicates a branch signal terminal.
Claims (1)
力するための直流電圧出力回路、および、 前記直流電圧出力回路からの直流電圧が所定の
範囲内にあるときに信号を出力するための信号出
力回路を備える、フアツクスの回線監視回路。 ２ 前記直流電圧出力回路は高抵抗を介して前記
２線間に接続される全波整流ブリツジを含む、請
求項１記載のフアツクスの回線監視回路。 ３ 前記信号出力回路はウインドコンパレータを
含む、請求項１または２記載のフアツクスの回線
監視回路。[Claims for Utility Model Registration] 1. A DC voltage output circuit connected between two lines of a telephone line to output DC voltage, and when the DC voltage from the DC voltage output circuit is within a predetermined range. A fax line monitoring circuit equipped with a signal output circuit for outputting signals to. 2. The fax line monitoring circuit according to claim 1, wherein said DC voltage output circuit includes a full-wave rectifier bridge connected between said two lines via a high resistance. 3. The fax line monitoring circuit according to claim 1 or 2, wherein the signal output circuit includes a window comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5566589U JPH02145852U (en) | 1989-05-15 | 1989-05-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5566589U JPH02145852U (en) | 1989-05-15 | 1989-05-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02145852U true JPH02145852U (en) | 1990-12-11 |
Family
ID=31578821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5566589U Pending JPH02145852U (en) | 1989-05-15 | 1989-05-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02145852U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62260460A (en) * | 1986-05-02 | 1987-11-12 | Nec Corp | Terminal equipment |
-
1989
- 1989-05-15 JP JP5566589U patent/JPH02145852U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62260460A (en) * | 1986-05-02 | 1987-11-12 | Nec Corp | Terminal equipment |
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