JPH02141572A - Method and device for bias sputtering - Google Patents

Method and device for bias sputtering

Info

Publication number
JPH02141572A
JPH02141572A JP29456688A JP29456688A JPH02141572A JP H02141572 A JPH02141572 A JP H02141572A JP 29456688 A JP29456688 A JP 29456688A JP 29456688 A JP29456688 A JP 29456688A JP H02141572 A JPH02141572 A JP H02141572A
Authority
JP
Japan
Prior art keywords
voltage
substrate
target
film
sputtering method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29456688A
Other languages
Japanese (ja)
Inventor
Masayasu Nihei
二瓶 正恭
Hitoshi Onuki
仁 大貫
Yasushi Kawabuchi
靖 河渕
Kunio Miyazaki
邦夫 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP29456688A priority Critical patent/JPH02141572A/en
Publication of JPH02141572A publication Critical patent/JPH02141572A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the damage of a substrate and to efficiently form a film thereon by impressing a square wave high-frequency voltage which can independently change the peak values of the negative polarity voltage and positive polarity voltage and energization time to the substrate and sputtering a target. CONSTITUTION:The target 11 having magnets 15 on the rear surface and the substrate 12 are disposed to face each other in a vacuum vessel 14. The above-mentioned vacuum vessel 14 is grounded and a sputtering voltage is impressed from a power source 10 to the target 11 and a bias voltage is impressed to the substrate 12 to sputter the target 11 and to form the film on the substrate 12. The above-mentioned bias voltage is impressed to the target from positive and negative polarity constant voltage power sources 1, 3 in the above-mentioned sputtering method. Voltage setting potentiometers 2, 4 are respectively provided to these power sources 1, 3 and the absolute value of the peak voltage of the negative polarity voltage is set higher than the peak value of the positive polarity voltage. Further, the voltage is set to the square wave which is longer in the energization time of the negative polarity than the energization time of the positive polarity by a waveform controller 5 and positive and negative polarity switching transistors 8, 9. The damage of the substrate 12 by electron bombardment is prevented in this way.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、バイアススパッタリングによる薄膜形成法と
装置に係り、特に、半導体段差部上のカバレッジの向−
りを図るバイアススパッタリング法およびその装置に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method and apparatus for forming a thin film by bias sputtering, and particularly to a method and apparatus for forming a thin film by bias sputtering.
The present invention relates to a bias sputtering method and an apparatus for the same.

〔従来の技術〕[Conventional technology]

半導体装置の集積度が進むと、シリコン基板とアルミニ
ウム配線間のコンタクトホールやアルミニウム配線間の
スルーホール径が小さくなり、アスペクト比が大きくな
ってくる。一般に用いられる直流マグネトロンスパッタ
法では、アスペクト比が1に近づいてくると配線材料の
スパッタ付着時のシャ1ヘーウイグ効果により、ステッ
プカバレージか悪くなり、配線抵抗の増大やエレクトロ
マイグレーション、ストレスマイグレーションなどの断
線が発生しやすくなる。これを改善するため真空容器を
アースとし、ターゲラ(−と基板に負の電圧を印加しな
がら膜形成するバイアススパッタ法が開発された。第5
図はその一例で直流バイアススパッタ法の原理を示して
いる。jl(板12とターゲット11には、それぞれ、
独立に負の電圧が印加されているため、基板はΔr・イ
オン衝撃()φスパッタ)を受けながら膜が形成される
。このjφスパッタ効果によりステップカバレージを改
善できる。
As the degree of integration of semiconductor devices increases, the diameters of contact holes between a silicon substrate and aluminum wiring and through holes between aluminum wiring become smaller, and the aspect ratio becomes larger. In the commonly used DC magnetron sputtering method, as the aspect ratio approaches 1, the step coverage deteriorates due to the sheer force effect during sputtering of wiring material, which increases wiring resistance and causes disconnections such as electromigration and stress migration. is more likely to occur. To improve this, a bias sputtering method was developed in which the vacuum chamber is grounded and a film is formed while applying a negative voltage to the target layer (-) and the substrate.
The figure shows an example of the principle of DC bias sputtering. jl (The board 12 and target 11 each have
Since a negative voltage is applied independently, a film is formed on the substrate while being subjected to Δr・ion bombardment ()φ sputtering). This jφ sputtering effect can improve step coverage.

図中16はバイアス電源。16 in the figure is a bias power supply.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、このようなバイアススパッタ法では、Si基板
は一般に絶縁膜S j、 02で被覆されているのでA
Q膜がある程度形成されなければバイアス電流は基板に
流れないため、バイアスの効果が得られない。また、膜
形成初期時は絶縁体であるため、チャージアップ(帯電
)する。これらが原因で異常放電を起し基板が破損する
ことがしばしば起る。基板の損傷、破損を軽減するため
、ある程度AQ膜が形成されてから基板に負のバイアス
電圧を与えて膜を形成している。しかし、これではバイ
アスの効果を十分得られず、ステップカバレージや膜質
を十分改善することはできない。また、特開昭61−2
64174号公報では、第6図に示すように、負のバイ
アス電圧を周期的にほぼ接地レベルに戻して、載板表面
に電子を流入させて基板のチャージアンプを改善してい
る。しかし、この方式では基板が接地レベルまで回復す
るのに時間がかかり、十分な解決策とはいえない。また
、第7図に示す波形のように、交流(高周波)を基板に
印加し絶縁体でもバイアススパッタができる方式もある
。しかし、波形が示すように、基板が正極時に加速され
た電子が基板に流れこむため、基板は電子衝撃を受け、
加熱し損傷するなどの欠点がある。
However, in such a bias sputtering method, since the Si substrate is generally covered with an insulating film Sj,02,
Unless the Q film is formed to some extent, the bias current will not flow to the substrate, and therefore no bias effect will be obtained. Furthermore, since the film is an insulator at the initial stage of film formation, it is charged up. These factors often cause abnormal discharge and damage to the board. In order to reduce damage and breakage of the substrate, after the AQ film has been formed to some extent, a negative bias voltage is applied to the substrate to form the film. However, with this method, the bias effect cannot be sufficiently obtained, and step coverage and film quality cannot be sufficiently improved. Also, JP-A-61-2
In Japanese Patent No. 64174, as shown in FIG. 6, the negative bias voltage is periodically returned to approximately the ground level to cause electrons to flow into the surface of the mounting plate, thereby improving the charge amplifier of the substrate. However, this method takes time for the board to recover to ground level, so it is not a sufficient solution. Furthermore, as shown in the waveform shown in FIG. 7, there is also a method in which bias sputtering can be performed even on insulators by applying alternating current (high frequency) to the substrate. However, as the waveform shows, when the substrate is a positive electrode, accelerated electrons flow into the substrate, so the substrate receives an electron bombardment.
It has drawbacks such as heating and damage.

〔課題を解決するための手段〕[Means to solve the problem]

上記の課題を解決するため、本発明による膜形成方法で
は、基板に周期的に極性の異なる方形波電圧を交互に印
加し、その電圧波形を負極性のピーク値より正極性の電
圧が低いか、または、負極性の通電時間が正極性の通電
時間よりも長くする。
In order to solve the above problems, in the film forming method according to the present invention, square wave voltages of different polarities are periodically applied to the substrate alternately, and the voltage waveform is changed to a point where the positive polarity voltage is lower than the negative polarity peak value. Or, the negative polarity energization time is made longer than the positive polarity energization time.

〔作用〕[Effect]

第7図のように、交流波形を基板に印加することにより
チャージアップを防ぐことができる。しかし、基板が正
極時に加速された電子が基板を衝撃し、基板を損傷する
という新たな問題が生しる。
As shown in FIG. 7, charge-up can be prevented by applying an AC waveform to the substrate. However, a new problem arises in that when the substrate is a positive electrode, accelerated electrons impact the substrate and damage the substrate.

この電子エネルギをできるだけ少なくするため、本発明
では第1図のバイアス電圧の波形が示すように、波形を
方形波にして、正極性のピーク電圧を負極時に比べて低
くし、また、通電時間を負極時より短くすることにより
、電子衝撃とチャージアップによる基板の損傷を防いで
いる。
In order to reduce this electron energy as much as possible, in the present invention, as shown in the bias voltage waveform in Figure 1, the waveform is made into a square wave, the peak voltage of the positive polarity is lower than that of the negative polarity, and the energization time is By making the length shorter than that for the negative electrode, damage to the substrate due to electron impact and charge-up is prevented.

〔実施例〕〔Example〕

第1図、第2図を参照して本発明による膜形成装置の実
施例を示す。第1図の上は本発明のバイアス波形の模式
図である。ここで、NVを基板12が負極時のピーク電
圧、Pvを正極時のピーク電圧、T1を負極時の通電時
間、T2を正極時の通電時間とし、PV/NVをバイア
ス電圧比、T2/ (T1+T2)をバイアス通電比と
する。
An embodiment of a film forming apparatus according to the present invention will be shown with reference to FIGS. 1 and 2. The upper part of FIG. 1 is a schematic diagram of the bias waveform of the present invention. Here, NV is the peak voltage when the substrate 12 is the negative electrode, Pv is the peak voltage when the substrate 12 is the positive electrode, T1 is the energizing time when the negative electrode is, T2 is the energizing time when the substrate 12 is the positive electrode, PV/NV is the bias voltage ratio, and T2/ ( T1+T2) is the bias energization ratio.

第2図で3は負極時の電圧を基板12に供給するための
定電圧制御電源、4は、その電圧を設定するだめのポテ
ンショメータ、1は正極時の電圧を基板に供給するため
の定電圧電源、2はその電圧を設定するためのポテンシ
ョメータ、5は波形制御装置、6は負極と正極の通電比
を設定するためのポテンショメータ、7は周波数設定用
ポテンショメータ、9は波形制御装置からの信号により
4で設定された負の電圧を周期的に基板を供給するスイ
ッチングトランジスタ、8は基板に正の電圧を周期的に
供給するためのスイッチングトランジスタ、このように
構成された薄膜形成装置で、まず、波形制御装置5のポ
テンショメータ6で負極性と正極性の通電比、7で周波
数を設定する。また、負極のピーク電圧を負極用定電圧
電源のポテンショメータ4でピーク電圧NVを設定する
。また、正極のピーク電圧PVをポテンショメータ2で
設定する。また、波形制御装置5で設定されたそれぞれ
の通電時間の信号はスイッチングトランジスタ8,9に
供給され、それぞれ設定された電圧を設定された時間だ
け交互にオン、オフし、負極、正極の電圧を交互に基板
に印加する。以下、第2図で示した薄膜形成装置による
薄膜形成について説明する。初めに、膜損傷に及ぼすバ
イアス電圧比PV/NVの影響について説明する。基板
12、膜面の損傷はチャージアップ、電子衝撃、異常放
電によって起るが、これを定量的に表現することは困難
なので、目測で確認できるものを有り、無しとして判定
した。膜形成条件は、Ar’4囲気圧カニ 2 X 1
0−8Torr、負極電圧N V : 300V、正極
電圧PV:O〜300V、バイアス電圧比PV/NV:
O〜1、バイアス通電比T2/(T1+T2):0.5
、周波数:100KHz、ターゲット:AQ−1%Si
、スパッタ電カニ1.5  KWで膜形成した。その結
果、バイアス電圧比PV/NVが0.03〜0.2すな
わち、正極電圧P、Vが10〜60Vの範囲であればチ
ャージアップや電子衝撃などによる膜の損傷を完全に防
げることがわかった。つぎに、バイアス通電比T2/(
T1+T2)の影響について説明する。負極電圧NV:
300V、正極電圧PV:300Vと一定にし、バイア
ス通電比T 2/(T 1 +T 2)を0〜0.5に
変えた結果、バイアス通電比は0.07〜0.15 の
範囲にあれば膜の損傷を防止できた。
In Fig. 2, 3 is a constant voltage control power supply for supplying the negative voltage to the board 12, 4 is a potentiometer for setting the voltage, and 1 is a constant voltage for supplying the positive voltage to the board. Power supply, 2 is a potentiometer for setting the voltage, 5 is a waveform control device, 6 is a potentiometer for setting the energization ratio of negative and positive electrodes, 7 is a frequency setting potentiometer, 9 is a signal from the waveform control device A switching transistor 4 periodically supplies a negative voltage to the substrate, and a switching transistor 8 periodically supplies a positive voltage to the substrate. The potentiometer 6 of the waveform control device 5 sets the energization ratio of negative polarity and positive polarity, and the frequency is set at 7. Further, the peak voltage NV of the negative electrode is set using the potentiometer 4 of the constant voltage power source for the negative electrode. Further, the peak voltage PV of the positive electrode is set by the potentiometer 2. In addition, the signals for the respective energization times set by the waveform control device 5 are supplied to the switching transistors 8 and 9, which turn the respective set voltages on and off alternately for the set time, thereby changing the voltages at the negative and positive poles. Apply voltage alternately to the substrate. Thin film formation using the thin film forming apparatus shown in FIG. 2 will be described below. First, the influence of the bias voltage ratio PV/NV on film damage will be explained. Damage to the substrate 12 and film surface occurs due to charge-up, electron impact, and abnormal discharge, but since it is difficult to express this quantitatively, it was determined that there was damage that could be confirmed by visual measurement and that there was no damage. The film formation conditions were Ar'4 ambient pressure crab 2 x 1
0-8 Torr, negative electrode voltage NV: 300V, positive electrode voltage PV: O to 300V, bias voltage ratio PV/NV:
O~1, bias energization ratio T2/(T1+T2): 0.5
, Frequency: 100KHz, Target: AQ-1%Si
A film was formed using a sputter electric crab at 1.5 KW. As a result, it was found that when the bias voltage ratio PV/NV is in the range of 0.03 to 0.2, that is, the positive electrode voltages P and V are in the range of 10 to 60 V, damage to the film due to charge-up and electron impact can be completely prevented. Ta. Next, bias energization ratio T2/(
The influence of T1+T2) will be explained. Negative electrode voltage NV:
As a result of keeping the positive electrode voltage PV constant at 300V and 300V and changing the bias energization ratio T 2 / (T 1 + T 2) from 0 to 0.5, the bias energization ratio is in the range of 0.07 to 0.15. Damage to the membrane could be prevented.

このように、バイアス通電比、バイアス電圧比を変える
ことにより、膜の損傷を防ぐことができる。
In this way, by changing the bias current ratio and bias voltage ratio, damage to the film can be prevented.

また、従来方式の直流バイアススパッタ法で上記の例と
ほぼ同じ条件(基板に300vの負の電圧を印加)で膜
を形成した結果、基板はチャージアップにより異常放電
し、基板12は割れ使用に耐えるものはできなかった。
In addition, as a result of forming a film using the conventional DC bias sputtering method under almost the same conditions as the above example (applying a negative voltage of 300 V to the substrate), the substrate caused abnormal discharge due to charge-up, and the substrate 12 cracked and became unusable. I couldn't bear it.

また、従来法でチャージアップによる割れを防ぐため、
膜形成開始後−分間バイアス(300V負電圧)を基板
12に印加せずにAQ膜を形成し、その後、バイアスを
印加したものと段差被覆性を本発明と比較した結果、本
発明は従来法に比べてステップカバレージは約15%向
上した。
In addition, in order to prevent cracking due to charge-up in the conventional method,
After the start of film formation, an AQ film was formed without applying a bias (300V negative voltage) to the substrate 12 for a minute, and then a bias was applied.As a result of comparing the step coverage with the present invention, the present invention was found to be superior to the conventional method. The step coverage was improved by about 15% compared to the previous model.

なお、図中、10はスパッタ電源、11はターゲラ1〜
.13は絶縁物、14は真空容器、15は磁石である。
In addition, in the figure, 10 is a sputtering power supply, 11 is a targeter 1~
.. 13 is an insulator, 14 is a vacuum container, and 15 is a magnet.

1実施例2」 本発明を絶縁膜の膜形成に適用した例を説明する。絶縁
膜をスパッタで膜形成するにはチャージアップを防止す
るため絶縁ターゲラ1〜に第7図に示すような高周波を
印加しなければならない。しかし、正極電圧はチャージ
アップに対し有効であるがスパッタによる膜形成には関
与せず、はとんど熱エネルギになりターゲットを加熱す
る。ターゲットとバッキングシートは、一般に、インジ
ューム半田で接合されているため、スパッタ電力を増加
するとターゲットがはくすすることがしばしばおこる。
1 Example 2 An example in which the present invention is applied to the formation of an insulating film will be described. To form an insulating film by sputtering, it is necessary to apply a high frequency wave as shown in FIG. 7 to the insulating targeters 1 to 1 to prevent charge-up. However, although the positive electrode voltage is effective against charge-up, it does not participate in film formation by sputtering, and mostly becomes thermal energy to heat the target. Since the target and the backing sheet are generally bonded using indium solder, increasing the sputtering power often causes the target to peel off.

しかし、本発明では負電圧に比へ正電圧を低くして交互
に印加するため、従来法に比ベスパツタ電力を1.4 
倍ターゲットに供給できる。
However, in the present invention, since a positive voltage is applied alternately with a lower ratio to a negative voltage, the specific Vesputter power is 1.4 compared to the conventional method.
Can be supplied to twice the target.

これにより、膜形成速度が向−ヒし、作業能率が向上す
る。
This increases the film formation rate and improves work efficiency.

「実施例3」 基板に印加する電圧とターゲットに印加する電圧を交互
にスイッチングし、その通電比を変えることにより、ス
テップカバレージと膜質を向−ヒさせるバイアススパッ
タ法において、第3図、第4図に示すように、基板、あ
るいは、基板とターゲットに本発明の波形を印加し交互
にスイッチングし膜形成することにより、従来法に比べ
よりステップカバレッジと膜質を向上させることができ
る。
"Example 3" In the bias sputtering method, step coverage and film quality are improved by alternately switching the voltage applied to the substrate and the voltage applied to the target and changing the energization ratio. As shown in the figure, step coverage and film quality can be improved compared to conventional methods by applying the waveform of the present invention to the substrate or to the substrate and target and alternately switching to form a film.

また、ターゲラ1−には従来波形の高周波を印加するこ
ともできる。
Further, it is also possible to apply a conventional high frequency waveform to the target laser 1-.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、 (1)チャージアップと電子衝撃による膜の損傷を防止
でき、 (2)従来法に比ベバイアスの効果が大きく、ステップ
カバレッジが向上し、 (3)ターゲラ1−とバッキングシートとの接合部のは
くりを防ぐことができ、 (4)膜形成速度を向上させることができる。
According to the present invention, (1) damage to the film due to charge-up and electron impact can be prevented; (2) the bias effect is greater compared to the conventional method and step coverage is improved; and (3) Targetera 1 and backing sheet. (4) It is possible to improve the film formation rate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の膜形成装置の一実施例の系統図、第2
図は本発明の波形の模式図、第3図、第4図は本発明の
波形の模式図、第5図は従来バイアススパッタ法の説明
図、第6図、第7図は従来バイアススパッタ法の波形の
模式図である。 1・・・正極定電圧電源、2・・正極電圧設定ポテンシ
ョメータ、3・・・負極定電圧電源、4・・・負極電圧
設定ポテンショメータ、5・・・波形制御装置、6 ・
通電比設定ポテンショメータ、7・・周波設定ポテンシ
ョンメータ、8・・・正極スイッチングトランジスタ、
9・・・負極スイッチング1ヘランジスタ、10・・・
スパッタ電源、11・・・ターゲット、12基板、13
・・・絶縁物、14 ・真空容器、15・磁石。
FIG. 1 is a system diagram of an embodiment of the film forming apparatus of the present invention, and FIG.
The figure is a schematic diagram of the waveform of the present invention, Figures 3 and 4 are schematic diagrams of the waveform of the present invention, Figure 5 is an explanatory diagram of the conventional bias sputtering method, and Figures 6 and 7 are the conventional bias sputtering method. FIG. DESCRIPTION OF SYMBOLS 1... Positive electrode constant voltage power supply, 2... Positive electrode voltage setting potentiometer, 3... Negative electrode constant voltage power supply, 4... Negative electrode voltage setting potentiometer, 5... Waveform control device, 6.
Energization ratio setting potentiometer, 7... Frequency setting potentiometer, 8... Positive switching transistor,
9... Negative switching 1 helang resistor, 10...
Sputter power supply, 11... target, 12 substrate, 13
...Insulator, 14 - Vacuum container, 15 - Magnet.

Claims (1)

【特許請求の範囲】 1、真空容器をアースとし、前記真空容器内に対向して
配置されたターゲットと基板に電圧を印加して膜形成す
るバイアススパッタ法において、前記基板に負極電圧と
正極電圧のピーク値および前記負極電圧と前記正極電圧
の通電時間を独立に変えられる方形波高周波電圧を印加
して膜形成することを特徴とするバイアススパッタリン
グ法。 2、特許請求項第1項において、 前記負極電圧の前記ピーク値の絶対値が前記正極電圧の
前記ピーク値より高いことを特徴とするバイアススパッ
タリング法。 3、特許請求項第1項において、 負極性の通電時間が正極性の通電時間より長いことを特
徴とするバイアススパッタリング法。 4、特許請求項第1項、第2項または第3項において、 ターゲットに印加する電圧を第1項から第3項の電圧波
形か、または直流あるいは高周波とすることを特徴とす
るバイアススパッタリング法。 5、真空容器および基板をアースとし、ターゲットに電
圧を印加し膜形成するスパッタリング法において、 前記ターゲットに電圧波形を印加して膜形成することを
特徴とするスパッタリング法。 6、真空容器をアースとし、前記真空容器内に対向して
配置された基板とターゲットに独立に設定された電圧を
交互に印加し、スパッタリングと逆スパッタリングを交
互にくり返して前記基板上に前記ターゲットを堆積する
方法において、電圧波形を前記基板に印加し、この電圧
とスパッタ電圧を交互にスイッチングし膜形成すること
を特徴とするバイアススパッタリング法。 7、特許請求項第6項において、 前記ターゲットに供給する前記スパッタ電圧を基板電圧
と交互にスイッチングされた波形か、または、交互にス
イッチングされた直流あるいは高周波とすることを特徴
とするバイアススパッタリング法。 8、特許請求項第6項または第7項において、前記交互
にスイッチングされた基板電圧とターゲット電圧にはベ
ース電圧を含むことを特徴とするバイアススパッタリン
グ法。 9、特許請求項第6項、第7項または第8項において、 前記基板と前記ターゲットに交互に印加する電圧とその
通電時間およびベース電圧を独立に任意に変えられるこ
とを特徴とするバイアススパッタリング法。 10、通電比、周波数を任意に設定できる波形制御装置
と、負電圧、正電圧を独立に設定できる電源および半導
体スイッチとからなり、設定された正、負の電圧を前記
波形制御装置からの信号により、半導体スイッチを交互
にスイッチングし、設定された電圧の極性を変えること
を特徴とする膜形成用電源装置。
[Claims] 1. In a bias sputtering method in which a vacuum vessel is grounded and a voltage is applied to a target and a substrate placed facing each other in the vacuum vessel to form a film, a negative electrode voltage and a positive electrode voltage are applied to the substrate. A bias sputtering method characterized in that a film is formed by applying a square wave high frequency voltage that can independently change the peak value of and the energization time of the negative electrode voltage and the positive electrode voltage. 2. The bias sputtering method according to claim 1, wherein the absolute value of the peak value of the negative electrode voltage is higher than the peak value of the positive electrode voltage. 3. The bias sputtering method according to claim 1, wherein the negative polarity current application time is longer than the positive polarity current application time. 4. A bias sputtering method according to claim 1, 2, or 3, characterized in that the voltage applied to the target has the voltage waveform of claims 1 to 3, direct current, or high frequency. . 5. A sputtering method in which a vacuum container and a substrate are grounded, and a voltage is applied to a target to form a film, the sputtering method being characterized in that the film is formed by applying a voltage waveform to the target. 6. With the vacuum container grounded, independently set voltages are alternately applied to the substrate and the target, which are placed facing each other in the vacuum container, and sputtering and reverse sputtering are alternately repeated to form the target on the substrate. A bias sputtering method characterized in that a voltage waveform is applied to the substrate and the voltage and the sputtering voltage are alternately switched to form a film. 7. The bias sputtering method according to claim 6, characterized in that the sputtering voltage supplied to the target is a waveform alternately switched with the substrate voltage, or a direct current or high frequency alternately switched. . 8. The bias sputtering method according to claim 6 or 7, wherein the alternately switched substrate voltage and target voltage include a base voltage. 9. Bias sputtering according to claim 6, 7, or 8, characterized in that the voltage alternately applied to the substrate and the target, the energization time, and the base voltage can be independently and arbitrarily changed. Law. 10. Consists of a waveform control device that can arbitrarily set the energization ratio and frequency, a power supply and a semiconductor switch that can independently set negative and positive voltages, and converts the set positive and negative voltages into signals from the waveform control device. A power supply device for film formation, characterized in that the polarity of a set voltage is changed by alternately switching semiconductor switches.
JP29456688A 1988-11-24 1988-11-24 Method and device for bias sputtering Pending JPH02141572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29456688A JPH02141572A (en) 1988-11-24 1988-11-24 Method and device for bias sputtering

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29456688A JPH02141572A (en) 1988-11-24 1988-11-24 Method and device for bias sputtering

Publications (1)

Publication Number Publication Date
JPH02141572A true JPH02141572A (en) 1990-05-30

Family

ID=17809445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29456688A Pending JPH02141572A (en) 1988-11-24 1988-11-24 Method and device for bias sputtering

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Country Link
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5922180A (en) * 1995-12-04 1999-07-13 Nec Corporation Sputtering apparatus for forming a conductive film in a contact hole of a high aspect ratio
JP2000256845A (en) * 1999-03-12 2000-09-19 Anelva Corp Formation of thin film and thin film forming device
JP2010229428A (en) * 2009-03-25 2010-10-14 Tsuru Gakuen Magnetron sputtering device and method for manufacturing electronic component
EP0692138B2 (en) 1993-04-02 2014-10-22 Advanced Energy Industries, Inc. Reactive dc sputtering system
TWI494967B (en) * 2011-07-28 2015-08-01 Advanced Energy Ind Inc System, apparatus and method for plasma-based processing
JP2019513903A (en) * 2016-04-22 2019-05-30 エリコン サーフェス ソリューションズ アーゲー、 プフェフィコン TiCN with reduced growth defects using HiPIMS
US10811228B2 (en) 2017-11-17 2020-10-20 Advanced Energy Industries, Inc. Control of plasma processing systems that include plasma modulating supplies
US11670487B1 (en) 2022-01-26 2023-06-06 Advanced Energy Industries, Inc. Bias supply control and data processing
US11842884B2 (en) 2017-11-17 2023-12-12 Advanced Energy Industries, Inc. Spatial monitoring and control of plasma processing environments
US11942309B2 (en) 2022-01-26 2024-03-26 Advanced Energy Industries, Inc. Bias supply with resonant switching

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0692138B2 (en) 1993-04-02 2014-10-22 Advanced Energy Industries, Inc. Reactive dc sputtering system
US5922180A (en) * 1995-12-04 1999-07-13 Nec Corporation Sputtering apparatus for forming a conductive film in a contact hole of a high aspect ratio
JP2000256845A (en) * 1999-03-12 2000-09-19 Anelva Corp Formation of thin film and thin film forming device
JP2010229428A (en) * 2009-03-25 2010-10-14 Tsuru Gakuen Magnetron sputtering device and method for manufacturing electronic component
TWI494967B (en) * 2011-07-28 2015-08-01 Advanced Energy Ind Inc System, apparatus and method for plasma-based processing
JP2019513903A (en) * 2016-04-22 2019-05-30 エリコン サーフェス ソリューションズ アーゲー、 プフェフィコン TiCN with reduced growth defects using HiPIMS
US10811228B2 (en) 2017-11-17 2020-10-20 Advanced Energy Industries, Inc. Control of plasma processing systems that include plasma modulating supplies
US10811229B2 (en) 2017-11-17 2020-10-20 Advanced Energy Industries, Inc. Synchronization with a bias supply in a plasma processing system
US10811227B2 (en) 2017-11-17 2020-10-20 Advanced Energy Industries, Inc. Application of modulating supplies in a plasma processing system
US11842884B2 (en) 2017-11-17 2023-12-12 Advanced Energy Industries, Inc. Spatial monitoring and control of plasma processing environments
US11670487B1 (en) 2022-01-26 2023-06-06 Advanced Energy Industries, Inc. Bias supply control and data processing
US11942309B2 (en) 2022-01-26 2024-03-26 Advanced Energy Industries, Inc. Bias supply with resonant switching

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