JPH0214128U - - Google Patents
Info
- Publication number
- JPH0214128U JPH0214128U JP9122188U JP9122188U JPH0214128U JP H0214128 U JPH0214128 U JP H0214128U JP 9122188 U JP9122188 U JP 9122188U JP 9122188 U JP9122188 U JP 9122188U JP H0214128 U JPH0214128 U JP H0214128U
- Authority
- JP
- Japan
- Prior art keywords
- microcomputer
- potential
- power supply
- output terminal
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Power Sources (AREA)
- Microcomputers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9122188U JPH0214128U (en17) | 1988-07-09 | 1988-07-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9122188U JPH0214128U (en17) | 1988-07-09 | 1988-07-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0214128U true JPH0214128U (en17) | 1990-01-29 |
Family
ID=31315706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9122188U Pending JPH0214128U (en17) | 1988-07-09 | 1988-07-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0214128U (en17) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5884330A (ja) * | 1981-11-13 | 1983-05-20 | Canon Inc | マイクロプロセツサの入力回路 |
| JPS62144218A (ja) * | 1985-12-18 | 1987-06-27 | Fujitsu Ltd | 待機系回路の電流節減方式 |
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1988
- 1988-07-09 JP JP9122188U patent/JPH0214128U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5884330A (ja) * | 1981-11-13 | 1983-05-20 | Canon Inc | マイクロプロセツサの入力回路 |
| JPS62144218A (ja) * | 1985-12-18 | 1987-06-27 | Fujitsu Ltd | 待機系回路の電流節減方式 |