JPH0214125U - - Google Patents
Info
- Publication number
- JPH0214125U JPH0214125U JP9159288U JP9159288U JPH0214125U JP H0214125 U JPH0214125 U JP H0214125U JP 9159288 U JP9159288 U JP 9159288U JP 9159288 U JP9159288 U JP 9159288U JP H0214125 U JPH0214125 U JP H0214125U
- Authority
- JP
- Japan
- Prior art keywords
- battery
- memory
- voltage
- terminal device
- portable terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の一実施例のブロツク構成図で
あり、第２図は本考案によるメモリ管理回路の具
体的な回路図である。
１……電圧監視回路、２……メモリ管理回路、
３……ＲＯＭ、４……ＲＡＭ、５……ＣＰＵ、６
……高容量コンデンサ、８……バツテリ、９……
ラツチ回路、１０……デコーダ回路。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a specific circuit diagram of a memory management circuit according to the present invention. 1...Voltage monitoring circuit, 2...Memory management circuit,
3...ROM, 4...RAM, 5...CPU, 6
...High capacity capacitor, 8...Battery, 9...
Latch circuit, 10...decoder circuit.
Claims (1)
するＣＰＵと、電源としてのバツテリと、周辺回
路とからなる携帯型端末装置において、前記バツ
テリの電圧値を監視する電圧監視回路と、前記メ
モリのアクセス管理するメモリ管理回路とを具備
し、前記電圧監視回路により前記バツテリの電圧
低下を検出し、前記メモリ管理回路により前記メ
モリのアクセスを切り換えることにより、該バツ
テリの電圧低下時のプログラムの暴走を回逃する
ことを特徴とする携帯型端末装置。 In a portable terminal device comprising a memory consisting of ROM and RAM, a CPU for arithmetic processing, a battery as a power source, and peripheral circuits, a voltage monitoring circuit monitors the voltage value of the battery, and manages access to the memory. a memory management circuit, the voltage monitoring circuit detects a voltage drop of the battery, and the memory management circuit switches access to the memory to avoid program runaway when the battery voltage drops. A portable terminal device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9159288U JPH0214125U (en) | 1988-07-11 | 1988-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9159288U JPH0214125U (en) | 1988-07-11 | 1988-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0214125U true JPH0214125U (en) | 1990-01-29 |
Family
ID=31316064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9159288U Pending JPH0214125U (en) | 1988-07-11 | 1988-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0214125U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0659785A (en) * | 1992-08-06 | 1994-03-04 | Fujitsu Ltd | Power control circuit for battery operation device |
-
1988
- 1988-07-11 JP JP9159288U patent/JPH0214125U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0659785A (en) * | 1992-08-06 | 1994-03-04 | Fujitsu Ltd | Power control circuit for battery operation device |
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