JPH02140840A - Program debug method - Google Patents

Abstract

PURPOSE:To write a patch program only by means of a code which is to be originally reflected on a source code by writing a return instruction in a whole patch area at the start-up time of a target system and overwriting the patch program on the instruction. CONSTITUTION:The return (RET) instruction is written in the whole patch area 7c in RAM 7 by a monitor program at the start-up time of the target system, and the patch program is overwritten on the RET instruction before a program to be debugged is performed. The RET instruction is left as it is in the remaining part. Consequently, control is normally returned to the program to be debugged by the first remaining RET instruction irrespective of the length of the patch program even if the patch area 7c is called by an interruption processing handler 10 by the interruption of a debug register 9. Thus, only the patch code of the patch program has to be written in the patch area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program debugging method for debugging a program to be debugged in a target system from a host machine.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a system to which the conventional program debugging method is applied, as shown in the specification and drawings attached to Patent Application No. 37930 of 1988. In FIG. A target system as an information processing device, 2 is this target system 1.
A host machine such as a personal computer is used to debug a program to be debugged in the target system 1. Reference numeral 3 represents a communication cable such as R5232C, which connects the target system 1 and the host machine 2.

Further, 4 is a central processing unit (hereinafter referred to as CPU) installed in the target system 1, and 5 is a read-only memory (hereinafter referred to as RO) installed in the target system 1.
6 and random access memory (hereinafter referred to as RA)
7 (referred to as M), each of which contains a program to be debugged and a monitor program for debugging the program to be debugged. 8 is an input/output device similarly installed in the target system 1;
is a debug register included in the CPU 4 in the target system 1, and any address can be set.
If it matches the execution address of U4, an interrupt is generated.

Next, the operation will be explained. FIG. 4 is a flowchart showing the flow of basic debugging operations.

First, when a debug command (for example, a command to read and display the memory in target system 1) is issued from the keyboard of host machine 2 (step 5TI), the monitor program in host machine 2 , performs lexical analysis of the issued command (step 5T2), creates a message in a form that can be determined by the monitor program on the target system 1 side for each command from the analysis result (step 5T3), and sends it to the target system 1 (step 5T3). Step 5T4).

This message is sent to the target system 1 by cable 3. The monitor program of the target system 1 receives the message (Step 5T5), decodes the message (Step 5T6), and executes a debug processing routine (for example, register read, memory write, etc.) according to its contents (Step 5T5). 5
T7).

When the execution of the debug processing routine is completed, a message of the result is created (step 5T8) and sent back to the host machine 2 (step 5T9).

Wait for the next message. After sending the message, the host machine 2 waits for the execution result to be returned from the target system 1, and when the result is sent back via the cable 3, it receives it (step 5TIO) and displays the result. (Step 5TII).

Next, a case will be described in which a few steps of instructions are added to an arbitrary address of the program to be debugged (hereinafter referred to as patch addition) and executed. FIG. 5 is an explanatory diagram showing the concept of processing in such a case, and FIG. 6 is a flowchart showing the flow of the processing operation.

In FIG. 5, 7 is the RAM in the memory 5, and 9 is the CPU.
7a is a debug register stored in the RAM 7, and 7b is a patch area (fixed address) secured in the RAM 7 in which a patch program for adding a patch is written. Here, the entire patch area 7b is initially filled with random numbers, and the patch program is overwritten on these random numbers before the program to be debugged is executed. Further, 10 is an interrupt processing handler that controls interrupts based on the contents of the debug register 9.

Next, processing operations will be explained. Prior to execution of the debugged program, the user issues a memory write command from the host machine 2 to write the patch code of the patch program to be added and a RET command to return to the debugged program 7a in the patch area 7b. (
In step 5T20), this patch program is obtained by creating a patch code in advance and assembling it with a RET command added to the end of the patch code. When the monitor program of the target system 1 receives this command message, it decodes it in step 5T21.
), these patch codes and RET commands are overwritten in the patch area 7b (step 5T22). Here, since the patch area 7b has been filled with random numbers as described above, the random numbers are left as they are in the margins.

When the overwriting of the patch code and RET command is completed.

The resulting message is created and sent to the host machine 2 (step 5T23), and the host machine 2 receives and displays the resulting message (step 5T24). In this case, the display only indicates that the processing in the target system 1 was normal. Then, when an interrupt occurs by the debug register 9, that is, when the address written in the debug register 9 matches the execution address, the address to which the patch is added is debugged so that control is transferred from the debugged program 7a to the patch area. A command for performing processing such as writing to register 9, for example, a PATCHADDR (patch address) command is issued (step 5T25). The target system 1 receives the sent message using its monitor program, decodes it (step 5T26), and stores the command parameter "' A D D in the debug register 9.
The contents of "R" are written (step 5T27), and a result message indicating that the processing was normal is created and sent to the host machine 2 (step 5T28).

The host machine 2 receives and displays the message as a result (step 5T29), and when the host machine 2 issues a command indicating execution of the program to be debugged 7a (step 5T30), the target system 1 receives the message.

It is decoded (step 5T31), and execution of the debugged program 7a is started (step 5T32).

That is, when the address written in the debug register 9 is executed, an interrupt occurs and the patch area 7bttCALL is performed in the interrupt handler 10, and the patch area 7b is called.
After execution of the instruction written in , the RET instruction returns to the interrupt processing handler 10, the interrupt processing is completed, the program returns to the debug target program 7a, and the continuation of the program is executed. Execution continues until a command to stop the execution of the debugged program 7a is issued. In this way, when the execution of the program to be debugged 7a is completed, a result message is created and transmitted (step 5T33). The host machine 2 receives and displays the results in step 5T3.
4) Then, a program termination command is sent to the target system 1 (step 5T35), the target system 1 receives it and decodes it (step 5T36), and stops the execution of the program to be debugged (step 5T37).
, this execution result message is created and sent to the host machine 2 (step 5T38), and the host machine 2 receives it and displays it (step 5T39).

[Ill g to be solved by the invention] Since the conventional program debugging method is configured as described above,
When patching an instruction to a debugged program as a debug operation, the patch program and RET instruction are written in the patch area 7b in advance, but after confirming the operation by adding the patch, when reflecting the patch program to the source code of the debugged program, The RET command is unnecessary, and it is easy to make a mistake by applying it to the source code with the RET command attached.If you apply a patch program to the source code with the RET command attached, the program will not work properly. was there.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a program debugging method that allows a patch program to be written using only codes that should originally be reflected in the source code.

[Means to solve the problem]

In the program debugging method according to the present invention, when starting up the target system, a return instruction is written in the entire patch area, and the patch program is overwritten on top of it, so that the execution address matches the address written in the debug register. At the same time, an interrupt is generated to transfer control from the program to be debugged to a patch area, and after execution of the patch program, control is returned from the patch area to the program to be debugged using the first return instruction remaining at the time of overwriting.

(Operation) The program debugging method in this invention first applies R to the entire patch area when starting up the target system.
Write the code for the ET command.

Before running the program to be debugged, the patch area is overwritten with the patch program, but the entire patch area is
Since the ET command is written, the RET code always comes after the patch program code in the patch area. Therefore, the batch area is CALed by the interrupt handler due to the debug register interrupt.
Even if the batch program is L, control is normally returned to the debugged program by the first RET command left, regardless of the length of the batch program.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Here, the program debugging method of the present invention is also applied to the system having the configuration shown in FIG.

FIG. 1 is an explanatory diagram showing the concept of processing when a patch is added to an arbitrary address of a debugged program and executed. In FIG. 6, 7 is a RAM, 7a is a debugged program, 9 is a debug register, 10 is an interrupt processing handler, which is the same as, or corresponds to, the conventional ones denoted by the same reference numerals in FIG. 5, so detailed explanation will be omitted. Also, is 7c RAM? This patch area 7c is secured within the target system 1 and in which a patch program for batch addition is written.
This patch area 7b is different from the conventional patch area 7b in that a RET command is written over the entire area by a monitor program when the program is started up, and a patch program is overwritten on this RET command before the program to be debugged is executed.

Next, the operation will be explained. FIG. 2 is a flowchart showing the flow of the processing operation. First, before executing the program to be debugged, the user issues a memory write command to overwrite the patch area 7c with the batch code of the patch program to be added from the host machine 2 (step 5T40). Target system 1
The monitor program receives this command message.

decode it (step 5T21) and overwrite the patch code in the patch area 7c (step 5T41),
Here, in the patch area 7C, as mentioned above, the entire RE
Because the T command was written.

The RET command is left as is in the margin.

Thereafter, the process proceeds in the same way as in the conventional case, and the target system 1 receives and translates the command message issued by the host machine 2 (step 5T31), and starts executing the debugged program 7a (step 5T4).
2), that is, when the execution address matches the address in the debug register 9, an interrupt is generated, the patch area 7c is called in the interrupt handler 10, and after executing the instruction written in the patch area 7c, the blank space is Control is returned to the interrupt processing handler 10 by the remaining first RET command, the interrupt processing of the patch program is ended, and the continuation of the program to be debugged is executed.

Thereafter, processing is performed as in the conventional case.

〔Effect of the invention〕

As described above, according to the present invention, the RET instruction code is written in the entire batch area when the target system is started up, and the patch program is overwritten thereon. If you want to add and run a program, you only need to write the patch code for the patch program in the patch area, and when incorporating the patch program into the source program,
This has the effect of eliminating the possibility of accidentally leaving the RET command on.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the concept of patch addition processing in a program debugging method according to an embodiment of the present invention, FIG. 2 is a flowchart showing the flow of the processing operation, and FIG.
The figure is a block diagram showing the configuration of a system to which the present invention and the conventional program debugging method are applied, Figure 4 is a flowchart showing the flow of normal processing operations of the conventional program debugging method, and Figure 5 is a conventional patch An explanatory diagram showing the concept of additional processing, and FIG. 6 is a flowchart showing the flow of the processing operation. 1 is the target system, 2 is the host machine. 4 is a CPU, 5 is a memory, 7 is a RAM, 7a is a program to be debugged, 7c is a patch area, 9 is a debug register, and 10 is an interrupt processing handler. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A program debugging method in which a host machine sends a message related to a debugging operation to a target system to debug a debugged program written in the memory of the target system, wherein a patch is installed in the memory when the target system is started up. A return instruction code is written in the entire area, and before the debugged program is executed, the patch area is overwritten with a predetermined patch program, and the execution address of the debug program is stored in the debug register in the central processing unit of the target system. An interrupt that occurs when the address matches the written address causes control to be transferred from the program to be debugged to the patch area, and after execution of the patch program, control is transferred to the patch area by the first return instruction remaining at the time of overwriting the patch program. A program debugging method characterized by returning from a patch area to the program to be debugged.