JPH02132575A - Parallel computer-vector register data flow synchronizing device and network presetting device - Google Patents

Abstract

PURPOSE:To reduce the synchronizing overhead of the memory lock, etc., by providing a means which writes the information at one time into the same addresses of the memories of full element processors from a host computer and a data flow synchronizing means. CONSTITUTION:The title device includes a broadcast means 24 which writes the information at one time into the same addresses of the memories of full element processors 2 from a host computer 1, a full synchronizing means 26 which detects the end of the process of the processor 2, a mutual connection network 3 which is used for transfer of information between the optional processors 2. Furthermore a data flow synchronizing means consists of a synchronizing variable or synchronizing register which is set at each processor 2 to secure the writing/reading synchronization with the memory at transfer of information and an exclusive addition/subtraction circuit is provided. Thus the synchronizing overhead of the memory lock, etc., can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel computer, and more particularly to a parallel computer for numerical calculations that mainly performs load distribution processing of repetitive loops. [Prior Art] Conventional parallel computers for numerical calculations include a local memory type parallel computer described in the following document 1, a shared memory type parallel computer described in the following document 2, and a multiprocessor such as a vector computer described in the following document 3. be. Reference 1 Charles L. Seitz: The C
osi+ic Cube, Com+aunication
ns of the ACM, vo Q. 28,
Nnl, pp. 22-33. 1985) Reference 2 Alan Gottlieb et.al.: The NYU Ultracomputer Design Anne MIMD Shared Memory Parallel Computer, IEEE Transactions on Computers Vol. C-32, No. 2, pp. 175-189, 1983 (Allan Gottligb et.al.: Th
e NYU Ultracomputer-Desig
ning an MIND Shared Memory
y Parallel Computer, IEEE
Transactions on Computers
,voQ. C-32, N(L2, pp.l75-
189. 1983) Reference 3 Kazuya Terauchi: CRAY-2 supercomputer with 2 GB main memory and liquid immersion cooling method, Nikkei Electronics, 1985.12.16,
Pages 195-209, 1985 Among these, in the local memory type parallel computer described in Reference 1, the problem to be solved is divided according to the configuration of the parallel computer used, and a program is created for each element processor.
When exchanging data between element processors, a data transmission/reception command, such as a SEND command or a RECIVE command, is issued. Furthermore, if sequential processing is required, one of the element processors executes it after synchronizing with the other element processors.

In a shared memory type parallel computer, data is stored in shared memory without being divided, and programs are divided or copied and executed by each element processor. Therefore, there is no need to exchange data between element processors using send/receive instructions.
Instead, read and write shared memory. Therefore, in order to control the order of reading and writing, it is necessary to synchronize the element processor that defines the data and the element processor that references the data. Typical synchronization means include memory locking and unlocking procedures.

The multiprocessor of a vector computer is also a shared memory type, and data shared between element processors is placed in the shared memory and read and written using lock/unlotter control. Therefore, parallel processing of vector processing (using vector registers) is possible only when there are no dependencies between variables in the loop. Document 4 listed below describes an example of constructing a shared memory on distributed memory. In this example, when each element processor accesses data in its own memory, it is fast, but when accessing the memory in other element processors, it is slow because it goes through the network. Reference 4 G.F. Feister et al.: The IBM Research Parallel Processor Prototype (R
P3): Introduction and Architecture, Proceedings of the 1985 International Conference on Parallel Processing, pp. 764-771, 1985 (G.F. Pfiststr st.al.: The
IBM Research Parallel Pr
ocessor Prototype (RP3):
Introduction and Architecture
ure、Proceedings of the 19
85International Conference
e in ParallelProcessing
pp. 764-771. 1985) [Problems to be Solved by the Invention] First of all, how can local memory type parallel computers be used by users? A major problem is that the problem must be divided keeping in mind the size of the column calculator. The remaining three types of parallel computers ■Shared memory type parallel computers,
Parallel computers with vector computer multiprocessors and distributed shared memory ■ have the following problems.

(1) In shared memory type parallel computers, the performance per unit is not as high as that of vector computers, so in order to increase the performance of the entire system, many computers must be connected. This increases the amount of hardware in the device that connects the element processors and the shared memory, which takes time for memory access and causes problems such as memory access contention. In particular, when data is shared by multiple element processors, synchronization overhead such as memory locking becomes large, and there is a problem that performance cannot be achieved even if many element processors are combined. (2) Since the performance of each multiprocessor in a vector computer is high, there is little need to combine a large number of element processors. However, there is still a problem in that synchronization overhead such as memory locking is large, and vector processing of loops with data dependencies cannot be executed in parallel.

(3) Parallel computers with distributed shared memory can access data at high speed if it is in its own memory, and there is no memory contention, so it is suitable for connecting a large number of element processors. . However, when exchanging data between element processors, communication takes time. In addition, once data is allocated on distributed memory, it is impossible to convert the program such as exchanging the inner loop and outer loop to obtain loop independence in order for the vector computer to perform vector processing. Therefore, it becomes necessary to target more dependent loops. this is,
This leads to increased synchronization overhead between element processors. The purpose of the present invention is to develop a multiprocessor vector computer, which is a parallel computer that can achieve even higher performance without the user having to be aware of the configuration of the parallel computer to divide the problem, and a parallel computer with distributed shared memory. This is a common problem with computers.

The object of the present invention is to provide a synchronization means that solves the problem of large synchronization overhead such as memory lock, and a parallel computer and vector computer using the synchronization means.

Yet another object of the present invention is to address problems specific to multiprocessors in vector computers.

An object of the present invention is to provide a vector calculator that solves the problem of not being able to execute vector processing in a loop with data dependence in parallel.

Furthermore, another object of the present invention is particularly noticeable in parallel computers having distributed shared memory.

The object of the present invention is to provide a parallel computer that solves the problem of communication taking time.

[Means to solve the problem]

In order to solve the above problems, the parallel computer of the present invention includes a broadcasting means for writing information from a host computer to the same address in the storage device of all element processors at once;
all synchronization means for detecting the completion of processing of all element processors;
An interconnection network for exchanging information between arbitrary element processors, and a synchronization variable or synchronization variable provided in each element processor to synchronize writing and reading from the storage device when exchanging information. It includes data flow synchronization means consisting of a synchronization register and its exclusive addition/subtraction circuit.

Further, in a preferred embodiment of the present invention, the element processors have a vector operation unit, such as a multiprocessor of a vector computer, and the vector register of one element processor is transferred to the vector register of one or more other element processors. A means for setting a route for directly sending data, and a unit for each word that allows data to be written to a vector register when its value is 0, and that allows data to be read from a vector register when its value is 1. It has a data flow synchronization device between vector registers, which consists of a vector register with a tag field provided in the tag field, and a means for manipulating the value of the tag field. Furthermore, in order to reduce communication overhead, we have added a network connection pattern setting circuit that sets the interconnection network connection pattern before using the network, and a vector register address that stores the data sent from the source element processor number. Alternatively, it is equipped with a network preset device consisting of a storage address generation circuit that converts into a storage area address in a storage device. [Operation] The end of one repetition loop to be executed in parallel is detected at high speed by using all synchronization means that detects the completion of processing by all element processors, and other loops to be executed in parallel following this loop are completely removed from the host computer. It is possible to start quickly by using a broadcasting means that writes information at once to the same address in the storage device of the element processor, and in this way to quickly synchronize to satisfy the data dependence relationship that exists between both loops. It becomes possible. Further, after the information producer-side element processor transfers the information to the consumer-side element processor, the content of the synchronization variable or synchronization register of the consumer-side element processor is increased by 1 using an exclusive addition/subtraction circuit, If the content of the synchronization variable or synchronization register in its own processor is positive, the consumer element processor decrements it by 1 using exclusive addition/subtraction, and then refers to the transferred information (or After the processor refers to the information of the producer-side element processor, the content of the synchronization variable or synchronization register of the producer-side element processor is increased by 1 using an exclusive addition/subtraction circuit, and the producer-side element processor If the contents of the synchronization variable or synchronization register in
Shared data can be accessed without performing an unlock procedure, and even if there is a data dependency that spans element processors within a single iteration loop, parallel processing can be performed without excessive overhead. ．． In particular, when element processors have vector arithmetic units, in vector processing of loops with data dependencies across element processors, route setting means between vector registers belonging to different element processors is used.
A route is set for directly sending data from the vector register of one element processor to the vector register of one or more other element processors according to the data flow representing the dependency relationship, and is set for each word of the vector register. If the content of the tag field indicates that data has arrived, the content is input to the vector calculator, and if the content of the tag field indicates that data has not yet arrived, the data is written there. In this way, by using the vector register-to-register data flow synchronizer of the present invention,
It becomes possible to execute vector processing of loops with data dependencies across element processors in parallel.

Furthermore, if a communication path is determined in advance by a network connection pattern setting circuit, there is no need to decode the communication destination and switch, and there is no need to send the destination itself. Furthermore, since the storage destination of the data sent by the storage address generation circuit can be generated by the receiving side hardware, there is no need to send an address, and the amount of communication can be reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. Figure 2 is an overall configuration diagram of the parallel computer of the present invention. 1
A plurality of element processors are connected under a normal sequential processing computer called a host computer, and these are connected by an interconnection network 3. Between the host computer and the element processor, there is a connection path for exchanging control signals and data, and a full synchronization signal line that transmits the processing end signal of the element processor from the element processor to the host computer. ．． The host computer l is
A coupling bus da is used to broadcast information to the element processors λ. The all-synchronizing signal line 6 is ANDed by an AND circuit (B), and the all-synchronizing signal is transmitted to the host computer (1) only when all the element processors have finished operating. It is assumed that the interconnection network 3 can connect arbitrary element processors.

FIG. 1 is a configuration diagram of one element processor and mutual connection network of the parallel computer of the first embodiment. An element processor is a normal sequential processing computer, and is a processing unit. 2/, memory control unit, local memory. 2J
, SEND unit-6, RECEIVE unit-6
, and a total synchronization register 6. The processing unit 27 is a so-called CPU, and the memory control unit 11 is a processing unit 2/, SEND! Knit II
, RECEIVE unit 6 and the host computer/to the local memory 23. Memory control unit. 2.2 may include a dynamic address translation device. Processing unit. ．． 2/, memory control unit 11, and local memory 3 are the same as those in a normal computer, and are not directly related to the present invention, so further explanation will be omitted. The SEND unit 11 sends the local memory of other element processors under the direction of the processing unit/or memory control unit 11. It is a device that transmits data to R.
ECEIVE unit. 2j receives this and sends it to the memory control unit. Local memory via 2.2. This is a device for writing to 23. These devices may also perform some more complicated processing, such as sending and replying data request information, but the details thereof are not directly related to the present invention, so further explanation will be omitted.

The interconnection network J may be any network as long as it can connect arbitrary element processors. Figure 1 shows a fully coupled full crossbar switch. Detailed circuit diagrams of the switch are shown in FIGS. 3-5. SEND unit. The information sent from 2 das is (
(destination element processor address, write area address, write data value). When the information arrives at the distributor 3/ of the crossbar switch via the data line /O, the destination element processor address is transferred to the decoder J/. 2 (Figure 3) and the corresponding selector 3.2 (Figure 1) is selected,
One of the data paths jtI-/ to jtI-j leading thereto is selected by the distributor 31/ (the third
figure). At this time, a control signal indicating that information is on the data path is output to one of the corresponding signal lines 33-l to 33-3. Each selector 3.2 selects one of the transmission requests arriving at the same time and sends it to the RECEIVE unit-6 of the element processor λ. This operation will be explained using Figures 4 and 5. data path 3der/
～Jllt-3 has data, signal line 33-7～J3-3
A control signal is applied to selector 3. ．． 2, the signal line 33-/-JJ-j passes through the address register 3-da to the ROMJ.2. 2- is input. ROMj. 2.2 is (
(in this example) is a memory accessed by a 5-bit address, the first 2 bits being ROMj. ．． The previous output (3 bits) of 2.2 is encoded by encoder 3.23, and the remaining 3 bits are sent to signal lines 33-l to 3.
3-3 is used. FIG. 5 shows ROMj. 2,. An example of the content of Section 2 is shown. The front side on the left side shows a 3-bit address, and the top side shows a 2-bit address. The 2-bit address is o o ni if the previous output of ROMj, 2.2 is 100, 0 1 ni if it is 010, 001
is encoded as 10. That is, for example, when the first 2-bit address is oo, it means that the previous output was 100, that is, the data bus jlIt-/ was selected last time. Therefore. ROM
J. 2. For addresses in which the first 2 bits of the address in 2 are OO, other data buses are selected, except when there is an output request only to the data path JD/ (the remaining 3 bits are 100). Contains output patterns. In this way, each output request is accepted equally. The RECEIVH unit 1J receives (address of write area, value of write data) and sends it to the memory control unit. Local memory via 21. Write on 23. In the present invention, the program to be executed is A. Repetition loop (array definition part excluding input/output) B.
Sequential processing units other than C. It is divided into input and output parts, with A being assigned to the array of element processors and B and C being assigned to the host computer for execution. In a program for a computer/host, an element is used instead of an execution instruction for A, such as Do 10 I=1,100 Do 10 J=1,100 A (I, J)=...1 0 Confinue, etc. An execution command command START TASKIO etc. of A for the array of processor λ is written. This command broadcasts and writes the entry address t of the program portion TASK10 corresponding to A to the same address #P in the memory devices of all element processors.

The element processors are responsible for the iterative loop processing (TA
When SKIO, etc.) is completed, the entry address t' for the next process is waiting to be written to this address #P, so as soon as the broadcast of t' is completed, the execution begins. When the program execution is finished, it writes 1 to all synchronization registers B and waits for the entry address t of the next process to be written again. The contents of register B for all synchronization are ANDed by AND circuit B.
and input to the host computer as a total synchronization signal.

Therefore, as soon as all element processors have finished processing, their status is immediately transmitted to the host computer l.

As mentioned above, the necessary synchronization between one iteration loop and the next iteration loop that has a dependency relationship with that loop is as follows:
This can be realized at high speed using all synchronization means by means of broadcasting means and hardware. Note that multiple mutually independent loops that are not dependent on each other are executed together.

Next, we will discuss the processing of data dependencies that exist within one iteration loop. Taking the FORTRAN program example, Do 10 I=1,100 Do 10 J=1,100 A(I,J)=A(I-1,J)+B(J)1 0
Repeated loop called CONTINUH (FORTRAN program example)
When performing parallel processing on the
=A(I-1,J)+B(J)1 0 CONTI
An inner loop called NUE is in charge of a specific one.

At this time, for each element of the array A (I-1, J), J=1,100, it is necessary to obtain the defined value from the element processor in charge of the next younger engineer and calculate it. In other words, sequential processing is required for ■. However, since J is independent for each element processor, if the element processor in charge of the next younger module sends definition values one after another in the order of J, parallel processing can be achieved by processing these in a pipeline. It becomes possible. In this way, parallel processing is possible even in repeat loops with data dependencies. In the present invention, local memory is used for parallel processing of such dependent loops. Synchronization variables secured during 23rd. 23/or set the value of the dedicated synchronization register 3- and the synchronization variable-37 or synchronization register J-1 to 1 exclusively.
Exclusive addition/subtraction circuit that increases or decreases by 2// is used as follows.

For simplicity, the element processor in charge of indexing will be referred to as element processor I. Element processor I-
1 defines A(I-1, J), sends this value to element processor I, and then sends control information (destination element processor address, code indicating control information, synchronization) to element processor I. variable or synchronization register address). When the control information arrives, the memory control unit 11 judges it and sends it to the processing unit. Interrupts 2/. Processing unit. The interrupt processing program of 2/ uses the exclusive addition/subtraction circuit 1/l to set the synchronization variable -3.
7 or synchronization register. 2J7! Add 1 to the contents of. On the other hand, element processor I uses this synchronization variable before referring to A(I-1, J). 2 J/. Or a synchronization register. Check whether the contents of 2J- are correct or not, and if not, repeat the checking operation (busy wait). If the content is positive, refer to A (I-1, J). The above is an example of a dependency relationship that refers to a defined variable, but the same applies to a dependency relationship that redefines a referenced variable.

That is, DO 10 I=1,100 Do 10 J=1,100 A(I,J)=A(I+1,J)+B(.T)1 0
When processing CONTINtlH (FORTRAN program example) in parallel, the element processor is A(I+1.,J).
After referring to , this value is sent to element processor I+1, and then control information (destination element processor address, code indicating control information, synchronization variable or synchronization register address) is transmitted to element processor I+1. When control information arrives at the synchronization variable or synchronization register, the memory control unit. 2.2 determines this and interrupts the processing unit 1/. Processing unit. 2
/'s interrupt processing program is an exclusive addition/subtraction circuit. 2//
Add 1 to the contents using . On the other hand, before defining A (I+1, J), element processor I+1 checks whether the contents of this synchronization variable 23/or synchronization register 3.2 are correct, and if not, repeats the checking operation ( busy wait). If the content is positive,
Define A (I+1.1).

Synchronization variable. Since the synchronization register 3.23/or the synchronization register 3.2 is of the counting type, in any of the above examples, the element processors in charge of the smaller index I can advance any number of processes.

Embodiment 2 The overall configuration of a parallel computer, the main components of the element processors, and the method of program division, allocation, and execution are the same as in Embodiment 1. In the following, different parts will be mainly explained using FIG. 6.

This embodiment includes a network preset device and a network preset device in Embodiment 1.
That is, the decoder 3/-l is removed from the distributor J/ of the interconnection network 3, and the connection pattern setting circuit 33 and the storage address generation circuit l? of the distributors J//-0 to J are replaced instead. is added. In the FORTRAN program example cited in Example 1, Section I
- It can be seen by analyzing the source program that it is necessary to transmit data and control information from the first element processor to the second element processor. In this embodiment, the interconnection pattern between element processors analyzed by the compiler is converted to the interconnection network 3 before starting the iterative loop processing.
The data is sent to the connection pattern setting circuit 33 to determine the connections of the distributors J//-0 to 3. Also, the receiving area start address (
A (T-.1.1) address) and its word length are respectively stored in the address generation circuit l? Storage area inside. Area address register /wo/-/~/? /−j and word length register /? Store in 5. In each element processor A (
I-1, J) and J=1,100 are assigned to the same address, the reception area start address and word length can be stored and broadcast from the host computer l. If A(I
-2, J), etc., that is, when there is a possibility of simultaneous reception from multiple element processors, the reception area start address and word length of each reception area are stored in the storage area address register lwo / corresponding to the source element processor. -/~/?
/-J and store in word length register /9.5. However, this device is mainly designed to be applied to repeat loops that define one formula, and in the case of a program that defines multiple formulas in one repeat loop, into a sequence of repeating loops that define

Storage address generation circuit/Storage area address register in file/9/1/~/? /-j is selector j. ．． 2-0～
3 (hereinafter referred to as input channel). This is because if the input channel to the selector 3 θ to 3, which is determined for each element processor, is known, the transmitting element processor can be known, and the address of the receiving area corresponding to this can be stored. In the example in this diagram,
There is a relationship: sending side element processor number = receiving side element processor number + input channel number to the selector + 1 (number of mad element processors). Therefore, in the present invention, the storage area address register/? /-l~/'
In order to select l/-j, the input channel numbers (0, 1.2) output from the selectors j, 210 to 3 of the interconnection network 3 as shown in FIG. As shown, the decoder l? 1 and decoded, and the selector /93 is switched according to the result. In the case of control information (code = 'i'), it is a synchronization variable. 23
l or synchronization register jJ. The register that stores the address of 2/? /-1 is selected. In the case of data, the register /? is set to the address of the storage area for the data sent from the transmitting element processor determined by the above relationship. Select /9/-J from /-/.

There is a storage area address register /9/-/~/? /
- When one of the registers is selected, the contents of the word length register are added to the contents of the adder/? The write control circuit/? is added to the selected storage area address register by Q. Returned via 0. This process advances the address by one word.
However, synchronization variable-3l or synchronization register. 2J
In the case of 1, the word length is O. Using the above device, the 1-1st element processor is A (
After defining I-1.1), the case where it is sent to the I-th element processor and pipelined by data flow synchronization will be explained using FIG. (1) All element processors are A (I-1, J), J=1
, 100 are allocated from the same ao address.

If you are in charge of multiple ■ (hereinafter referred to as ``work'', etc.).
A (I-1, J), J=1 in the area starting from address ao
, 100 followed by A(I'-1, J), J=1,1
Assign 00 etc. (2) The host computer stores ao in the storage area address register /D/-3 via the write control circuit. Storage area address register/? /
-/~3 correspond to input channels 0 to 2 (displayed in the box of selector 3 no -θ~3) to each selector 3λ-θ~3 of mutual coupling network 3, respectively, and input channel 2 is Every selector is connected to the element processor with the next lower number (modulo the number of processors).

(3) Is the host computer/word length register/? The word length of A is stored in 6.

(4) Set the distributor pattern setting circuit 33 to output channel 0 of each distributor (the output channel number is displayed to the left of distributors J//-0 to 3). Streamer 3ii-o
The output channels O of ~3 are connected to the input channels 2 of selectors 12-0~J, respectively. In other words, there is a relationship: destination (receiving side) element processor number = source (sending side) element processor number 10 distributor output channel number + 1 (mad, number of element processors). (5) Synchronization variables. 2J/or initialize the value of synchronization register 3 to O. From here, the loop process begins. (6) The 0th element processor sends A(1.1) to the SEND unit. Send by 2ll.

(7) Output channel 0 of distributor J//-0
from input channel 2 of selector 3-1/ to the first
RECEIVE unit of element processor. Data is passed to 2j. On the other hand, the input channel number 2 of the selector 3.2-/ is input to the decoder l of the first element processor along with the control information code 0 in the data, and as a result, the selector /? 3 sets the storage area address register/? /-
3 is selected and its content (ao) is Rll! CEIV
The memory control unit, . Sent to 2. (8) Memory control unit. 2- is the value A (1,1)
Write to address ao. (9) Adder/? Selector/? The word length (in bytes, for example, 8 for double precision arithmetic) is added to the third output ao, and ao+8 is the write control circuit/? It is written to storage area address register /9/-j via O.

(lO) The 0th element processor sends control information through the SEND unit.

(11) From the output channel O of the distributor J//-0 to the RECEIVE unit of the first element processor via the input channel 2 of the selector 3-1/. Control information is passed to 2J. decoder/? To one, selector J2
-/input channel number 2 and control information code '1''
is input. As a result, the storage area address register containing the synchronization variable address or synchronization register address /? /-9 is selected and sent to the memory control unit 11, after which it is exclusively incremented by 1 by the interrupt processing program of the processing unit 11. (12) The O-th element processor further enters the next iteration and converts A (1.2) to the first
Send to element processor. (13) The first element processor is . Write A (1.2) to address aO+8. The contents of the storage area address register /'l/-j become ao+16.

(14) The O-th element processor sends control information, and the first element processor performs exclusive addition to it. Variable for synchronization of the first element processor. 23l or synchronization register 3
、． The value of 2 is 2. (It doesn't matter how much time the O-th element processor sends in advance in this way.) (15) The first element processor sends synchronization variable -37 or synchronization register . Check whether the content of 2J1 is positive or not, and if it is positive, 1 is exclusively subtracted. (If zero or negative, busy wait).

(16) The first element processor starts from address ao to A(1,1
) and use it to define A (2.1).
The result is sent to the second element processor. As above,
It is possible to perform pipeline operations between element processors by communicating efficiently without sending address information or decoding/switching. [11l] The overall configuration of the parallel computer, some of the constituent parts of the element processors, and the method of dividing, allocating, and executing programs are the same as in the second embodiment. Below, the different parts will be explained with emphasis using Figures 8 and 9. This embodiment is an extension of Embodiment 2 to the case where the element processors are vector processors. Element processors include local memory, 23, as well as scalar processors l, 5,
Register for all synchronization. 2A, load/store pipe 7-/
, 7-2, Vector register/l-/~l-da, Vector arithmetic unit/dar/~/Q-J, Interchange A/
A, Interchange B/7, SEND pipe 8, R
ECEIVE pipeline and storage address generation circuit/
? It consists of Synchronization variables and registers are not used. The functions of each component are briefly described below.

・Local memory 3 and scalar processor/, 5: A normal sequential processing computer, responsible for processing other than vector processing assigned to element processors.・Register B for all synchronization: Register for synchronizing all element processors. Same as Examples 1 and 2.・Load/store pipe 7-/t 7-. 2: Vector register /11/~/. A device that transfers data between 2-Q and local memory 3 at high speed. It is the same as that used in ordinary vector calculators.・Vector register/,2
-/-/j-Il: Temporary register that stores data used in vector operations. Unlike those used in ordinary vector calculators, each word has a 1-bit tag.
Fields l3-/~/3-da are prepared, and vector registers /. 2-/~/ Set to 1 when data is loaded into the coder. In addition, the vector operator
~/lI-j is the tag field /3-7~/J-1
Enter the word only if the value of is 1, and reset the value of the tag field /3-/ to /3-da to 0. If constant data to be referenced repeatedly is stored in vector registers /11/~/2-2, the tag/
Do not reset the values of fields /3-l to /j-ll to 0.

- Vector calculator /l1t-/~/%-j: Same as the one used in normal vector calculators.

・Interchange A/B: Vector register 7.2-/
~/d-9 and load/store pipe 7-/, 7-. 2,
A data path that interconnects the SEND pipe 8 and the RECEIVE pipe.

・Interchange B17: Vector operator ll1t-/
A data path interconnecting ~/der 3 and vector register /U-/~/coder.

・SEND pipe 8: Vector register /11/~/,
? -1 to the vector registers of other element processors /11/~/. A device that transfers data to 2-1 at high speed.

vector register/. A device that stores data transferred at high speed from 2-/~/1-9 into its own vector register /J-/~/1-9 via interchange A/A.・Storage address generation circuit: Vector register/. 2
−／〜／． ．． A device that generates an address of 2-1 from a receiving channel. By this address, Interchange C/8
The connection path for is set. Although it is functionally similar to the second embodiment, the storage area address register/? The difference is that vector register addresses are stored in /-/~3, and there is no word length register or addition circuit. The mutual coupling network 3 is the same as in the second embodiment, and the connection pattern of the distributors J//-0 to J//-j is set by the distributor pattern setting circuit 33, eliminating the need for address decoding and switching. This is what I did.

Next, the operation of the parallel computer of this embodiment will be described. The program is a FORTRAN program example of Example 1■
Explain using.

(1) Before starting vector processing, the host computer l sets the coupling pattern of the mutual coupling network 3. That is, the output channel of each distributor 3//-0 to J//-J is set to 0 by the distributor pattern setting circuit 33. In this example, output channel 0 of the distributor is connected to selector 3--0 to j2-, respectively.
This is because it is connected to input channel 2 of No. 3.

(2) Issue a receive command to vector register /11/. In other words, the storage area address register/? /-. ．．
? , host computer 1 stores the address of receiving vector register /11/ via write control circuit /90, and simultaneously assigns one of the data paths of interchange A/4 to vector register /2-/. do. Specifically (FIG. 9), the vector instruction control circuit/. 50 uses the signal line 10 to connect the selector /Otsu0-/ to the signal line 1/9, and the signal line 1/0 connects the RECEIV
E instruction generation control circuit? Send a start signal to 0. It also sends a start signal to the vector register access control circuit via signal line 1. RECEIVE instruction generation control circuit? O is activated and the signal line? Wait until the receive vector register address is input from J-,2. The storage area address register /'7/-/~3 corresponds to input channels 0~2 to each selector 3.2-0~3-3 of the interconnection network 3, and input channel 2 corresponds to which element processor. It is also connected to the element processor with the next lower number in the selector. Therefore, the vector registers /2-/ of all element processors are now ready to receive vector data transmitted from the element processor with the next lower number. That tag field/3
-/ is initialized to 0. (However, only the O-th element processor uses a vector register /11/
Issue an instruction to load initial data to.

In this case, the tag field /3-l will be 1. ) (3) Vector register 7.2-1 B (J), J
Start loading =1,100. This is done using the load pipe 7-/, and 1 is set in the tag field /3-1. Specifically, the selector/O-1 is connected to the signal 1/O via the signal line 10, and the activation signal, number of elements, and data width are sent to the request generation control circuit 70-/ via the signal line 1j. The start address and increment of B (J) are sent to the address generation control circuit 7/-/. Further, the signal line 1/ sends an activation signal to the vector register access control circuit 78-l and the vector register/. Send the address of 2-2. This allows the vector register access control circuit 78-l to control writing to the vector registers/1--. Address generation control circuit 7/-
The address generated by / is stored in the address register 7-1I, passes through the priority control circuit 73, enters the address register 7II, and is transferred to the local memory 7-1I. 23 is used for reading. After a predetermined number of cycles, the priority control circuit 23
Selector 76, vector register access control circuit 28
Send selection information and write instruction signals to -/, respectively,
Local memory. The data outputted from 23 is written into the vector register/1-1 via the selector lO-1. At this time, 1 is also written in the tag field /J-,2.

(4) At the same time, a vector addition instruction is issued and the vector register/. Adds the contents of 2-/ and vector register /2-2 and starts outputting to vector register /, 2-j and vector register /, 2-1. For processors other than the 0th element processor, the tag field /3-/ of vector register /1-/ is 0, so it is not immediately included in the calculation. but,
The Oth element processor can start calculations and send the results to vector registers /t2-J~/. through interchange B/7. ．． Output to 2-1. The tag field /3-3~/J-da corresponding to the output word is 1
becomes.

(5) Issue a transmission command from vector register/, 2-J. As a result, a data bus from vector register /1-3 to SEND pipe 8 is created on interchange A/A, and SEND pipe 8 is connected to tag field /3-3.
3 sends the contents of 1 to the interconnection network 3. Specifically, the vector instruction control circuit/JO connects the selector/Otsu0-J to the signal line 1/8 using the signal 10, and the signal line 1? The activation signal is sent to the SEND instruction generation control circuit 80 using the SEND instruction generation control circuit 80, and the activation signal and the vector register/. 2-Send J's address. The data read from the vector register 7.2-J by the signal of the vector register access control circuit 83 is outputted to the signal line 1/8 via the selector/Otsu0-j and stored in the data register 8-J. Ru. At this time, if the content of the tag field at the beginning of each word is 1, the next read instruction signal is sent from the SEND instruction generation control circuit 80 to the vector register access control circuit 83, and the vector register/. ．． 2-J's next word is read. Further, the read data is outputted to the data line /0 except for the tag part, and a transmission signal is outputted to the signal line 1//. If the content of the tag field is O, the SEND instruction generation control circuit 80 does not send the next read instruction signal and repeatedly reads the same word. Also, the signal line 1/7
No transmission signal is output.

In the interconnection network 3, the distributor J/
Since the output channel 0 of /-0 to J//-j is connected to the input channel 2 of the selector 3-10 to 3.2-3 of the element processor with the next higher number, the data is sent from the 0th element processor. The processed data is sent to the first element processor.

(6) Vector register/. Issue the store command 2-1. Vector register/, 2-Z has vector register/. 2-. The same contents as 7 are stored. With this command, storage into the own memory is executed independently of transmission. Storage is performed using another store pipe 7-λ. Specifically, vector instruction control circuit/. 50 connects selector/60-tI to signal line 1/7 by signal 10, and puts the start signal, number of elements, data width, and start address of A (I, J) on signal line 17 and signal line 18, respectively. Request generation control circuit 70-J, address generation circuit 7
Send to /-2. Furthermore, the vector register access control circuit 7B-2 receives an activation signal and the vector register/. 2-I
Send I's address. The addresses of A (I, J) are sequentially sent to local memory in the same way as when loading, and
The data read from vector register/119 is sent to selector/O-tI, signal line 1l7, and data register 7.
7-. ．． 2 to the local memory 3.

(7) Data sent from the element processor with the next lower number is sent from the input channel 2 of the selector in the interconnection network 3 to the RBCEIVE pipe.

At the same time, the input channel number 12' of the selector is changed to the decoder l? − is input to the result selector /? 3 selects storage area address register /9/-J, and its contents (address of reception vector register /j-/) are set to R.
Interchange AI as the address of the vector register where the received data passed from ECEIVE byte 2 is stored.
Sent to Party B. In other words, the signal line? 3-Is the address of the upper vector register /11/ the RECEIME instruction generation control circuit? 0 and is passed to the vector register access control circuit via signal line 1/j? It is input together with the write instruction signal. Based on this input, vector register access control circuit? 1 is the data on the signal line 931/ and the RECEIVE instruction generation control circuit? The value 1 of the tag field generated by 0 is transferred to the data register? /, signal line 1
l? , writes to vector register /11 via selector /40-/. In this way, the received data is transferred to the vector register/. 2-/, and its tag field /J-/ is set to 1 for each written word. From the first element processor onward, vector processing is performed using this value. As described above, it is possible to efficiently communicate and perform vector operations across element processors without transmitting address information or decoding/switching.

〔Effect of the invention〕

In the present invention, the necessary synchronization between one repeating loop and the next repeating loop that is dependent on the loop is achieved at high speed by using broadcast means and hardware-based total synchronization means. Furthermore, in order to satisfy data dependencies in a repeat loop, if the element processors are scalar processors, all that is required is to issue control information transmission & addition instructions and check & busy-%tait instructions in the element processors that maintain synchronization. , does not interfere with other processes like locking/unlocking shared memory. Furthermore, exclusive addition and subtraction are performed after the element processor on the side where the synchronization variable or register exists receives the control information.
It does not monopolize the network unnecessarily and interfere with other processing. In addition, if the element processors are vector processors, vector processing can be performed after connecting vector registers across element processors, and vector processing of repeating loops with data dependencies can be executed in parallel. becomes possible. Furthermore, the network brisset device eliminates the need to send destination information and eliminates decoding and switching of destinations during communication, resulting in faster communication.

[Brief explanation of the drawing]

Figure 1 is an overall configuration diagram of the first embodiment of the present invention, Figure 2 is a conceptual diagram of a parallel computer common to each embodiment of the present invention, and Figure 3 is a conceptual diagram of a parallel computer common to each embodiment of the present invention.
FIG. 4 is a configuration diagram of a distributor in an interconnected network, FIG. 4 is a configuration diagram of a selector in an interconnected network, and FIG.
An example of M, FIG. 6 is an overall configuration diagram of the second embodiment of the present invention, FIG. 7 is an explanatory diagram of the contents of transmission information of the second embodiment, and FIG.
The figure is an overall block diagram of a third embodiment of the present invention, and FIG. 9 is a detailed block diagram of a vector processing device according to a third embodiment of the present invention. Razor imp/Tenita Oribetsu Cork Fig. 4 Ishire Kidney High 5 1 for 4-tooth bow I own number I Bridge 6 AND circuit

Claims (1)

[Scope of Claims] 1. Means for writing information from a host computer to the same address in the storage device of all element processors at once, means for detecting the completion of processing of all element processors, and means for writing information between arbitrary element processors. Mutual connection network for sending and receiving information, and synchronization variables or registers and their exclusiveness provided in each element processor to synchronize writing and reading to and from the storage device when sending and receiving information. 1. A parallel computer comprising: a data flow synchronization means comprising a digital addition/subtraction circuit; 2. Between element processors having vector calculation units, 1
means for establishing a path for sending data directly from the vector register of one element processor to the vector register of one or more other element processors, and when the value is zero, data can be written to the vector register; , a data flow synchronization device between vector registers consisting of a vector register having a tag field provided for each word, which allows data to be read from the vector register when the value is 1, and means for manipulating the value of the tag field. . 3. A network connection pattern setting circuit that sets the connection pattern of the network that interconnects the element processors before using the network, and a vector register address or storage device that stores the source element processor number and the data sent from there. A network preset device consisting of a storage address generation circuit that converts into a storage area address inside. 4. A parallel computer using the vector register data flow synchronization device according to claim 2 as data flow synchronization means. 5. A parallel computer using the network preset device according to claim 3. 6. A parallel computer using the network presetting device according to claim 3 as an interconnection network.