JPH02132312A - Pattern inspection instrument - Google Patents

Abstract

PURPOSE:To constitute a minute pattern inspection instrument which can inspect the entire surface of a wafer and all integrated circuits in a relatively short time by dividing the minute pattern of the integrated circuits on the wafer into a chip peripheral part and a chip center part and detecting them. CONSTITUTION:An area dividing mechanism 10 divides an inspected area into a regular area (microarea, chip center part) and an irregular area (macroarea, chip peripheral part) and a chip peripheral part inspection system 20 performs digital image processing for the macroarea. Then a chip center part detection system 30 processes the microarea by optical filtering to inspect whether the outward appearance of the chip surface pattern is abnormal or abnormal. Consequently, wide-area batch inspection is performed at high speed of several seconds per chip with resolution corresponding to the pattern (resolution based upon the pattern size of the macroarea or resolution of submicron fro the microarea).

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding an inspection device for integrated circuit patterns formed on a wafer, the present invention provides a fine pattern inspection device that requires relatively short inspection time and is capable of 100% inspection of the entire wafer. A region dividing mechanism that divides an integrated circuit chip on a wafer into a peripheral part of the chip consisting of irregularly arranged patterns and a central part of the chip consisting of repeated fine patterns.
A chip peripheral inspection system comprising a pattern imaging optical system for inspecting the chip periphery, a detection sensor, and an image processing processor, and an optical filtering optical system and a defect detection sensor for inspecting the chip center. The present invention includes at least a chip center inspection system, and is configured to inspect a fine pattern of an integrated circuit on a wafer by dividing it into a chip peripheral area and a chip center area.

[Industrial application field]

The present invention relates to an inspection apparatus for integrated circuit patterns formed on a wafer.

The manufacturing process of integrated circuits (LSI) is rapidly becoming more sophisticated.
Taking MOS devices as an example, the storage capacity of MOS devices is currently on the verge of transitioning from 1 megabit to 4 megabits. Along with this, pattern miniaturization,
Wafer sizes are becoming larger, and submicron pattern sizes and larger wafers (6 inches) are becoming mainstream. As wafers become larger and patterns become finer, it has become necessary to develop technology that can rapidly inspect the entire wafer at once.

[Conventional technology]

Currently, LSI inspection includes functional tests using electrical methods. However, although this type of (electrical) method can inspect patterns for disconnections, short circuits, etc., it is impossible to discover defects such as close cuts and short circuits. Therefore, visual inspection is necessary in the semiconductor manufacturing process.

On the other hand, the size of the wiring pattern on the wafer to be inspected has recently reached the submicron order, and the wafer size has increased to 6", so the amount of image information handled during inspection will be enormous. In the inspection process of LSIs, which are becoming more complex and sophisticated, it has become practically difficult to perform a complete and complete inspection using the visual inspection that has been carried out up until now, and the development of automatic visual inspection equipment has become indispensable. It's coming.

There are roughly two types of devices that can automatically test LSI patterns.

■Digital image processing type: Scans a wide area to be inspected all at once using a camera, photoelectrically converts it, digitizes it,
Automatic inspection is performed by applying inspection logic to the digital data and determining whether it matches or does not match, for example, standard pattern data.

Since inspection is performed with submicron resolution, it takes a long time (10 hours or more) to inspect the entire surface of a 6-inch wafer, and it is almost impossible to inspect the entire surface of the wafer.

■ Optical spatial processing type: Optically filters the detection signal (by executing the cutoff filter method described later)
What to inspect.

A feature of this equipment is that it is capable of inspecting large areas of wafers in near real time with submicron precision.

However, the drawback is that only regular repeating patterns can be inspected, and irregular patterns found around the chip become noise.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a fine pattern inspection apparatus capable of inspecting the entire surface of a wafer in a relatively short amount of time.

[Means to solve the problem]

As shown in FIG. 1, the pattern inspection apparatus of the present invention includes an area dividing mechanism 10, a chip peripheral inspection system 20, and a chip center inspection system 30.

The region dividing mechanism 10 divides the chip surface into a portion A where the pattern shape of wiring etc. is relatively large and the pattern arrangement is irregular, and a portion B where the pattern shape is fine and the fine pattern is regularly repeated. Bonding pads and I/O buffers are formed around the chip,
These are large (100 to 200 μm for pads, 5 to 10-odd μm for wiring) and have no regularity, and many random black spots due to P-P marks and surface roughening are formed, and the images are irregular. Belongs to a sexual pattern. The above portion A corresponds to the peripheral area of this chip. In addition, in the center of the chip, there is a group of internal gates for logic, and a group of memory cells for memory.Memory cells are particularly small (wiring width is 1 μm or less), and there are many of them, and they are arranged regularly and repeatedly. . The above portion B corresponds to the center of this chip.

Figure 2 shows an outline of the IC pattern. A large number of chips 2 are formed on a wafer 1, and the chips 2 can be divided into a peripheral part A and a central part B depending on the size and regularity and irregularity of the pattern.

The chip periphery inspection system 20 includes a pattern imaging optical system, a detection sensor, and an image processing processor, and inspects the chip periphery A for abnormalities in appearance by digital image processing.

The chip center inspection system 30 is equipped with an optical filtering optical system and a defect detection sensor, and inspects the chip center B for presence or absence of external appearance abnormalities using a cutoff filter method.

[Effect]

In this device, an area dividing mechanism 10 divides the inspection area into a regular area (micro area, chip center) and an irregular area (macro area, chip periphery), and a chip periphery inspection system 20 divides the inspection area into a regular area (micro area, chip center) and an irregular area (macro area, chip periphery). Digital image processing is performed, and the micro area B is processed by optical filtering by the chip center inspection system 30 to inspect the appearance abnormality/normality of the chip surface pattern.

This takes advantage of the high inspection adaptability of image processing and the high inspection speed of optical filters, which allows for high-speed inspection of several seconds per chip and resolution corresponding to the pattern (for macro areas, the pattern size (e.g., several micrometers or more, or submicron resolution for micro areas), it becomes possible to inspect a wide area at once.

Inspection by optical filtering utilizes the fact that the reflected light of a laser beam from a fine repeating pattern optically undergoes Fourier transformation. That is, when a plane wave beam is incident on a repeating pattern and its transmitted or reflected light is projected through a lens, the repeating portions form a Fourier transform image and are distributed as bright spots at discrete positions. However, if there is a defect in the pattern, the pattern deviates from the pattern repeatability at that location, and the resulting light distribution has a widely diffused shape. Therefore, by masking the normal bright spot distribution, only the defect (non-repetitive component) signal can be extracted.

FIG. 3 shows the configuration of the light blocking filter optical system.

In the figure, 31 is a laser light source, 32 to 34 are ordinary lenses, and 35 to 37 are surfaces on which the target pattern is placed or imaging surfaces. Now, if a pattern 35a to be inspected is placed on the surface 35 and the pattern 35a is a regular fine pattern, a Fourier diffraction image 36a will appear on the imaging surface 36. When this image is re-imaged on the surface 37 by the lens 34, the image becomes 3
7a, that is, the first target pattern 35 after Fourier inverse transformation.
Return to a.

If the target pattern 35a has an abnormal (defect) portion d+, dz, the image of this abnormal portion on the surface 36 becomes a defect diffraction image 36b. If the target pattern 35a is both a fine repeating pattern and an abnormal area, the image at the surface 36 is a Fourier diffraction image 3.
6a and the defect diffraction image 36b, and in addition to many bright spots, the entire image appears to be faintly shining.

A light blocking filter 36C is installed on this Fourier transform surface 36 (in the figure, the black dot of the filter 36c is the light blocking part, and the surrounding white part is the light transmitting part) to block the diffraction image 36a of the normal pattern. Only the image passes through the filter 36c, and is imaged again by the lens 34 (inverse Fourier transform), so that a defect image 37b appears on the surface 37. Thus defect d. , d. can be detected.

In this cutoff filter method, if a target pattern (such as a light-transmitting mask or the like since the system in FIG. 3 is a transmission system is used; if a reflection method is used, the chip itself may be used) is placed on the surface 35, and a filter 36c is placed on the surface 36, If there is a defect in the chip pattern, a defect image 37b is obtained on the surface 37, so the inspection is instantaneous and does not require time unlike pattern comparison or numerical calculation.

FIG. 4 shows an example of a defect. In this example, the defect is a partially missing portion of the wiring pattern.

This cutoff filter method does not require calculations and is capable of extremely high-speed defect detection, but it requires that the target pattern be a periodic fine pattern, and if it is an aperiodic pattern, the target pattern itself may be defective. As a result, a Fourier analysis image 36a in which dots of zero-order terms, first-order terms, etc. are arranged in an orderly manner cannot be obtained, and light is distributed over a wide range.

Therefore, an ideal filter 36c cannot be made and a defective image 37b cannot be obtained.

Digital box image processing is used for macro area inspection, but
Since the macro area pattern has a pattern size q large and the inspection area is generally less than a fraction of the micro area, it is possible to avoid an enormous amount of processing time.

This inspection can be carried out, for example, as shown in FIG. That is, when two chips on a wafer l are inspected and parts 2a and 2b of their peripheral area A are taken out, the image is 21
a, 2lb, etc., but the degree of mismatch is detected for these image patterns (step 22). In this example, image 2
lb is normal, and image 21a has defect d. If we calculate the degree of mismatch multiple times (9 times in this example) while shifting these image patterns by n (≧1) pixels vertically, horizontally, etc., the degree of mismatch between normal patterns will be 0 when they match perfectly ( In reality, it is close to 0 because of noise, matching errors (manufacturing deviations), etc.) However, in this example, since there is a defect d, no matter how much alignment is performed, the mismatch will not become 0. Find the one with the lowest degree of inconsistency (step 23, the arrow indicates the case with the least degree of inconsistency), and find its state (the state of the time with the least degree of inconsistency among the various positions shifted)
Find the difference between images 21a and 2lb (step 24),
Filter (step 25) and leave the defective image (step 26).

Note that the difference between normal patterns does not become 0 as described above, but the noise component can be removed by removing isolated points, and the difference due to matching error can be removed as being larger than the window W, leaving only the defect.

In FIG. 5, small area 2a. 2b is to be compared, therefore, for the inspection of the chip peripheral area A, the small head area 2a. 2b is moved around the entire circumference of the chip. Of course, the small head regions 2a and 2b may be expanded to cover the entire peripheral area A, and in this case, the above movement is not necessary. The two chips in FIG. 5 may be two arbitrarily selected chips on the wafer, but one may be used as a reference and the other as a test.

It goes without saying that the reference chips are selected from those found to be defect-free in the above-mentioned inspection.

The method shown in FIG. 6 (feature extraction method) can also be used to inspect the macro area. (a) (g)) are cases in which the wiring pattern is normal, and (C) and (d) are cases in which it is defective. (a
)l1, the width 2 of the wiring pattern 27 in the horizontal, vertical, and diagonal directions.
8 is found along each point on the center line, and in (b), the diameter of the circle 29 inscribed in the wiring pattern 27 is found along each point on the center line. (a) [Yes]) is normal, so the width 28 is the same at each point, and the diameter of the inscribed circle is also the same at each point, but (C)
If there is a defect d as shown in (d), the width becomes short as 280 and the diameter of the inscribed circle becomes small as 29a, which makes it possible to know the existence of the defect d.

Figure 3 deals with the center of the chip, and the periphery is not subject to inspection, so the periphery is masked, and Figure 5 deals with the periphery of the chip, and the center of the chip is not subject to inspection, so the center of the chip is (This masking of the center is not actually necessary due to resolution issues.) The region dividing mechanism 10 performs this masking. The boundary line between the periphery and the center of the chip is determined according to the setting data (depending on whether it is an internal gate group or memory cell group area) or by setting the aperture (rectangular window) of the optical system to the actual chip. Alternatively, the range within the aperture where the Fourier diffraction image can be seen clearly can be set at the center of the chip, and the area outside the aperture is set at the periphery of the chip. Of course, once a boundary line is determined for one chip, the boundary line can also be applied to other chips (chips of the same type) on the same wafer.

〔Example〕

FIG. 7 shows the configuration of the optical system of the pattern inspection apparatus of the present invention. Laser light source 31, lens 3 constituting the exbander
2, a reflecting mirror 38, a beam splitter 39, an area shutter 41, an FT lens 33, a filter 36c, an IFT lens 34, and a CCD (area sensor, movable) 40 constitute a chip center inspection system 30. Further, an objective lens 42, an imaging lens 43, and a COD (area sensor, movable) 50 constitute an optical system of the chip peripheral inspection system 20. The optical system of this chip peripheral inspection system 20 is for two chips, and the COD 50 etc. are assumed to be two (two-head camera).

The area shutter 41 projects a laser beam onto the center of the chip, excluding the periphery of the chip. Placing it directly above the wafer (not shown) on the sample stage 37 is advantageous for high-precision masking. Furthermore, since the chip center inspection system and the chip peripheral inspection system do not need to inspect the center and periphery of the same chip at the same time, the fields of view of the objective lens 42 and the FT lens 33 may be on different chips. This is lens 42
This is advantageous in that the lens 33 and the lens 33 are arranged at different positions (this is necessary).

FIG. 8 shows an embodiment of the present invention including a control system.

The sample stage 37 is capable of two-dimensional movement in the X and Y directions and rotation in the θ direction, and a stage controller 37A controls these movements. The laser light source 31 is controlled by a laser power controller 31A, and these controllers 3
7A and 31A are connected to a common bus CB via an input/output adapter I/O, and are controlled by a processor CPU.

COD camera 40.50a, 50b is communication control device CC
U. ~ is connected to the above I/O via the CCU 3, and the lighting system controller 51 is also connected to the I/O. ■B. -V
B. is a video bus, and M1 to M3 are gray box image memories. The display device iDI is connected to the bus CB via the display controller.
sP is connected to the hard disk device and floppy disk device FDD via the disk controller, and the adapter I/O is connected to the printer PR, keyboard KB, L.
C shutter array LCSA and macro closure mask MCM are connected.

Furthermore, a density histogram creation means, a defect position memory, a matching circuit, a filter circuit, an image transfer means, etc. are connected to the bus CB. The pattern inspection performed with these is as described above.

The defect image 26 and the defect image 37b written in the defect position memory are displayed on the display device DISP and/or recorded on the disk HDD, FDD, and printer PR.

FIG. 9 shows the flow of pattern inspection processing. Sample stand 37
Set the wafer 1 on top ■, decide the target position (chip to be inspected) of the macro system and micro system and set the desired settings ■, then focus the macro system and detect the chip periphery. ■, l5 l6 Divide the area by determining the boundary line between the periphery and the center of the chip■. Specifically, make a mask (41 etc.) and set it. For the micro system, a filter 36c is prepared (1), this filter is set on the surface 36, the focus is taken (2), and the micro system is inspected (2). We will also focus on macro systems and perform macro system inspections [phase]. Defects are detected through these inspections and displayed, recorded, etc.

To create the filter 36c, simply place the photosensitive film on side 3.
6 and expose the defect-free target pattern at surface 35;
This can be done by developing. Filter 3 as described below
A liquid crystal can also be used for 6c.

FIG. 10 shows a specific example of the area shutter. Movable plate 41
a and 4lb move in opposite directions to each other in the X direction, and the movable plate 4
1c and 41d move in opposite directions to each other in the Y direction, thereby enlarging/reducing the window W formed by the four movable plates 41a to 41d. Motor 41e, wire 41f and pulley 41
g opens and closes movable plates 4la and 4lb, and motor 41h, wire 411 and pulley 41j open and close movable plates 41c and 41d.
Open and close.

The window W limits the beam projection area so that the light beam is projected only onto the center B of the IC chip.

41k and 441 are movable plates 41a and 4lbg? , and 4
1m and 41n are guide frames for movable plates 41c and 41d.

In addition to providing the area shutter 41 on the wafer 1 as shown in FIG. 11 (this is the same as in FIG. 7), the area shutter 41 is provided in the optical system (expander ) may be provided. Although not shown, IFT
It is also possible to remove the peripheral portion of the chip by disposing it after 34.

In these FIGS. 11 and 12, in addition to the Fourier image forming lens system 54, an inspection lens system 5 is mounted on the stage 56.
5 is set.

Region division can be performed using a macro inspection optical system. First, the entire chip pattern is photographed using a macro inspection optical system, and the outline of the micro area is extracted from the obtained image. It is easy to distinguish between the periphery and the center of the chip). The movable plate of the area shutter 41 is moved to the extracted area outline to limit the inspection area.

Macro areas are inspected using white light as a light source.

The illumination system controller 5l in FIG. 8 is a controller for this white light source.

FIG. 13 shows a flowchart of the inspection procedure. Set the wafer 1 on the sample stage 37 ■, take macro focus ■
, Determine the microscopic inspection area (■), and calculate the mask shape (■). The area shutter 4l is opened and closed (2) so that the calculated mask shape is obtained, and the microscopic focus (2) is taken.

Next, the cutoff filter 36c is set (1), the inspection optical system is set (2), the inspection image is detected (2), and a defect is determined.

The cutoff filter 36c may be a liquid crystal plate, as shown in FIG.
This liquid crystal panel is used in Figure 2. 53 is a liquid crystal (LCD)
) is a controller.

FIG. 14 shows an outline of the liquid crystal filter. Reference numeral 60 denotes a liquid crystal plate, which is composed of a large number of cells arranged in a matrix, each cell having transparent substrates 61, 62 and transparent electrodes 6 as shown in FIG.
3 and 64, a liquid crystal molecule alignment layer 65 (rubbing direction -), a liquid crystal molecule alignment layer 66 (rubbing direction 1), and a sealing material 67, and the inside thereof is filled with liquid crystal.

Polarizers 68 and 69 are placed above and below, and the laser beam is projected to pass through these.

The laser light incident on this filter is transmitted through the transparent electrodes 63 and 64.
The polarization state changes by 90 degrees depending on whether the voltage is the same or not, and is turned on or off by the polarizer 69 on the output side. (C) shows a state in which the voltage is not uniform across the electrodes and the incident light passes through, and (C) shows a state in which the voltage is uniform in the electrodes and the incident light is blocked.

This liquid crystal filter 36c is set, for example, as shown in FIG. 11, and first the liquid crystal filter is brought into a completely transmitting state, and the imaging optical system 55 of the cut-off filter surface 36 is used (55 can be replaced with 54 by a switch operation). Detects the light intensity distribution. Since a normal signal has a light intensity above a certain level, a pattern of the cutoff filter 36c is created on the processor CPU depending on the strength of the detection signal. This pattern signal is
It is sent to the CD controller 53 and turns on/off each cell of the liquid crystal board.
Then, a two-dimensional cutoff filter having the pattern shown in FIG. 36a is formed.

The method of creating a cut-off filter by exposing and developing a photosensitive plate requires wet processing, but this cut-off filter using liquid crystal can be created instantly electrically and does not require wet processing, so it can be used as an in-line filter. It becomes possible to create.

FIG. 15 shows an inspection procedure using a liquid crystal filter. Set the wafer on the sample stage ■, set the liquid crystal filter to the fully transmitting state ■, set the micro area ■, create an area division filter and set the optical system ■, focus ■, and detect the Fourier image. ■, Set the slice level for the detection light intensity ■, Calculate the cut-off filter pattern ■, Write the pattern to the liquid crystal filter ■, Set the inspection optical system [Phase], Inspection element detection, Defect Perform detection■.

In calculating the cutoff filter pattern, if the detected light intensity is above the slice level, the liquid crystal cell is turned on, and if it is below, the liquid crystal cell is turned off. In addition to determining the pattern of the cutoff filter from the actual chip pattern, the pattern may be determined by Fourier calculation from the chip pattern information obtained as design data, and this pattern may be written to the liquid crystal filter.

〔Effect of the invention〕

As explained above, according to the present invention, high-speed, high-resolution, wide-area batch inspection of chip patterns can be performed, and LSI
Since 100% inspection of the entire surface is possible, it greatly contributes to higher efficiency and labor savings in the wafer process.

In addition, by using the area dividing shutter shown in Figure 10, the inspection area can be divided optically, making it possible to inspect the entire wafer at high speed and with high resolution. , it is possible to form optical cutoff filters in-line, and high-speed, high-resolution 100% inspection of the entire wafer surface is possible.

2l

[Brief explanation of the drawing]

Figure 1 is an illustration of the principle of the present invention, Figure 2 is an illustration of an IC pattern, Figure 3 is an illustration of a spatial filtering method, Figure 4 is an illustration of an example of a chip defect, and Figure 5 is a macro inspection. FIG. 6 is an explanatory diagram of another example of macro inspection. FIG. 7 is an explanatory diagram of the optical system of the inspection device. FIG. 8 is an explanatory diagram of the outline of the inspection device including the control system. The figure is a flowchart showing the inspection procedure, Figure 10 is a perspective view of the area dividing shutter, Figures 11 and 12 are perspective views showing an example of the arrangement of the area dividing shutter, and Figure 13 is an example of the operation of the area dividing shutter. Flowchart FIG. 14 is an explanatory diagram of a liquid crystal filter, and FIG. 15 is a flowchart showing an example of creating a liquid crystal filter. ■

Claims (1)

[Claims] 1. An integrated circuit chip on a wafer is divided into a peripheral area (A) of the chip consisting of a pattern with no regularity in arrangement, and a central area (B) of the chip consisting of a repeated fine pattern. a region dividing mechanism (10) for inspecting the chip periphery, a chip periphery inspection system (20) comprising a pattern imaging optical system for inspecting the chip periphery, a detection sensor, and an image processing processor; and a chip periphery inspection system (20) for inspecting the chip center. a chip center inspection system (30) comprising an optical filtering optical system and a defect detection sensor; A pattern inspection device characterized by: