JPH0213196A - Semiconductor picture memory - Google Patents

Abstract

PURPOSE:To simplify control by providing a control means varying data delay in the unit of one scanning line of a television signal and a control means varying the data delay of a part corresponding to the scanning line in the unit of bits. CONSTITUTION:An inputted data is stored tentatively in write data registers 103, 104 and written in the lump in memory cells 106, 107 when the write data registers 103, 104 are occupied. In the case of reading a data from the memory cells 106, 107, the data of quantity corresponding to the picture element number of one scanning line is transferred to read data registers 108, 109 and then outputted. Since the memory cells 106, 107 have a capacity corresponding to the picture element number of one field or one frame of a television signal, a delay circuit of one field or one frame is realized by having only to control the timing of data write/readout in matching with the television signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor image memories. More specifically, the bit length of a portion in which a data delay corresponding to one field or one frame of a television signal is obtained, and the amount of data delay corresponds to one scanning line unit and at least one scanning line of the television signal. The present invention relates to a semiconductor image memory that is variable in bit units.

2. Description of the Related Art Conventionally, in devices that handle television signals, typically color televisions, the television signals are analog-processed within the device and reproduced as images from a cathode ray tube. However, when processing images using analog signals, it is extremely difficult to temporarily store the image signals, process them, delay them in the time axis direction, and compare images between fields or frames to determine image quality. It was difficult. Therefore, by converting an analog image signal into a digital signal and storing the data in a conductor memory, data processing between fields or frames by data processing or data delay has come to be performed.

For example, the broadcasting system in Japan and the United States, NTSC
In this method, one field is composed of 262.5 horizontal scanning lines, and by interlacing, two fields constitute one frame (525 scanning lines) of the screen, that is, one spatially complete picture. We are adopting a method to do so. By streaming the frames at a rate of 30 times/second, a continuous screen is constructed.

Therefore, when performing image processing using data delay caused by an image memory, an image memory that can obtain data delay corresponding to the field or frame size is required. In this case, the analog signal is sampled and digitized, for example, the color signal subcarrier frequency (fsc
#3. When sampling at a frequency four times that of 58M1, a sampling link point of 910 bits (address) is required per horizontal scanning line. required a memory capacity of 910 x 263 x n bits for field memory and 910 x 525 x n bits for frame memory, depending on the number of scanning lines. Here, n is the number of gradations per pixel/sampling point, and 525 is the number of scanning lines per frame. 263 is the number of scanning lines per field, and it is actually a 262.5 tree, but in order to align the starting positions of the scanning lines between fields, 263 is the number of scanning lines per field.
Alternatively, 262 may be used, and when used as a one-field or one-frame delay element, peripheral circuits are connected in cascade to this memory. Processing is also carried out in which a line memory is used as a delay line for one scanning line, and a bit delay element is provided to process data in units of one bit (pixel), and the whole is used as a delay circuit for one field or one frame. ing.

FIG. 2 shows an example of a circuit using a conventional semiconductor image memory. The circuit shown in FIG. 2 is an example of a noise reducer circuit that utilizes correlation between frames.

This circuit includes a multiplier 21 that multiplies video signal input data by (here, K is O≦≦1) and outputs the multiplier to an adder 23;
A multiplier 22 that multiplies the video signal that has passed through the delay circuit 25 by (1-K) and also outputs it to the adder 23, and contacts N21 and N
A motion detector 24 compares the data between 22 and detects whether there is movement, and if there is movement, changes the value of K and outputs it to the multipliers 21 and 22 according to the motion detected.
and a delay circuit 25 corresponding to about one frame.

In this noise reducer circuit, the motion detector 24 compares the video signal input data with the data whose time has been shifted by one frame in the delay circuit 25, and the correlation between the two is high as in a still image. In this case, the value of K is reduced to output an average value with respect to the picture of the previous frame, and a picture with suppressed randomly generated noise is output. Furthermore, when the correlation between the two is low as in the case of a moving image, the value of K is increased to increase the ratio of new data and the video signal is output.

What is important in this circuit is that the delay amount of the data at the contact N22 must be delayed by exactly one frame with respect to the data at the contact N21. All frame delay circuits 25 must provide exactly one frame of data delay. Therefore, about 1 frame delay circuit 25
required an operation to change the amount of delay depending on the circuits connected to the periphery.

Problems to be Solved by the Invention Conventionally, when data delay corresponding to one field or one frame as described above was performed using a memory, a general-purpose dynamic RAM was used. Therefore, address control and reflexology control were necessary. In addition, in order to use it as a data delay, it is necessary to write and read at the same time, and furthermore, the amount of data delay must be changed according to the circuits connected to the periphery, making control extremely complicated. There was a drawback.

Therefore, an object of the present invention is to solve the problems of the prior art described above and to provide a semiconductor image memory that does not require complicated control.

Means for Solving the Problems According to the present invention, a write data register and a read data register each having a capacity corresponding to the pixel amount of one scanning line of a television signal, and a pixel amount of one field or one frame of the television signal are provided. a memory cell with a capacity corresponding to the write data register, a transfer means for transferring and writing data input to the write data register in blocks corresponding to the memory capacity of the write data register to the memory cell; and a memory cell. The data stored within
an output means for transferring the data in blocks corresponding to the memory capacity of the read data register i'+ij to the read data register and outputting from the read data register, and outputting from the read data register 411; The amount of delay of the data is changed in units of one scanning line of the television signal so that the data input to the write data register is delayed by a pixel equivalent to one field or one frame of the television signal from the data input to the write data register. There is provided a semiconductor image memory characterized in that it has a control means and a control means for changing the amount of data delay of a portion corresponding to at least one scanning line within an l field or one frame on a bit by bit basis.

Operation The semiconductor image memory of the present invention includes a write data register and a read data register with capacities corresponding to the number of pixels in one scanning line of a television signal, and
The memory cell has a capacity corresponding to the number of pixels in a field or one frame. The input data is temporarily stored in the write data register, and when the write data register becomes full, it is written to the memory cell array. When reading data from a memory cell, (1) data in an amount corresponding to the number of pixels of a scanning line is transferred all at once to a read data register and then output.

A memory cell has a capacity corresponding to the number of pixels in one field or one frame of a television signal, so by simply controlling the timing of data writing and reading according to the television signal, one field or one frame can be stored. delay circuit can be realized.

Furthermore, the amount of data delay can be changed in accordance with the amount of peripheral line memories and bit delay elements using only control signals regarding the number of lines of memory cells and the number of bits in any one row of memory cells.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an example of a semiconductor image memory of the present invention.

Data input from the data input terminal Din is temporarily stored and accumulated in write data registers 103k and 104. The write address of the above data is determined by the Carano decoders 101 and 102 by the write address generator 11.
The column addresses where 2 occurs are decoded and selected respectively.

The write data register 103 has a capacity to hold four pieces of data, and when it is full, the write control circuit 11 (described later)
By the signal generated by 6, 4 pieces of data are batched into m rows x
The signal is output to the row selected by the row decoder 105 of the first memory cell array 106 having a β column configuration. Similarly, when the write data register 104, which has a capacity for storing β' pieces of data, becomes full, the write data register 104, which has a configuration of m rows and β' columns, collects the β' pieces of data at once by a signal generated by the control circuit 116. The output signal is output to the row selected by the row decoder 105 of the second memory cell array 107.

The data in each row of the memory cell array 106 is stored in a read data register 108, which also has a capacity to hold β pieces of data.
The data in each row of the memory cell array 107 is transferred to a read data register 109 having a capacity for storing β' pieces of data in response to a signal generated by a read control circuit 117, which will be described later, and is stored and accumulated.

The data in read data registers 108 and 109 are as follows:
The read address on read data registers 108 and 109 is selected by column decoders 110 and 111 decoding the column address generated by read address generator 113.

When memory cell arrays 106 and 107 are configured with dynamic memories, a refresh address generator 114 consisting of a refresh timer and a counter for generating addresses is required.

Write row address generated by the write address generator 112, read row address generated by the read address generator 113, and refresh address generator 1
The refresh addresses generated by 14 are switched by multiplexer 115.

Write clock signal WCK and write address generator 11
The write control circuit 116, which receives as input the ``γ signal j:l, ff ding digit 1'' for restoring the write address of 2 to 1 (initial value), generates the write address generator described above based on these signals. 112, and also generates an increment signal and a clear signal for the write data register 103.
The data accumulated in the memory cell array 106 is
A control signal is generated for collectively transferring the data stored in the data register 104 to each row of the memory cell array 107.

Similarly, the read control circuit 11 receives the read clock signal RCK and the clear signal [to return the read address of the read address generator 113 to 1 (initial value)].
7 is a read address generator 11 based on these signals.
3, generates an increment signal and a clear signal, and also sends data for each row of the memory cell array 106 to the read data register 108 and data for each row of the memory cell array 107 to the read data register 109. Generates control signals for transfer.

Furthermore, the write address generator 112 and the read address generator 113 are also controlled by a line number/line length control circuit 118 that outputs a control signal based on the set values of line number and line length setting signals input from the outside. be done.

In the present invention, β+β' corresponding to one row of the above memory cell array is the number of pixels of one scanning line of a television signal or 1/2K of one scanning line (K=1.2,...)
The number of addresses corresponds to the number of pixels. For example, in the NTSC system, which is the broadcasting system in North America and Japan, one line of analog signal is transmitted at a frequency four times the color signal subcarrier frequency (
When sampling at 4 fsc), the number of pixels in one scanning line is 910, so β+β'=910 (β=β' = 45
5) Or! +1' = 910 /2 = 455 (
β=228, β′=227′), etc. may be considered.

Similarly, in the PAL system, which is the broadcasting system used in Western Europe, the Middle East, and South America, the number of pixels in one scanning line is 11.
It will be 35, so R+I! ' = 1135 (j7 = 56
8, l'-567>.

Next, the operation of the semiconductor image memory of this embodiment configured as described above will be explained.

Writing to the semiconductor image memory described above is performed as follows. Well, A$ times the signal.

The write address generator 112 is cleared, and the write column address and row address are set to address 1.

When clearing is completed, the column address is incremented by the WCK signal, and the data input from the Din terminal corresponding to each address is transferred to the write data register 10.
3 is stored. ! When writing is performed once, the write data register 103 becomes full, and data is similarly stored in the write data register 104. At the same time, the write control circuit 116 detects that the write data register 103 is full, and the write control circuit 116 detects that the write data register 103 is full.
A control signal is generated for transferring the data of 3 all at once to the first row (first row) of the first memory cell array 106.

After data has been written to the write data register 104 β' times, the data in the write data register 104 is transferred all at once to the first row (first row) of the second memory cell array 107 by the write control circuit 116. At this time, the write column address is reset to address 1, and data from the Din terminal is again stored in the write data register 103 in synchronization with the write clock WCK.

When the column address for writing is reset to address 1, the row address for writing is incremented by one address, and at this time, the data in the newly stored write data registers 103 and 104 are respectively stored in the memory cell arrays 106 and 107. Transferred and stored in the second line.

Similarly, write data registers 103 and 104
The contents of the memory cell arrays 106 and 107 are transferred to addresses sequentially incremented from the third row to the fourth row, and when the last row is reached, the data transfer of the write data register is repeated again from the first row.

Reading is performed as follows. The read address generator 113 is cleared by the πT sign π signal, and the read column address and row address are set to address 1. At the same time, the first memory cell array 106 and the second memory cell array 106 are cleared during the clearing period. The data in the first row of memory cell array 107 is collectively transferred to read data registers 108 and 109, respectively.

When clearing and associated data transfer operations are completed, the column address is incremented based on the RCK signal, and the read data register 108 is incremented corresponding to each address.
Reading is performed from. The second
When the data transfer from the first row of the memory cell array 107 to the read data register 109 is completed, the read row address is incremented by one address. Therefore, after one reading from the read data register 108 is completed after clearing, the read data register 108
Reading starts from 9, and at the same time, the read control circuit transfers the data in the second row of the first memory cell array 106 to the read data register 108 in batches. Further, when reading is performed p' times from the read data register 109, the data in the second row of the second memory cell array 107 is transferred to the read data register 109, and at the same time, the read row address is incremented by one.

Similarly, when reading from the read data register is completed, data is transferred from the incremented address sequentially to the third and fourth rows of the memory cell array, and when the last row is reached, read data is transferred again from the first row. is repeated.

In the semiconductor image memory of the present invention, WCK and RCK are connected in common and the same clock signal is input. Similarly, T1 at the bottom and T1 at the bottom are connected in common, and the same clear signal is input. By simultaneously inputting a clear signal, both write and read addresses are cleared to address 1, and write data is written and read data is read to the same address in the write data register and read data register, respectively. In the semiconductor image memory of the present invention, write data is transferred to the memory cell array after the write data register is full. Therefore, read data when the write address and read address are the same is data delayed by exactly the amount of pixels corresponding to all addresses of this memory cell array.

Therefore, for example, in the case of 4 fsc sampling in the NTSC system, if β+β' is 910, the number of rows in the memory cell array is m.
If m is set to 263 (or 262), a delay line corresponding to one field will be obtained, and if m is set to 525, a delay line corresponding to one frame will be obtained.

Next, in the memory of the present invention, data transfer from the write data register to the memory cell, data transfer from the memory cell to the read data register, and refreshing.
We will explain the case where both are requested at the same time. In this case, an access order arbitration circuit (not shown) is provided, so that even if three requests are made at the same time, they can be performed one by one in an orderly manner. Further, even if a transfer request for the write data register and the read data register occurs, since access from the Din and Dout terminals is performed from the other register, writing or reading will not be interrupted.

Generally, this data transfer or refresh period ends in about 300 ns. On the other hand, β+β' -91
When the address is 0, the access period for one register is approximately 32 μs, so data transfer to the write data register memory cell, data transfer from memory cell to read data register, and refresh must be completed within 32 μs. is quite possible.

The semiconductor image memory of the present invention also includes a number of lines that allows the memory capacity of the first memory cell array + second memory cell array to be adjusted in units of rows and in units of bits per row;
A line length control circuit 118 is provided.

The above line number and line length control circuit determines the last row of write and read row addresses in one address unit according to the setting value of the line number setting signal input from the outside, and when the last row is reached, the first row The configuration is such that a control signal that returns to the first row) is generated. With this configuration, it is possible to change the memory capacity by one line of the television signal.

Also, only when the write address and read address reach the final line set by the line number setting signal, the line length setting signal becomes valid, and the reset address of the column address is changed in units of column addresses according to the set value. The structure should be such that it can be done. With this configuration, it is possible to change the line length of the last row of a field or frame on a bit-by-bit basis.

As explained above, the present invention has a function of varying line by line corresponding to one scanning period of a television signal or at least one line by bit.
An image memory that can be used as a delay line for pixels corresponding to one field or one frame can be realized. In reality, there are 1 to 2 line memories connected to this image memory and the delay circuit in bit units is about 10 to 15 bits, so the variable amount in line units is the last 4 lines, and the variable amount in bit units is about 10 to 15 bits. There is no problem in using the last 16 bits 71- of the final line.

For example, to make this memory a frame memory of NTSC system 4fsc sampling, the number of line setting signals should be two, the line length setting signals should be four, and β+β' should be 910 addresses. With this configuration, m can be set from 525 to 522 in units of one line, and the final line length can be set to any value from 910 to 895 addresses in units of one address.

Incidentally, since the bit delay element can be manufactured manually at low cost, by externally attaching it and adjusting it, it is also possible to make the final line length variable, such as in units of 2 addresses, units of 4 addresses, and so on.

As described in detail, the present invention allows the data delay corresponding to one field or one frame and the amount of data delay corresponding to the amount of externally connected line memory and bit delay elements to be adjusted by simple control. , exactly 1 including surrounding circuits
A field or one frame delay circuit is provided.

The following explanation is based on the case where the NTSC television signal is sampled at 4fsc, but the sampling rate can be set to 3fsc, 2fsc, etc. without particular limitation.

Furthermore, even if the television system is different, such as the PAL system, Koyoshi et al. can design the system by changing the memory capacity accordingly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of the semiconductor image memory of the present invention, and FIG. 2 is a block diagram showing an example of use of the frame delay element. [Main reference number] 101.102 ...Write column decoder, 1
03.104 ...Write data register, 105
...Row decoder, 106.107 ...Memorial array, 108.
109...Read data register, 110.11
1... Read column decoder, 112...
-Write address generator, 113... Read address generator, 114... Refresh address generator, 115... Address switching multiplexer, 116... Write control circuit, 117... Read control circuit, 118 ...Line number/line length control circuit, WCK
...Write clock, RCK...Read clock, Vte1dpi...Write address clear signal, -DetekotsuX...Read address clear signal, 21.22...
・Multiplier, 23... Adder, 24... Motion detector, 25... Approximately 1 frame delay circuit Patent applicant NEC Corporation Representative Patent attorney Takashi Senjo

Claims (1)

[Claims] A write data register and a read data register having a capacity corresponding to the amount of pixels of one scanning line of the television signal, a memory cell having a capacity corresponding to the amount of pixels of one field or one frame of the television signal, and the write data A transfer unit that transfers and writes data input to the register in block units corresponding to the memory capacity of the write data register to a memory cell; output means for collectively transferring blocks corresponding to the memory capacity of the register to the read data register and outputting from the read data register, wherein the data output from the read data register is the write data. A control means for changing the amount of delay of the data in units of one scanning line of the television signal so that the data input to the register is delayed by a pixel equivalent to one field or one frame of the television signal, and one field or one frame. What is claimed is: 1. A semiconductor image memory comprising: control means for changing a data delay amount of a portion corresponding to at least one scanning line in bit units.