JPH02130813A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To immediately cope with occurrence of defects when it happens by simultaneously exposing a mark indicating the kind of an exposure mask for forming a P<+>-type layer in a target pattern. CONSTITUTION:In a semiconductor wafer 10, an N<+>-type layer 2 is formed on the rear, while a P<+>-type layer 3 is formed on the surface, and chip patterns 11 for forming a P-N diode are drawn crosswise and in a large number, while target patterns 12 for wafer alignment are drawn. Indication marks 13P<+>1, P<+>2... indicating the kinds of exposure masks are drawn inside an area of a target pattern 12. In case of poor condition is generated according to capacity measurement in a wafer 10 condition on a manufacture line, an area ratio of the exposure mask used by above-mentioned indication mark 13 inside a target pattern 12 is judged. Then, basing on a measurement result, judgment is shown to what extent the connection capacity is to be increased or decreased. Then, after a mask to be used is selected, the mask of an afore-selected kind is used from the next lot. When a mask is changed, a connection area to be formed by the P<+>-type layer 3 can be changed, so that the connection capacity C can be controlled to the value nearer to the designed value.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a variable capacitance diode, which facilitates control of manufacturing conditions.

(b) Conventional technology The conventional variable capacitance diode shown in FIG. ), then a P" type layer (3) is formed on the surface of the N type shrimp layer (2) by selective diffusion, and a P" type layer (3) is formed through the contact hole of the surface oxide film (4). Ohmink contact electrode (
5).

Junction capacitance C is the main electrical characteristic of the variable capacitance diode with this configuration. This characteristic is due to the P
There is a close relationship with the area of the type 4 layer (3), and the design accuracy is extremely strict, so small fluctuations in the capacitance value due to process variations cannot be overlooked. Therefore, in the past, the junction capacitance C was measured in a wafer state in which the formation of the P" type layer (3) was completed by placing one epitaxial wafer in advance, and based on this value, the P3 type layer (3) of the subsequent lot wafer was determined appropriately. Select an appropriate exposure mask from a plurality of exposure masks for forming the P1 type layer (3) having different diffusion window areas so as to form a bonding area of
The next lot wafer to be processed was manufactured using the selected exposure mask, so that the value of the junction capacitance C was strictly controlled.

(c) Problems to be solved by the invention However, if the value of junction capacitance C becomes out of specification due to abnormality in the process, etc., which type of mask for forming the P0 type layer (3) should be selected among multiple types of P0 type layer (3) formation masks. The only way to determine whether a product was used was by checking records during the manufacturing process, which had the disadvantage of delaying response in the event of a defect.

(d) Means for Solving the Problems In view of the above-mentioned conventional problems, the present invention provides a target pattern (
By simultaneously exposing a symbol (13) representing the type of the exposure mask for forming the P+ type layer (3) in <12>, a method for manufacturing a semiconductor device is provided in which immediate action can be taken when a defect occurs.

(E) Function According to the present invention, since the display symbol (13) is exposed on the target pattern (12), it is possible to immediately determine which exposure mask was used in the state of the wafer (10). Moreover, since such display symbols are not attached to the chip pattern (11), there is no problem in appearance.

(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

The semiconductor wafer (10) shown in FIG. 1 has an N+ type layer (2) formed on its back surface, and a P+ type layer (3) formed on its front surface using a well-known selective diffusion technique.
A large number of chip patterns (11) for forming N diodes are drawn vertically and horizontally, and target patterns (12) for wafer alignment are drawn at two locations on the left and right.

Then, the oxide film (4) on the surface of the wafer (10) is photo-etched as an exposure mask for forming the P1 type layer (3), and is used as a selection mask for diffusion. A pattern corresponding to the selection mask for forming the target pattern (
12) Display symbols (13) P"1, P"2, P"3, . . . representing the types of the exposure masks are drawn in the area.

The display symbol (13) indicates the size (area) of the pattern for forming the P" type layer (3) by indicating the type of exposure mask, and the relationship is as shown in Table 1, for example.

Table 1 If a defect occurs in the capacitance measurement of wafer (10) on the actual production line, the area ratio of the exposure mask currently used will be determined by the display symbol (13) in the target pattern (12). Determine whether it has. After determining how much the junction capacitance C should be increased or decreased based on the above measurement results and selecting which mask to use, it is sufficient to use the selected type of mask from the current lot. , by changing the mask, the P1 type layer (3
) can change the junction area formed, so the junction capacitance C can be controlled to a value closer to the design value during manufacture. Thereafter, the individual chip patterns (11) are divided and each is housed in a package.

(G) As described in detail, according to the present invention, the target pattern (
Since the display symbol (13) is exposed in 12), it is possible to immediately determine what type of mask was used in the state of the wafer (10), which has the advantage of being able to immediately respond to process variations. Therefore, it can also contribute to improving yield.

Also, since the chip pattern (11) is not provided on the main body,
It is possible to solve the problem that different patterns are drawn on the chip pattern (11) in the same model.

[Brief explanation of the drawing]

FIG. 1 is a plan view for explaining the present invention, and FIG. 2 is a sectional view showing a PN diode.

Claims (2)

[Claims] (1) Anode/cathode junctions are formed on each chip by simultaneously exposing multiple chip patterns and multiple alignment target patterns on one wafer to diffuse impurities, and the capacitance of the anode/cathode junctions is formed on each chip. A method for manufacturing a semiconductor device in which a value is measured and the type of exposure mask used for the next manufactured lot is sequentially changed based on the value, wherein a symbol indicating the type of the exposure mask is placed in the target pattern area during the exposure. A method for manufacturing a semiconductor device characterized by printing. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the anode/cathode junction is a PN junction.