JPH02129946A - High power thick film hybrid ic package - Google Patents
High power thick film hybrid ic packageInfo
- Publication number
- JPH02129946A JPH02129946A JP63282588A JP28258888A JPH02129946A JP H02129946 A JPH02129946 A JP H02129946A JP 63282588 A JP63282588 A JP 63282588A JP 28258888 A JP28258888 A JP 28258888A JP H02129946 A JPH02129946 A JP H02129946A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- frame
- board
- thick film
- wind frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 239000011521 glass Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 6
- 238000003466 welding Methods 0.000 abstract description 3
- 239000003566 sealing material Substances 0.000 abstract description 2
- 230000005855 radiation Effects 0.000 abstract 2
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000005476 soldering Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、高電力用厚膜ハイブリッドＩＣのパッケージ
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a package for a high power thick film hybrid IC.
（発明の背景）
高電力用のハイブリッドＩＣでは大きい電力が流れるた
めに発熱量が多くなり、従って放熱性の良いパッケージ
であることが必要である。(Background of the Invention) Hybrid ICs for high power use generate a large amount of heat due to the flow of large amounts of power, and therefore require a package with good heat dissipation.
第３図はこの種のＩＣに用いられている従来のパッケー
ジを示す断面図である。この図で符号１０はセラミック
基板であり、この基板ｌＯの一側面（上面）に抵抗や導
体あるいは誘電体、保護膜などが形成されている。すな
わち基板１０に厚膜ペーストで抵抗を含む回路がスクリ
ーン印刷され、その後加熱してこの回路を焼付け、必要
な箇所に保護膜を形成したものである。この回路には、
半導体ＩＣ１２やコンデンサチップ１４などの部品がワ
イヤボンディング法やハンダリフロー法、ハンダ浸漬法
などにより接続・固定される。FIG. 3 is a sectional view showing a conventional package used for this type of IC. In this figure, reference numeral 10 is a ceramic substrate, and a resistor, a conductor, a dielectric, a protective film, etc. are formed on one side (upper surface) of this substrate IO. That is, a circuit including a resistor is screen-printed on the substrate 10 using thick film paste, and then heated to bake the circuit and form a protective film at the necessary locations. This circuit has
Components such as the semiconductor IC 12 and the capacitor chip 14 are connected and fixed by a wire bonding method, a solder reflow method, a solder dipping method, or the like.
１６はケースであり銅、銅−タングステン合金等の金属
により上に開いた略箱状に作られている。Reference numeral 16 denotes a case, which is made of metal such as copper or copper-tungsten alloy and has a substantially box shape that is open upward.
このケース１６の側壁には複数本のメタルリード１８が
ガラス封着されている。すなわちメタルリード１８はこ
のケース１６に形成した孔２０を貫通し、この孔２０内
壁からメタルリ・−ド１８が離れるように両者間にガラ
スが封止されている。A plurality of metal leads 18 are glass-sealed to the side wall of the case 16. That is, the metal lead 18 passes through a hole 20 formed in the case 16, and glass is sealed between them so that the metal lead 18 is separated from the inner wall of the hole 20.
前記のように厚膜回路が形成されかつＩＣ１２やコンデ
ンサチップ１４等の部品が実装された基板１０は、ハン
ダ付けの方法によってケース１６の内面に固定される。The substrate 10 on which the thick film circuit is formed and components such as the IC 12 and the capacitor chip 14 are mounted as described above is fixed to the inner surface of the case 16 by soldering.
図中２２はこのハンダを示している。そしてこの基板１
０上のポンディング位置をメタルリード１８にワイヤボ
ンディングした後、必要に応じて抵抗をレーザで切込ん
でトリミングする。そして最後にケース１６の開口にメ
タルカバー２４をシーム溶接したものである。22 in the figure indicates this solder. And this board 1
After wire-bonding the bonding position on 0 to the metal lead 18, the resistor is cut and trimmed with a laser if necessary. Finally, a metal cover 24 is seam-welded to the opening of the case 16.
しかしこの従来のパッケージにおいては、基板１０がケ
ース１６にハンダ付けされるため、ハンダ付は時に発生
するガスなどによりハンダ内にボイド（気泡）が混入す
るのが避けられない。このために基板１０とケース１６
との間の熱抵抗が増大し放熱性が不十分になったり、製
品ごとの熱抵抗のバラツキが大きくなって均質な製品を
得るのが困難になるという問題があった。However, in this conventional package, since the board 10 is soldered to the case 16, it is inevitable that voids (bubbles) will be mixed into the solder due to gas generated during soldering. For this purpose, the board 10 and the case 16
There have been problems in that the thermal resistance between the two products increases, resulting in insufficient heat dissipation, and the variation in thermal resistance from product to product increases, making it difficult to obtain homogeneous products.
また第４図は従来の他のパッケージを示す断面図である
。これはセラミック基板３０に抵抗等の回路と共に外部
接続用の導体膜３２も厚膜回路の手法によって形成し、
これにセラミック類のカバー３４を被せエポキシなどの
樹脂３６で固着したものである。そしてメタルリード３
８は基板３０の縁に導体膜３２を挟むようにして固定し
たものである。Moreover, FIG. 4 is a sectional view showing another conventional package. In this method, a conductor film 32 for external connection is formed on a ceramic substrate 30 along with circuits such as resistors by a thick film circuit method.
This is covered with a ceramic cover 34 and fixed with a resin 36 such as epoxy. and metal lead 3
Reference numeral 8 indicates a structure in which a conductor film 32 is fixed to the edge of a substrate 30 with a conductor film 32 sandwiched therebetween.
しかしこの場合、厚膜回路の製法で作られた導体膜３２
は許容電流が小さく電気抵抗が大きくなるため、電圧ド
ロップが大きくなるという問題があった。また樹脂を用
いるために使用温度範囲が十分広く確保できず、例えば
−３０〜＋８５°Ｃ程度に制限されるという問題もあっ
た。However, in this case, the conductor film 32 made by the thick film circuit manufacturing method
Since the allowable current is small and the electrical resistance is large, there is a problem that the voltage drop becomes large. Further, since a resin is used, a sufficiently wide usable temperature range cannot be ensured, and is limited to, for example, about -30 to +85°C.
（発明の目的）
本発明はこのような事情に鑑みなされたものであり、放
熱性が良く、放熱性のバラツキが少なくなり、また許容
電流が大きく電圧ドロップも小さくなり、さらに許容使
用温度範囲を拡大することが可能な高電力用ハイブリッ
トＩＣのパッケージを提供することを目的とする。(Objective of the Invention) The present invention has been made in view of the above circumstances, and has good heat dissipation properties, less variation in heat dissipation properties, large allowable current, small voltage drop, and further extends the allowable operating temperature range. The purpose of the present invention is to provide a high-power hybrid IC package that can be expanded.
（発明の構成）
本発明によればこの目的は、抵抗を含む厚膜回路が一側
面に形成されたアルミナ・セラミック基板に、半導体Ｉ
Ｃ等を実装した高電力用厚膜ハイブリッドＩＣにおいて
、前記基板にハンダ付けされ前記厚膜回路および実装部
品を囲む枠状のメタルウィンドフレームと、前記メタル
ウィンドフレームの他側にシーム溶接されたメタルカバ
ーと、前記メタルウィンドフレームを貫通してガラス封
着されたメタルリードとを備えることを特徴とする高電
力用厚膜ハイブリッドＩＣのパッケージにより達成され
る。(Structure of the Invention) According to the present invention, this object is to provide a semiconductor I
A high-power thick film hybrid IC mounted with C, etc., includes a frame-shaped metal window frame soldered to the board and surrounding the thick film circuit and mounted components, and a metal seam welded to the other side of the metal window frame. This is achieved by a high power thick film hybrid IC package characterized by comprising a cover and a metal lead that passes through the metal window frame and is sealed with glass.
（実施例）
第１図は本発明の一実施例の分解斜視図、第２図は断面
図である。これらの図において符号５０はアルミナ・セ
ラミック基板であり、この基板５０の一側面（上面）に
厚膜回路が形成されている。すなわち厚膜ペーストを用
いたスクリーン印刷の手法により、抵抗、導体、誘電体
、保護膜などが形成されている。この基板５０にはまた
半導体ＩＣ５２やコンデンサチップ５４等が実装されて
いる。この基板５０には、後記ウィンドフレーム５６が
ハンダ付けされる位置部分に予めメタライジングなどの
前処理を施しておき、ハンダ付けを容易に行えるように
処理する。(Embodiment) FIG. 1 is an exploded perspective view of one embodiment of the present invention, and FIG. 2 is a sectional view. In these figures, reference numeral 50 denotes an alumina ceramic substrate, and a thick film circuit is formed on one side (upper surface) of this substrate 50. That is, resistors, conductors, dielectrics, protective films, etc. are formed by screen printing using thick film paste. A semiconductor IC 52, a capacitor chip 54, etc. are also mounted on this substrate 50. This board 50 is subjected to a pretreatment such as metallization in advance at a position where a window frame 56 (described later) is to be soldered to facilitate soldering.
５６はメタルウィンドフレームであり、基板５０の外形
より僅かに小さい枠型に作られ、材料としては例えばコ
バールが用いられる。このフレーム５６には適宜の数の
孔５８が形成され、この孔５８に挿入されたメタルリー
ド６０はこの孔５８内に流入したガラス封着材によりフ
レーム５６から絶縁された状態に保持されている。Reference numeral 56 denotes a metal wind frame, which is made in a frame shape slightly smaller than the outer shape of the substrate 50, and is made of, for example, Kovar. A suitable number of holes 58 are formed in this frame 56, and the metal leads 60 inserted into these holes 58 are held in a state of being insulated from the frame 56 by the glass sealing material that has flowed into these holes 58. .
このフレーム５６は基板５０にハンダ付けされる。ハン
ダとしては例えばスズ９６．５重量％、銀３．５重量％
を含むものが好適である。このハンダ付けは、ホットプ
レート上に基板５０あるいはフレーム５６を載せて加熱
し、糸ハンダとフラックスを用いて行なうことができる
。ハンダ付は箇所に予めプリフォームハンダを設けてお
き基板５０上にフレーム５６を載せて加熱するようにす
れば、Ｎ２ （窒素）を入れたシーリングボックス内の
不活性雰囲気の下でハンダ付けを行うことも可能である
。This frame 56 is soldered to the board 50. For example, the solder is 96.5% by weight of tin and 3.5% by weight of silver.
Those containing the following are preferred. This soldering can be performed by placing the substrate 50 or the frame 56 on a hot plate and heating it, using thread solder and flux. For soldering, preform solder is provided at the location in advance, and the frame 56 is placed on the board 50 and heated, and soldering is performed under an inert atmosphere in a sealing box containing N2 (nitrogen). It is also possible.
このように基板５０にフレーム５６をハンダ付けした状
態で、基板５０の回路とメタルリード６０とがボンディ
ングワイヤを用いて接続される。そして最後にメタルカ
バー６２がフレーム５６にシーム溶接されて密封される
。すなわちメタルカバー６２の周縁部分に電極ローラを
転接させつつこのローラとフレーム５６との間に電流を
流すことによりシーム溶接される。この溶接をＮ２雰囲
気内で行えばＮ２の封入が可能である。With the frame 56 soldered to the board 50 in this manner, the circuit of the board 50 and the metal lead 60 are connected using bonding wires. Finally, the metal cover 62 is seam welded to the frame 56 and sealed. That is, seam welding is performed by rolling an electrode roller into contact with the peripheral edge of the metal cover 62 and passing a current between the roller and the frame 56. If this welding is performed in an N2 atmosphere, N2 can be sealed.
この実施例によれば一６５〜＋１５０°Ｃの範囲で使用
可能となる。According to this embodiment, it can be used in the range of -65°C to +150°C.
この実施例ではアルミナ・セラミック基板５０を用いた
が、他の材料例えば熱伝導率と熱膨張係数の点で優れた
窒化アルミ（ＡρＮ）などを用いてもよいのは勿論であ
る。Although the alumina ceramic substrate 50 is used in this embodiment, it is of course possible to use other materials such as aluminum nitride (AρN), which has excellent thermal conductivity and thermal expansion coefficient.
（発明の効果）
本発明は以上のように、厚膜回路を形成しかつ半導体Ｉ
Ｃ等の部品が実装された基板にメタルウィンドフレーム
を直接ハンダ付けすると共に、このフレームにメタルカ
バーをシーム溶接したものであるから、基板自身がパッ
ケージの外壁になり放熱性が良くなる。また基板を別の
ケースにハンダ付けする場合のように（第３図の従来例
参照）ハンダ内にボイドが発生して熱伝導が不均一にな
るおそれがなく、製品毎の放熱性のバラツキが少なくな
る。さらにメタルリードが厚膜回路に接続されるのでこ
のリード内での電気抵抗が小さくなり、電圧ドロップも
小さくなる。さらにまた樹脂を用いないから許容使用温
度範囲が広くなる、等の効果がある。(Effects of the Invention) As described above, the present invention provides a method for forming a thick film circuit and for forming a semiconductor I.
Since the metal wind frame is directly soldered to the board on which components such as C are mounted, and the metal cover is seam-welded to this frame, the board itself becomes the outer wall of the package, improving heat dissipation. In addition, unlike when soldering a board to another case (see conventional example in Figure 3), there is no risk of voids occurring in the solder and uneven heat conduction, and variations in heat dissipation from product to product are avoided. It becomes less. Furthermore, since the metal leads are connected to the thick film circuit, the electrical resistance within the leads is reduced, resulting in smaller voltage drops. Furthermore, since no resin is used, the permissible operating temperature range is widened.
第１図は本発明の一実施例の分解斜視図、第２図はその
断面図、第３図と第４図は従来のパッケージ構造を示す
断面図である。
５０・・・基板、５６・・・メタルウィンドフレーム、
６０・・・メタルリード、６２・・・メタルカバー特許
出願人 日本アビオニクス株式会社代 理 人 弁理士
山 １）文 雌
伏 理 人 弁理士 山 １）洋 資
第 ２ 図
第４図FIG. 1 is an exploded perspective view of an embodiment of the present invention, FIG. 2 is a sectional view thereof, and FIGS. 3 and 4 are sectional views showing a conventional package structure. 50... Board, 56... Metal wind frame,
60...Metal lead, 62...Metal cover Patent applicant Nippon Avionics Co., Ltd. Agent Patent attorney Yama 1) Written by Mebushi Attorney Patent attorney Yama 1) Hiroshi Shi 2nd Figure 4
Claims (1)
ナ・セラミック基板に、半導体ＩＣ等を実装した高電力
用厚膜ハイブリッドＩＣにおいて、前記基板にハンダ付
けされ前記厚膜回路および実装部品を囲む枠状のメタル
ウィンドフレームと、前記メタルウィンドフレームの他
側にシーム溶接されたメタルカバーと、前記メタルウイ
ンドフレームを貫通してガラス封着されたメタルリード
とを備えることを特徴とする高電力用厚膜ハイブリッド
ＩＣのパッケージ。(1) In a high-power thick-film hybrid IC in which a semiconductor IC or the like is mounted on an alumina ceramic substrate on which a thick-film circuit including a resistor is formed on one side, the thick-film circuit and mounted components are soldered to the substrate. A high riser characterized by comprising a frame-shaped metal wind frame surrounding the metal wind frame, a metal cover seam-welded to the other side of the metal wind frame, and a metal lead penetrating the metal wind frame and sealed with glass. Thick film hybrid IC package for power use.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63282588A JPH02129946A (en) | 1988-11-10 | 1988-11-10 | High power thick film hybrid ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63282588A JPH02129946A (en) | 1988-11-10 | 1988-11-10 | High power thick film hybrid ic package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02129946A true JPH02129946A (en) | 1990-05-18 |
| JPH0381304B2 JPH0381304B2 (en) | 1991-12-27 |
Family
ID=17654457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63282588A Granted JPH02129946A (en) | 1988-11-10 | 1988-11-10 | High power thick film hybrid ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02129946A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5700724A (en) * | 1994-08-02 | 1997-12-23 | Philips Electronic North America Corporation | Hermetically sealed package for a high power hybrid circuit |
-
1988
- 1988-11-10 JP JP63282588A patent/JPH02129946A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5700724A (en) * | 1994-08-02 | 1997-12-23 | Philips Electronic North America Corporation | Hermetically sealed package for a high power hybrid circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0381304B2 (en) | 1991-12-27 |
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