JPH02128480A - Tunnel diode type semiconductor device - Google Patents

Tunnel diode type semiconductor device

Info

Publication number
JPH02128480A
JPH02128480A JP28192688A JP28192688A JPH02128480A JP H02128480 A JPH02128480 A JP H02128480A JP 28192688 A JP28192688 A JP 28192688A JP 28192688 A JP28192688 A JP 28192688A JP H02128480 A JPH02128480 A JP H02128480A
Authority
JP
Japan
Prior art keywords
layer
electrode
thickness
inas
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28192688A
Other languages
Japanese (ja)
Inventor
Akihiko Okamoto
明彦 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP28192688A priority Critical patent/JPH02128480A/en
Publication of JPH02128480A publication Critical patent/JPH02128480A/en
Pending legal-status Critical Current

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Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices

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  • Engineering & Computer Science (AREA)
  • Nanotechnology (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To make a valley current small to increase the ratio of it to a peak current of a diode so as to improve a semiconductor element of this design in performance by a method wherein layers other than a quantum well layer constituting a tunnel diode are formed of a semiconductor layer whose valence band width is large. CONSTITUTION:The following are provided onto an N-type InAs substrate 6 to constitute a diode: an N-type InAs layer 7; an undoped GaAs layer 1 of 7nm thickness, an undoped AlNb layer 2 of 3nm thickness; an undoped InAs layers 3 of 7nm thickness; an undoped AlNb layer 4 of 3nm thickness; and an undoped GaAs layer 5 of 50nm thickness. And an n-type InAs layer 8 is epitaxially grown thereon, an electrode 10 of AuGeNi alloy is fitted to the layer 8, and an electrode 9 like the electrode 10 is fitted to the rear side of the substrate 6. The diode is composed as mentioned above, and when a voltage is applied to the electrode 9 as an anode and the electrode 8 as a cathode, a quantum level in each InAs layer is located lower than the valence band of the layers 5 and 3, so that a tunnel current penetrates the layers 5 and 4 and flows to the layer 1 penetrating the layer 2 via the quantum level of the layer 3. If the voltage is made to increase furthermore, electrons are blocked by the layer 1 and consequently a current does not flow.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はトンネルダイオード型半導体装置に関し、特に
電子親和力が異なる半導体層、又は電子親和力と禁制帯
幅との和が異なる半導体層により形成される量子準位を
用いたトンネルダオード型半導体装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a tunnel diode type semiconductor device, and in particular is formed of semiconductor layers having different electron affinities or different sums of electron affinities and forbidden band widths. This invention relates to a tunnel diode type semiconductor device using quantum levels.

〔従来の技術〕[Conventional technology]

電子親和力が異なる半導体層、あるいは電子親和力と禁
制帯幅が異なる半導体層により形成される量子準位を用
いたトンネルダイオードは、特に低温において大きな負
性抵抗が得られることより近年ますます着目されている
ものである。この型のトンネルダイオードは、例えばヒ
化ガリウム(以下GaAsと記す)層とこれより電子親
和力の小さい半導体層たとえばヒ化アルミニウムガリウ
ム(以下A、RGaAsと記す)層により形成される量
子順位を透過する電子を電極電圧で制御して動作する。
Tunnel diodes, which use quantum levels formed by semiconductor layers with different electron affinities or semiconductor layers with different electron affinities and forbidden band widths, have attracted increasing attention in recent years because of their ability to obtain large negative resistance, especially at low temperatures. It is something that exists. This type of tunnel diode transmits a quantum layer formed by, for example, a gallium arsenide (hereinafter referred to as GaAs) layer and a semiconductor layer having a lower electron affinity than this layer, such as an aluminum gallium arsenide (hereinafter referred to as A, RGaAs) layer. It operates by controlling electrons with electrode voltage.

さて、このような半導体装置において、例えば電子はG
 a A s層及び障壁となるA 4 G a A s
層を透過するが、A、ffGaAs層中ではトンネル電
流であり、一般にアルミニウム組成が多いほど、つまり
GaAs層とA I G a A s層の価電子帯の不
連続量を大きくするほど、又AρGaAs層か厚いほど
、透過する確立が下がる。従って、透過する電流量を大
きくするにはApGaAs層をある程度薄くする必要が
あるが、量子準位を形成するためには、ある程度以上で
なければならない。
Now, in such a semiconductor device, for example, electrons are
A 4 G a As layer and barrier
However, it is a tunnel current in the A,ffGaAs layer, and generally speaking, the higher the aluminum composition, that is, the greater the amount of discontinuity in the valence band between the GaAs layer and the A I Ga As layer, the more the AρGaAs The thicker the layer, the lower the chance of penetration. Therefore, in order to increase the amount of current that passes through it, it is necessary to make the ApGaAs layer thinner to a certain extent, but in order to form a quantum level, it must be thinner than a certain level.

従って、A (l G a A sの厚さは5nm程度
である。
Therefore, the thickness of A(lGaAs) is about 5 nm.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このようにA Il G a A s層を透過する電子
はトンネル現象であり、ダイオードの電流−電圧特性に
見られるピーク電流とバレー電流のうち、ピーク電流を
決定する。一方、バレー電流はAρGaAsよりなるエ
ネルギー障壁を越える電子に依存し、従ってバレー電流
を小さくするために障壁を大きなA、&Asを用いたり
、歪InGaAsを用いて量子井戸の深さを大きくする
ことが試みられている。
Electrons passing through the A Il Ga As layer in this way are a tunnel phenomenon, and determine the peak current of the peak current and valley current seen in the current-voltage characteristics of the diode. On the other hand, the valley current depends on electrons exceeding the energy barrier made of AρGaAs, so in order to reduce the valley current, it is possible to use a large barrier of A, &As or to increase the depth of the quantum well by using strained InGaAs. is being attempted.

しかし、このようなエネルギー障壁を大きくすることに
より電子のトンネルする確率が下がり、ピーク電流が減
少する。従って、ピーク及びバレー電流の比は余り改善
が見られない。
However, by increasing such an energy barrier, the probability of electron tunneling decreases, and the peak current decreases. Therefore, the ratio of peak and valley currents does not show much improvement.

本発明の目的は、大きなピーク及びバレー電流の比が大
きなトンネルタイオード型半導体装置を提供することに
ある。
An object of the present invention is to provide a tunnel diode type semiconductor device with a large peak to valley current ratio.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のトンネルダイオード型半導体装置は、第1の半
導体層上に電子親和力が該第1の半導体層の電子親和力
と禁止帯幅の和よりも大きい第2の半導体層を設け、該
第2の半導体層の上に電子親和力が前記第1の半導体層
のそれよりも大きい第3の半導体層を設け、該第3の半
導体層の上に電子親和力が該第3の半導体層のそれより
も小さい第4の半導体層を設け、該第4の半導体層の上
に電子親和力と禁止帯幅の和か前記第3の半導体層の電
子親和力よりも小さい第5の半導体層を設けて、少なく
とも一つの量子井戸を構成していることを特徴とする。
In the tunnel diode type semiconductor device of the present invention, a second semiconductor layer having an electron affinity larger than the sum of the electron affinity and the forbidden band width of the first semiconductor layer is provided on the first semiconductor layer; A third semiconductor layer having an electron affinity larger than that of the first semiconductor layer is provided on the semiconductor layer, and a third semiconductor layer having an electron affinity smaller than that of the third semiconductor layer is provided above the third semiconductor layer. A fourth semiconductor layer is provided, and a fifth semiconductor layer is provided on the fourth semiconductor layer, the sum of the electron affinity and the forbidden band width being smaller than the electron affinity of the third semiconductor layer. It is characterized by forming a quantum well.

〔作用〕[Effect]

ヒ化インジウム(以下InAsと記す)の電子親和力は
アンチモン化ガリウム(以下GaSbと記す)親和力と
禁止帯の和よりも第2層のアンチモン化アルミニウムガ
リウム(以下AfflGaSbと記す)の間にInAs
層を設けることにより量子井戸構造を形成するが、さら
にその両端にG a S bを配した場合、GaSb中
の正孔がAρGaSbを透過し、I nAs層中の量子
準位を経て、再びAβGaSbを透過し、電流が流れる
The electron affinity of indium arsenide (hereinafter referred to as InAs) is greater than the sum of the affinity of gallium antimonide (hereinafter referred to as GaSb) and the forbidden band.
A quantum well structure is formed by providing a layer, but when GaSb is further placed on both ends of the layer, holes in GaSb pass through AρGaSb, pass through the quantum level in the InAs layer, and return to AβGaSb. passes through, and current flows.

従って、GaSb中では正孔はGaSbの禁止帯がある
ために、その依存位置はG a S bの価電子帯以下
のところである。
Therefore, in GaSb, since there is a forbidden band of GaSb, the hole dependence position is below the valence band of GaSb.

従来のトンネル型ダイオードでは量子井戸の外側では電
子が依存し、従って、障壁を乗越えて透過し、バレー電
流となる。
In conventional tunneling diodes, electrons are dependent on the outside of the quantum well and therefore pass through the barrier, resulting in a valley current.

しかし、本発明では、透過する荷電子は正孔であり、価
電子帯以下のエネルギー準位に依存するため、障壁を乗
越えることがない。従って、バレー電流は低く抑えられ
る。
However, in the present invention, the transmitted charge electrons are holes and do not cross the barrier because they depend on the energy level below the valence band. Therefore, the valley current can be kept low.

〔実施例〕〔Example〕

一 次に、本発明の実施例について図面を参照して説明する
First, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の主要部の断面図である。FIG. 1 is a sectional view of the main parts of an embodiment of the present invention.

この実施例では、n型I nAs基板6上にn型InA
s層7を設け、第1の半導体層として厚さ7nmのノン
ドープGaSb層1、第2の半導体層として厚さ3r+
n+のノンドープGaSb層2、第3の半導体層として
厚さ7nmのノンドープInAs層3.第4の半導体層
として厚さ3nmのノンドープA、!O3b層4、第5
の半導体層として厚さ50nmのノンドープGaSb層
5を設け、さらにn型InAs層8をエピタキシャル成
長させたものである。電極9,10は金ゲルマニウムニ
ッケルを蒸発し、合金化したものである。
In this example, an n-type InAs substrate 6 is coated with an n-type InAs substrate 6.
An s layer 7 is provided, a non-doped GaSb layer 1 with a thickness of 7 nm as a first semiconductor layer, and a thickness of 3r+ as a second semiconductor layer.
An n+ non-doped GaSb layer 2, a 7 nm thick non-doped InAs layer 3 as a third semiconductor layer. Non-doped A with a thickness of 3 nm as the fourth semiconductor layer! O3b layer 4, 5th
A non-doped GaSb layer 5 with a thickness of 50 nm is provided as a semiconductor layer, and an n-type InAs layer 8 is further epitaxially grown. The electrodes 9 and 10 are made of evaporated gold-germanium-nickel alloy.

第2図はこの実施例のトンネルダイオードにおいて電極
10下における深さ方向の熱平衡状態でのエネルギーバ
ンド状態図である。
FIG. 2 is an energy band state diagram in a thermal equilibrium state in the depth direction under the electrode 10 in the tunnel diode of this embodiment.

ここで、第2.第3.第4の半導体層により量子井戸構
造が形成されていて第3の半導体層中に量子準位が形成
されている。
Here, the second. Third. A quantum well structure is formed by the fourth semiconductor layer, and a quantum level is formed in the third semiconductor layer.

次に、電極9を正、電極10を負として電圧を印加する
。第3図(a)はこのときのエネルギーバンド状態図で
ある。電圧を印加することによりI nAs中の量子準
位はGaSb層5の価電子帯端よりも下に位置し、G 
a S b層1の価電子帯端よりも下に位置している。
Next, a voltage is applied with electrode 9 being positive and electrode 10 being negative. FIG. 3(a) is an energy band state diagram at this time. By applying a voltage, the quantum level in InAs is located below the valence band edge of the GaSb layer 5,
a S b Located below the valence band edge of layer 1.

従って、この状態ではトンネル電流はGaSb層5によ
りApsb層4を透過し、InSb層3の量子準位を経
てApsb層2を透過してGaSb層1へ流れる。
Therefore, in this state, the tunnel current passes through the Apsb layer 4 through the GaSb layer 5, passes through the quantum level of the InSb layer 3, passes through the Apsb layer 2, and flows to the GaSb layer 1.

さらに、印加する電圧を大きくしたときのエネルギーバ
ンド状態図を第3図(b)に示す。このとき、InAs
中の量子準位はG a S b層5の価電子帯端よりも
低いが、GaSb層1の価電子帯端よりも上に位置する
。従って、G a S b層よりAfflSb層を透過
した電子はGaSb層1により阻止されて流れない。
Furthermore, an energy band phase diagram when the applied voltage is increased is shown in FIG. 3(b). At this time, InAs
The quantum level therein is lower than the valence band edge of the GaSb layer 5 but located above the valence band edge of the GaSb layer 1. Therefore, electrons that have passed through the AfflSb layer from the GaSb layer are blocked by the GaSb layer 1 and do not flow.

一方、従来の構造、つまり第1及び第5の半導体層(G
aSb層1.5)のない構造では、InAs7より注入
された正孔はエネルギー分布をもっているため量子準位
とI nAs層6.7中の価電子帯端か一致しない場合
においても、電流が僅かに流れる。又、AfflSb層
2.4が薄いためにエネルギー障壁を越える電子も多く
なり、ピーク電流とバレー電流の比は悪くなる。
On the other hand, the conventional structure, that is, the first and fifth semiconductor layers (G
In the structure without the aSb layer 1.5), the holes injected from the InAs 7 have an energy distribution, so even if the quantum level and the valence band edge in the InAs layer 6.7 do not match, the current will be small. flows to Furthermore, since the AfflSb layer 2.4 is thin, the number of electrons that cross the energy barrier increases, resulting in a poor peak current to valley current ratio.

上記実施例では第2及び第4の半導体層にApsb層を
用いたが、Aρsb及びGaSbの混晶を用いても、ト
ンネル電流を通す程度の厚さである限り、本発明を同様
に適用できる。
In the above embodiment, Apsb layers were used as the second and fourth semiconductor layers, but the present invention can be similarly applied even if mixed crystals of Apsb and GaSb are used as long as the thickness is sufficient to conduct tunneling current. .

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように、本発明は、量子井戸層
の外の部層に価電子帯端が大きいものを用いることによ
りバレー電流を小さくすることが可能となるという利点
があり、トンネルダイオード型半導体装置のピーク電流
とバレー電流の比を増大することができ、従来のものと
比較して半導体素子の性能向上を達成することができる
という効果を有する。
As is clear from the above description, the present invention has the advantage that it is possible to reduce the valley current by using a layer with a large valence band edge as a layer outside the quantum well layer. The present invention has the effect that the ratio between the peak current and the valley current of a type semiconductor device can be increased, and the performance of the semiconductor element can be improved compared to the conventional one.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の主要部を示す断面図、第2
図は第1図に示す実施例の熱平衡状態でのエネルギーバ
ンド状態図、第3図(a)(b)は第1図に示す実施例
の電圧印加状態でのエネルギーバンド状態図である。 1・・・ノンドープGaSb層、2・・・ノンドープG
aSb層、3・・・ノンドープInAs層、4・・・ノ
ンドープAfflSb層、5・・・ノンドープGaSb
層、6− n型I nAs基板、7−・−n型InAs
層、8・・・n型I nAs層、9,10・・・電極。
FIG. 1 is a sectional view showing the main parts of an embodiment of the present invention, and FIG.
The figure is an energy band state diagram of the embodiment shown in FIG. 1 in a thermal equilibrium state, and FIGS. 3(a) and 3(b) are energy band state diagrams of the embodiment shown in FIG. 1 in a voltage applied state. 1... Non-doped GaSb layer, 2... Non-doped G
aSb layer, 3... Non-doped InAs layer, 4... Non-doped AfflSb layer, 5... Non-doped GaSb
layer, 6- n-type InAs substrate, 7-.-n-type InAs
Layer, 8... n-type InAs layer, 9, 10... electrode.

Claims (1)

【特許請求の範囲】[Claims] 第1の半導体層上に電子親和力が該第1の半導体層の電
子親和力と禁止帯幅の和よりも大きい第2の半導体層を
設け、該第2の半導体層の上に電子親和力が前記第1の
半導体層のそれよりも大きい第3の半導体層を設け、該
第3の半導体層の上に電子親和力が該第3の半導体層の
それよりも小さい第4の半導体層を設け、該第4の半導
体層の上に電子親和力と禁止帯幅の和が前記第3の半導
体層の電子親和力よりも小さい第5の半導体層を設けて
、少なくとも一つの量子井戸を構成していることを特徴
とするトンネルダイオード型半導体装置。
A second semiconductor layer having an electron affinity larger than the sum of the electron affinity of the first semiconductor layer and the forbidden band width is provided on the first semiconductor layer; a third semiconductor layer having a larger electron affinity than that of the third semiconductor layer; a fourth semiconductor layer having an electron affinity smaller than that of the third semiconductor layer; A fifth semiconductor layer is provided on the fourth semiconductor layer, and the sum of electron affinity and forbidden band width is smaller than the electron affinity of the third semiconductor layer, thereby forming at least one quantum well. A tunnel diode type semiconductor device.
JP28192688A 1988-11-07 1988-11-07 Tunnel diode type semiconductor device Pending JPH02128480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28192688A JPH02128480A (en) 1988-11-07 1988-11-07 Tunnel diode type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28192688A JPH02128480A (en) 1988-11-07 1988-11-07 Tunnel diode type semiconductor device

Publications (1)

Publication Number Publication Date
JPH02128480A true JPH02128480A (en) 1990-05-16

Family

ID=17645869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28192688A Pending JPH02128480A (en) 1988-11-07 1988-11-07 Tunnel diode type semiconductor device

Country Status (1)

Country Link
JP (1) JPH02128480A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0634055A1 (en) * 1992-03-30 1995-01-18 YATER, Joseph C. Reversible thermoelectric converter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0634055A1 (en) * 1992-03-30 1995-01-18 YATER, Joseph C. Reversible thermoelectric converter
EP0634055A4 (en) * 1992-03-30 1995-03-22 Joseph C Yater Reversible thermoelectric converter.
US5470395A (en) * 1992-03-30 1995-11-28 Yater Joseph C Reversible thermoelectric converter
US5889287A (en) * 1992-03-30 1999-03-30 Yater; Joseph C. Reversible thermoelectric converter

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