JPH0212698A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To ensure the switching of a redundancy circuit and to improve reliability by providing a redundancy fuse to be blown externally as required and a means holding a 2nd node potential connecting to a 1st node via a 1st switch means conductive when a set signal is in a 2nd potential. CONSTITUTION:The 1st node N1 connected to a constant power line having the 1st potential via a prescribed resistor T1 and a signal generating means 20 generating a set signal whose potential changes from the 1st potential to the 2nd potential periodically are connected. Then a redundant fuse F to be blown externally as required, the 1st switch means TNA conductive when a set signal is in the 2nd potential, the 2nd node NIN connecting to the 1st node N1 via the 1st switch means and the 2nd switch means TNB conductive when the set signal is in the 1st potential are provided. The potential of the 1st node N1 corresponding to blown/unblown of the fuse F is given to the 2nd node NIN and the potential is held in the holding means. thus, the reliability of the redundant program is improved.

Description

[Detailed Description of the Invention] (Summary) The purpose of this invention is to improve reliability by ensuring the switching operation of a redundant circuit while improving power consumption in a semiconductor memory device. A semiconductor memory device capable of selectively cutting off a plurality of redundant fuses to perform an IA between a regular memory cell array including a defective bit cell and a redundant memory cell array, wherein one potential is regulated through a predetermined resistor. A first node connected to a power supply line, a signal generating means for generating a set signal that periodically changes from a first potential to a second potential, and a connection between the signal generating means and the first node. In addition, a redundant fuse that can be disconnected from the outside as necessary, a first switch means that conducts when the set signal is at a second potential, and a first switch connected to the first node via the first switch means. a second node,
a second switch means that becomes conductive when the set signal is at one potential; and a holding means that receives a power supply voltage through the second switch means and holds the potential of the second node. It is composed of

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a redundant circuit.

Generally, as the memory capacity of a semiconductor memory device increases and the design rules become stricter, the rate of occurrence of defective cells in the manufactured semiconductor memory device increases, which deteriorates the yield.

Therefore, in addition to the original memory cell array (regular memory cell array), a redundant memory cell array is built into the chip, and a part of the regular memory cell array containing defective cells is replaced with the redundant memory cell array to avoid deterioration in yield. will be held.

(Prior Art) FIG. 3 is a schematic diagram of a chip layout of a semiconductor memory device having a redundant circuit. In Figure 3, 1 is a chip;
2 to 5 are regular memory cell arrays, 2a to 5a are redundant memory cell arrays, 6 is a peripheral circuit, and 7 is a redundant switching circuit. The redundant switching circuit 7 selectively blows out a plurality of redundant fuses to program the regular memory cell array 2.
5 is replaced with the redundant memory cell arrays 2a to 5a, and the main part of the first conventional example is shown in FIG. In FIG. 4, F is a redundant fuse that can be blown by e.g. laser irradiation from outside the chip;
T1 is a normally-on transistor that has a relatively high channel-on resistance ROM and functions as a predetermined resistor, and when F is not fused, a current I flows from the voltage V on to R80 via F. As a result, a potential of IFXROM is generated at the node N1 between F and T, with VSS as a reference.

On the other hand, when F is fused, node N is at V. is connected to and kept at a potential of approximately VSS. That is, the potential of N1 indicates a binary logic corresponding to when F is blown/unblown, and the replacement destination of the redundant memory cell is programmed according to this logic. By the way, in this first conventional example, when F is not fused, I
Since the configuration was such that F was always flowing, there was a problem in terms of power consumption.

FIG. 5 is a diagram showing the main part of a second conventional example with improved power consumption. Note that the same components as in the first conventional example are given the same reference numerals. In FIG. 5, 10 is a latch circuit that holds the potential of the node N1, and the latch circuit 10 includes a first inverter INV, which has a P-channel transistor T□ and an N-channel transistor T□, a P-channel transistor TP2, and N-channel transistor T. 2
A second inverter I N V z having a potential of N. These are expressed as U, and are retained. Therefore, after the latch circuit 10 enters the latch operation, it is not necessary to flow (2) and (2) to F, and power consumption can be improved.

[Problem to be solved by the invention]

However, in such a second conventional example, with the intention of improving power consumption, the configuration is such that IP is not passed to F after the launch circuit 10 has latched. Later, when disturb (noise, etc.) is applied from the outside, the launch circuit 10 may easily reverse its launch state. There was an open problem in terms of reliability, such as no longer corresponding to whether F was blown or not fused, and redundant memory cells could be programmed incorrectly.

The present invention was made in view of these problems, and
The purpose is to improve reliability by ensuring the switching operation of redundant circuits while improving power consumption.

[Means for Solving the Problems] In order to achieve the above object, the present invention selectively disconnects a plurality of redundant fuses according to the position of a defective pit cell, and disconnects the regular memory cell array and the redundant memory cell array including the defective bit cell. A semiconductor memory device capable of replacing a first node connected to a constant power supply line at one potential through a predetermined resistor, and periodically changing from one potential to a second potential. a redundant fuse that connects the signal generating means and the first node and can be disconnected from the outside as necessary; a second node connected to the first node via the first switch means; and a second switch that conducts when the set signal is at one potential. and holding means that receives supply of power supply voltage through the second switch means and holds the potential of the second node.

[For production]

In the present invention, the potential at the first node corresponding to whether or not the redundant fuse is blown is transmitted to the second mate, and the potential at the second node is held by the holding means. Further, the above-mentioned holding operation is repeated at the cycle of the set signal which changes intermittently, and even if the held contents are reversed to the incorrect side by the disc scoop, the set signal of the next cycle will restore the held contents to the correct side. Therefore, the reliability of the redundant program can be improved. Note that since current is intermittently passed through the redundant fuse at the cycle of the cent signal, power consumption is improved compared to a redundant fuse that passes a constant current (for example, the first conventional example).

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1.2 is a diagram showing an embodiment of the present invention.

In this embodiment, the same parts as in the first and second conventional examples described above are given the same reference numerals.

In FIG. 1, 20 is a signal generation means, and the signal generation means 20 generates set signals VP, VF which periodically change from one potential (for example, Vss) to a second potential (for example, Veo). ' (where y and l are signals with opposite phases of Vde) (see Fig. 2). The set signal V, is supplied to the first node N, via the redundant fuse F, and is also applied to the gate of the N-channel transistor (first switch means) TNA. N-channel transistor T.

is interposed between the first node N1 and the input side node N1N of the latch circuit 10 as the 20th node, and transmits the potential of the first node N to the input side node NIN when conductive. T'Nm is an N-channel transistor serving as a second switch means, and ■ and ' are added to the gate of To. Ta1B is the power supply voltage ■ when conductive. , is supplied to the latch circuit 10 as a holding means.

Next, the circuit operation will be explained with reference to the waveform timings of V, , and VP' in FIG.

During the period (a) when the voltage is at the potential of VDD, this V is applied to the F and T1 channels. Current sourced from I■
, flows into N1 and causes the potential of IFXRON to occur at N1. During this period (a), since TNA is in a conductive (ON) state, the potential of N1 is transmitted to NIN. Next, ■
During the period (b) when , is at the potential of ■, the TNA becomes non-conductive (OFF), and during this period (b),
P' is V. Since it is at the potential of TN! + is conductive (O
N), Vo is supplied to the latch circuit 10, and the latch circuit 10 latches to hold the potential of I'J+x.

Then, the above-mentioned operation is repeated according to the cycles of ■ and Vp'.

That is, the latch circuit 10 latched in period (b)
Even if it reverses unexpectedly due to disturb, etc., if the potential is transferred to Nl -'NIN in the next cycle,
The correct latched state corresponding to state F (non-fused) is restored, thereby improving the reliability of the redundant program. In addition, since Iy is flown to F for only the half cycle period (period (A)) of ■2, power consumption can be improved compared to the first conventional example in which I was continuously flown. .

On the other hand, if F is fused by a laser or the like from the outside, I
F doesn't flow. In other words, the potential of N is approximately VSS, and this potential is applied to N via TNA during period (A).
1) transmitted to l. Then, in period (b), T
■■ is supplied to the latch circuit 10 via NI, and the latch circuit 10 latches the potential of No (about V8.). Then, the above-mentioned operation is repeated according to the cycles of ■ and v2.

That is, the latch circuit lO latched in period (b) is
Even if it is involuntarily reversed due to disturb or the like, it will return to the correct latched state corresponding to the state of F (blown out) in the next cycle, thereby improving the reliability of the redundant program.

In this way, in this embodiment, the potential corresponding to the state of ■The potential is transmitted from N1 to Nl, ■The potential of NIN is latched by the latch circuit 1o, and ■~■ are repeated according to the period of the set signal.For this reason, if the latch is caused by disturb etc. Even if the state of the circuit IO is unexpectedly reversed, it can be restored to the correct state in the next cycle (1) to (2), and the reliability of the redundant program can be improved.

In addition, since l, flows only during the half cycle period of the set signal in F when not blown, power consumption can be improved compared to the case where 2, continuously flows.

Furthermore, in the present embodiment, V is followed by F. This has the effect of preventing the glow-back phenomenon. Here, the glow-back phenomenon refers to the phenomenon in which a fuse of polyethylene, etc., which has been disconnected for a few degrees, is reconnected. For example, if a conductive substance such as water enters the fused area, if voltage is constantly applied to the redundant fuse, there is a high possibility that the redundant fuse will appear to be connected again.In contrast, in this example, Since an intermittent voltage is applied, the above-mentioned degree can be reduced and the occurrence of the glowback phenomenon can be suppressed.

In this example, one of the changing potentials of ■2, V, and l is set to VDD, but this is not limiting.In short, a voltage exceeding the threshold value of THA is applied to VsS. It is sufficient if the voltage is higher than the specified voltage.

Further, although in this embodiment, ■ and V% are in opposite phases, they can also be made in the same phase by using a P-channel transistor for TNI.

(Effects of the Invention) According to the present invention, the switching operation of the redundant circuit can be ensured while improving the power consumption, and reliability can be improved.

[Brief explanation of the drawing]

FIG. 1.2 is a diagram showing an embodiment of the present invention, FIG. 1 is a configuration diagram of its essential parts, and FIG. 2 is a waveform timing chart of Vp and Vp'. 3 to 5 are diagrams showing conventional examples. FIG. 3 is an overview of the chip layout, FIG. 4 is a configuration diagram of the main part of the first conventional example, and FIG. 5 is a diagram of the second conventional example. FIG. 2 to 5...Common memory cell array, 2a to 5a
...Redundant memory cell array, 10...
Latch circuit, 20... Signal generation means, F... Redundant fuse, N,... First node, No... Input side node (second node), T,
IA... N-channel transistor (first switch means), THll... N-channel transistor (second switch means), T,... Transistor (predetermined resistor) ). Patent applicant Fujitsu Ltd. Fujitsu VLC T1: Toji λ9 Faculty of one contribution example 11 reaction m Fig. *; Koda Sugi 7 Fuimikiku γ15 Self Diagram 4-, Nfuruiavut #!

Claims (1)

[Scope of Claims] A semiconductor memory device capable of selectively cutting a plurality of redundant fuses according to the position of a defective bit cell and replacing a regular memory cell array containing a defective bit cell with a redundant memory cell array, comprising: a first node connected to a constant power supply line at one potential via a predetermined resistor; a signal generation means for generating a set signal that periodically changes from the first potential to the second potential; and signal generation. a redundant fuse that connects the means and the first node and can be disconnected from the outside as necessary; a first switch means that becomes conductive when the set signal is at a second potential; a second node connected to the first node via a switch means; a second switch means that conducts when the set signal is at one potential; receive supply,
A semiconductor memory device comprising: holding means for holding the potential of the second node.