JPH02124608A - Frequency conversion circuit - Google Patents

Frequency conversion circuit

Info

Publication number
JPH02124608A
JPH02124608A JP27886388A JP27886388A JPH02124608A JP H02124608 A JPH02124608 A JP H02124608A JP 27886388 A JP27886388 A JP 27886388A JP 27886388 A JP27886388 A JP 27886388A JP H02124608 A JPH02124608 A JP H02124608A
Authority
JP
Japan
Prior art keywords
frequency conversion
modulation circuit
double
phase inverter
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27886388A
Other languages
Japanese (ja)
Inventor
Kiyoshi Iwasaki
岩崎 潔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27886388A priority Critical patent/JPH02124608A/en
Publication of JPH02124608A publication Critical patent/JPH02124608A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Amplitude Modulation (AREA)

Abstract

PURPOSE:To eliminate carrier leakage caused due to the variance in the characteristic of components of a modulation circuit by employing a double balanced modulation circuit, a phase inverter and an adder so as to apply arithmetic operation. CONSTITUTION:A frequency conversion carrier 2 is used to control 1st and 2nd double balance modulation circuits 3, 4 thereby converting the frequency. That is, when an input signal 1 is inputted, it is subject to frequency conversion at the 1st double balance modulation circuit 3 by using the conversion carrier 2. On the other hand, the input signal passes through a 1st phase inverter 5 simultaneously, then the signal is subject to frequency conversion by the 2nd double balance modulation circuit 4 and after the phase restoration by a phase inverter 6, the output after the phase restoration and the output of the 1st double balance modulation circuit 3 are added by an adder 7 to produce an output signal 8. Thus, carrier leakage is prevented for the frequency conversion.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は周波数変換回路に関し、特に二重平衡変調回路
を用いた周波数変換回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency conversion circuit, and more particularly to a frequency conversion circuit using a double-balanced modulation circuit.

〔従来の技術〕[Conventional technology]

従来、かかる二重平衡変調回路を用いた周波数変換回路
は、入力信号を周波数変換キャリアを用いて変調するこ
とにより実現している。
Conventionally, a frequency conversion circuit using such a double-balanced modulation circuit has been realized by modulating an input signal using a frequency conversion carrier.

第2図はかかる従来の一例を示す周波数変換回路図であ
る。
FIG. 2 is a frequency conversion circuit diagram showing an example of such a conventional system.

第2図に示す↓うに、この周波数変換回路は入力信号↓
と周波数変換用キャリア2が入力されると、出力信号8
は入力信号1とキャリア2との乗算された結果となる。
As shown in Figure 2, this frequency conversion circuit converts the input signal ↓
and frequency conversion carrier 2 are input, output signal 8
is the result of multiplying input signal 1 and carrier 2.

例えば、入力信号1の位相をSinα、キャリア2の位
相をSinβとすれば、出力信号6の位相はSinαS
inβとなる。これを展開すると、1/2(Cos(α
−β)−Cos(α+β))となり、したがって入力信
号1の周波数αは出力信号8において、1αβ1とα+
βとの位相をもった周波数に変換される。尚、入力信号
1はバイアス1oとトランジスタQ5.Q6および抵抗
R,,R4により差動段が構成され、周波数変換用キャ
リア2はバイアス9とトランジスタQ+〜Q4および抵
抗R1R2により差動段が構成され、またトランジスタ
素子および抵抗R5はバイアス11により定電流源を構
成し、トランジスタQ8および抵抗R6は出力段を構成
している。
For example, if the phase of input signal 1 is Sinα and the phase of carrier 2 is Sinβ, then the phase of output signal 6 is SinαS
becomes inβ. Expanding this, 1/2(Cos(α
−β)−Cos(α+β)), therefore, the frequency α of input signal 1 becomes 1αβ1 and α+
It is converted to a frequency that has a phase with β. Note that the input signal 1 is connected to the bias 1o and the transistor Q5. Q6 and resistors R, , R4 constitute a differential stage, frequency conversion carrier 2 constitutes a differential stage with bias 9, transistors Q+ to Q4 and resistors R1R2, and transistor element and resistor R5 are regulated by bias 11. The transistor Q8 and the resistor R6 constitute a current source, and the transistor Q8 and the resistor R6 constitute an output stage.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の周波数変換回路は回路構成が容易で且つ
コスト的に利点があるが、回路を構成するトランジスタ
素子の特性のばらつきに対して周波数変換特性が変化し
やすいという欠点がある。
The above-mentioned conventional frequency conversion circuit has an advantage in that the circuit configuration is easy and in terms of cost, but it has the disadvantage that the frequency conversion characteristics are easily changed due to variations in the characteristics of the transistor elements that constitute the circuit.

例えば、第2図において、トランジスタQ5とQ6のそ
れぞれの■BE電圧にばらつきがあると、変換用キャリ
ア2が出力信号8にリークしてしまう。特に、民生用V
TRにおけるカラー信号の周波数変換のように、入力信
号と変換用キャリアとの周波数が非常に近い場合、この
キャリアリークが間圧にされることが多い。
For example, in FIG. 2, if there are variations in the BE voltages of the transistors Q5 and Q6, the conversion carrier 2 will leak to the output signal 8. In particular, consumer V
When the frequencies of the input signal and the carrier for conversion are very close, as in the case of frequency conversion of a color signal in a TR, this carrier leak is often made into an intermediate pressure.

本発明の目的は、かかるキャリアのリークを防止して周
波数を変換することのできる周波数変換回路を提供する
ことにある。
An object of the present invention is to provide a frequency conversion circuit that can convert frequencies while preventing such carrier leakage.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の周波数変換回路は、二重平衡変調回路を用いる
周波数変換回路において、入力信号端子にそれぞれ接続
された第一の二重平衡変調回路および第一の位相反転器
と、前記第一の位相反転器に接続された第二の二重平衡
変調回路と、前記第二の二重平衡変調回路に接続された
第二の位相反転器と、出力信号端子に接続され前記第一
の二重平衡変調回路の出力と前記第二の位相反転器の出
力とを加算する加算器とを有し、周波数変換用キャリア
を用いて前記第一および第二の二重平衡変調回路を制御
して周波数の変換を行うように構成される。
The frequency conversion circuit of the present invention is a frequency conversion circuit using a double-balanced modulation circuit, and includes a first double-balanced modulation circuit and a first phase inverter each connected to an input signal terminal; a second double-balanced modulation circuit connected to the inverter; a second phase inverter connected to the second double-balanced modulation circuit; and a second phase inverter connected to the output signal terminal and connected to the first double-balanced modulation circuit. an adder that adds the output of the modulation circuit and the output of the second phase inverter, and controls the first and second double-balanced modulation circuits using a frequency conversion carrier to increase the frequency. configured to perform the conversion.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示す周波数変換回路のブロ
ック図である。
FIG. 1 is a block diagram of a frequency conversion circuit showing one embodiment of the present invention.

第1図に示すように、本実施例は入力信号端子1にそれ
ぞれ第一の二重平衡変調回路3とインバータで構成され
る位相反転器5とが接続され、この位相反転器5の出力
側には第二の二重平衡変調回路4が接続される。また、
二重平衡変調回路4の出力側には、前述した第一の位相
反転器5と同様の第二の位相反転器6が接続され、更に
この第二の位相反転器6の出力と第一の二重平衡変調回
路3の出力とを加算する通常の加算器7が設けられ、出
力信号端子8にその演算結果を出力する。
As shown in FIG. 1, in this embodiment, a first double-balanced modulation circuit 3 and a phase inverter 5 composed of an inverter are connected to the input signal terminal 1, respectively, and the output side of the phase inverter 5 is connected to the input signal terminal 1. A second double-balanced modulation circuit 4 is connected to. Also,
A second phase inverter 6 similar to the first phase inverter 5 described above is connected to the output side of the double balanced modulation circuit 4, and furthermore, the output of the second phase inverter 6 and the first phase inverter 6 are connected to each other. A normal adder 7 is provided to add the output of the double-balanced modulation circuit 3, and outputs the calculation result to an output signal terminal 8.

尚、周波数変換用キャリア端子2からは変換用キャリア
が入力され、第一および第二の二重平衡変調回路3およ
び4を制御している。
Note that a carrier for conversion is inputted from the carrier terminal 2 for frequency conversion, and controls the first and second double balanced modulation circuits 3 and 4.

かかる周波数変換回路において、入力信号1が入力され
ると、変換用キャリア2により第一の二重平衡変調回路
3で周波数変換される。一方、同時に入力信号1は第一
の位相反転器5を通した後、第二の二重平衡変調回路4
で周波数変換され、位相反転器6による位相復元後に、
この位相復元後の出力と第一の二重平衡変調回路3の出
力とを加算器7で加算処理し出力信号8となる。
In such a frequency conversion circuit, when an input signal 1 is input, it is frequency converted by a first double-balanced modulation circuit 3 using a conversion carrier 2. Meanwhile, at the same time, the input signal 1 passes through the first phase inverter 5 and then passes through the second double-balanced modulation circuit 4.
After frequency conversion by the phase inverter 6 and phase restoration by the phase inverter 6,
The output after the phase restoration and the output of the first double-balanced modulation circuit 3 are added together by an adder 7 to obtain an output signal 8.

例えば、入力信号1をSinψ、変換キャリア2をSi
nγとすれば変調回路3の出力の位相はSinψSin
γ、変調回路4の出力の位相は一8inψSinγとな
る。一方、変換キャリア2のリークは入力信号に対する
リークレベルの係数をK(IKI<1)とすると、KS
in7となる。従って、変調回路3と変調回路4のに値
が同じであるとすれば、加算器7の出力における信号位
相は、 (SinψS i n7+KS i n7)+(−(−
3inψS i nγ+KS i nγ) )=2Si
nψ5in7 となり、リーク分は相殺されて除去される。
For example, input signal 1 is Sinψ, conversion carrier 2 is Si
If nγ, the phase of the output of the modulation circuit 3 is SinψSin
γ, and the phase of the output of the modulation circuit 4 is -8 inψSinγ. On the other hand, if the leakage level coefficient for the input signal is K (IKI<1), then the leakage of conversion carrier 2 is
It becomes in7. Therefore, if the modulation circuits 3 and 4 have the same value, the signal phase at the output of the adder 7 is (SinψS in7+KS in7)+(-(-
3inψSi nγ+KS i nγ) )=2Si
nψ5in7, and the leakage amount is canceled out and removed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の周波数変換回路は、二重
平衡変調回路と位相反転器および加算器とを用いて演算
することにより、変調回路を構成する素子の特性のばら
つきによって生ずるキャリアリークを除去することがで
きるという効果がある。
As explained above, the frequency conversion circuit of the present invention uses a double-balanced modulation circuit, a phase inverter, and an adder to perform calculations to eliminate carrier leakage caused by variations in characteristics of elements constituting the modulation circuit. It has the effect of being able to be removed.

6一61

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す周波数変換回路のブロ
ック図、第2図は従来の一例を示す二重平衡変調回路図
である。 1・・・入力信号、2・・・周波数変換用キャリア、3
.4・・・二重平衡変調回路、5,6・・・位相反転器
、7・・・加算器、8・・・出力信号。
FIG. 1 is a block diagram of a frequency conversion circuit showing an embodiment of the present invention, and FIG. 2 is a diagram of a double balanced modulation circuit showing an example of the conventional art. 1... Input signal, 2... Frequency conversion carrier, 3
.. 4... Double balanced modulation circuit, 5, 6... Phase inverter, 7... Adder, 8... Output signal.

Claims (1)

【特許請求の範囲】[Claims]  二重平衡変調回路を用いる周波数変換回路において、
入力信号端子にそれぞれ接続された第一の二重平衡変調
回路および第一の位相反転器と、前記第一の位相反転器
に接続された第二の二重平衡変調回路と、前記第二の二
重平衡変調回路に接続された第二の位相反転器と、出力
信号端子に接続され前記第一の二重平衡変調回路の出力
と前記第二の位相反転器の出力とを加算する加算器とを
有し、周波数変換用キャリアを用いて前記第一および第
二の二重平衡変調回路を制御して周波数の変換を行うこ
とを特徴とする周波数変換回路。
In a frequency conversion circuit using a double-balanced modulation circuit,
a first double-balanced modulation circuit and a first phase inverter connected to input signal terminals, a second double-balanced modulation circuit connected to the first phase inverter, and a second double-balanced modulation circuit connected to the first phase inverter; a second phase inverter connected to the double-balanced modulation circuit; and an adder connected to the output signal terminal for adding the output of the first double-balanced modulation circuit and the output of the second phase inverter. 1. A frequency conversion circuit comprising: a carrier for frequency conversion to control the first and second double-balanced modulation circuits to perform frequency conversion.
JP27886388A 1988-11-02 1988-11-02 Frequency conversion circuit Pending JPH02124608A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27886388A JPH02124608A (en) 1988-11-02 1988-11-02 Frequency conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27886388A JPH02124608A (en) 1988-11-02 1988-11-02 Frequency conversion circuit

Publications (1)

Publication Number Publication Date
JPH02124608A true JPH02124608A (en) 1990-05-11

Family

ID=17603180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27886388A Pending JPH02124608A (en) 1988-11-02 1988-11-02 Frequency conversion circuit

Country Status (1)

Country Link
JP (1) JPH02124608A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994016502A1 (en) * 1993-01-13 1994-07-21 Bayruns Robert J Method and apparatus for reducing local oscillator leakage in integrated circuit receivers
US5584066A (en) * 1993-10-08 1996-12-10 Sony Corporation Correcting circuit for mixing circuit receiver using same and frequency spectrum inverting circuit using same
WO2007123072A1 (en) * 2006-04-17 2007-11-01 Advantest Corporation Modulator
JP2007288794A (en) * 2007-05-11 2007-11-01 Advantest Corp Modulator

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994016502A1 (en) * 1993-01-13 1994-07-21 Bayruns Robert J Method and apparatus for reducing local oscillator leakage in integrated circuit receivers
US5428837A (en) * 1993-01-13 1995-06-27 Anadigics, Inc. Method and apparatus for reducing local oscillator leakage in integrated circuit receivers
US5584066A (en) * 1993-10-08 1996-12-10 Sony Corporation Correcting circuit for mixing circuit receiver using same and frequency spectrum inverting circuit using same
WO2007123072A1 (en) * 2006-04-17 2007-11-01 Advantest Corporation Modulator
US8183951B2 (en) 2006-04-17 2012-05-22 Advantest Corporation Modulator
JP2007288794A (en) * 2007-05-11 2007-11-01 Advantest Corp Modulator

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