JPH02122718A - Semiconductor circuit device - Google Patents

Abstract

PURPOSE:To eliminate unstability in latch information and waste current consumption at the time of applying a power source by setting the threshold voltage of a first P-channel MOS transistor differently from that of a second P-channel MOS transistor. CONSTITUTION:Relation between the threshold voltage Vthp1 of the first P- channel MOS transistor 3 and the threshold voltage Vthp2 of the second P- channel MOS transistor 5 is set as ¦Vthp1¦>¦Vthp2¦. Thereby, when a high potential point 1 is increased and exceeds the voltage ¦Vthp2¦, a TR 5 is energized, and the potential of a node 8 rises to a level equivalent to the high potential point 1. At this time, a TR 3 is de-energized, and a node 7 remains at an L level. Furthermore, when the high potential point 1 is increased and exceeds the voltage ¦Vthp1¦, the node 8 increases following that increment, however, the TR 3 remains at a de-energized state since gate potential rises. Therefore, by changing the threshold voltages of the TRs 3 and 5 comprising a latch circuit, it is possible to eliminate the unstability in the latch information and the waste current consumption at the time of applying the power source.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a latch circuit that is often used to store information on a semiconductor circuit device.

[Conventional technology]

As a conventional latch circuit, there is a circuit shown in FIG. 1, which is a circuit diagram of a semiconductor circuit device in which all input and output terminals of two CMOS inverter circuits are connected in a complementary manner. In FIG. 1, (1) is a high potential point, (21 is a low potential point, (3) is a first P-channel type MOS transistor, +41i is a first N-channel type MOS transistor, +51i is a second P-channel type MOS transistor) M.O.
S transistor, [61: second N-channel type MO8)
The transistors (3) and (4) are connected as shown in the figure, and the first CMOS
This constitutes an inverter circuit, and transistors (5) and (6) constitute a second inverter circuit. (7)
C is the output end of the first inverter, and is also the input end of the second inverter. (8) D is the output terminal of the second inverter, and is also the input terminal of the first inverter. (9) This is an N-channel type MOS (MOS) transistor that serves as a transfer gate for transmitting all information to the Nilatch circuit. Transfer gate of DO1i transistor (9)? ll1(l gate input signal, (ll) [latch input signal.

Next, the operation will be explained. First, during normal operation, the output (8) of the second inverter of the latch circuit is connected to a high potential (
To latch the latch input signal (hereinafter referred to as "l H+"), set the latch input signal (1111 low potential (hereinafter referred to as "L") and transfer gate signal (10) to "°H'1", then the transistor (9) Conduction L node (7) is II L l
It becomes l. Then, the output of the second inverter t81ic
It becomes "H". As a result, the output f7 of the first inverter
1 i becomes “L”.

After this, even though the transistor (9) is non-conducting, IILII and IIHI are applied to the nodes (7) and (8), respectively.
+ is maintained completely stable, that is, the output f8Hc"'H" is latched. Output of the second inverter (8
) will be latched in the same way.Next, we will explain the case where, for example, the high potential point (11) rises from QV to 5V when the power is turned on.

[Problem to be solved by the invention]

In the conventional latch circuit, the first P-channel transistor (3) and the second P-channel transistor (6) have the same threshold voltage, and the first N-channel transistor (41) and the second P-channel transistor (41) have the same threshold voltage. N-channel transistor (6
) are also the same, so when the power is turned on, the transistors +31, +4+, +51, t
el becomes conductive at the same time, the power supply current increases, and the clutch information becomes unstable, making it necessary to initialize the semiconductor circuit device before operating it.

As a countermeasure for this, the threshold 1 direct voltage of the first inverter circuit and the second inverter circuit? What is the transistor size of P-channel type and N-channel type transistors, that is, channel length and channel width? There is a method of making the data different by converting it to a different value, but even with this method, unnecessary power current flows until the latch information is stabilized, and the content of the latch information is easily affected by process fluctuations. There was a point.

The present invention has been made in order to solve the above-mentioned problems, and to obtain a latch circuit that can arbitrarily set initial latch information without causing unnecessary power supply current to flow when the power is turned on. With the goal.

[Means and effects for solving the problem] In the latch circuit according to the present invention, the threshold voltages of the first P-channel type MO5 transistor and the 20th P-channel type MO5 transistor are made different, so that the threshold voltage of the transistor when the power is turned on is The objective is to be achieved by setting and establishing the conduction order.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the first and second two common to the present invention and the prior art.
This is a circuit diagram of a semiconductor circuit device in which the input and output terminals of two inverter circuits are connected complementary to each other, and since the reference numerals in the figure are the same as those of the conventional device, a description thereof will be omitted.

In the present invention, the first P-channel MO5) transistor (31 and the second P-channel MOS) transistor (5) have different threshold voltages, and both transistors (31, (51)
The order of conduction is different.

Next, the operation will be explained. In FIG. 1, a case will be described where IIHIIk is latched to the output (8) of the latch circuit as initial latch information when, for example, the high potential point 11) rises from Ov to 5■ when the power is turned on. In this case, the relationship between the threshold voltage (vthp+) of the first P-channel transistor (3) and the threshold voltage (Vthp2) of the second P-channel transistor (5) is expressed as the following equation il1. You can set it to .

1Vthpl I (V) > 1Vthp21 (v)
・il+ By setting il+ in this way, when the high potential point il+ increases and exceeds IVthp21 (V:), the second P-channel transistor (6) becomes conductive, and the potential of the node (8) becomes the high potential point fi+. raise it to a level equal to At this time, the first P-channel transistor (3) is non-conductive, and the node (7) is IIL"
It remains as it is. Furthermore, the high potential point +11 increases and IVt
hpl I CM) When f exceeds / -Ft81 follows and increases, but the first P-channel transistor +31 rr remains non-conductive because its gate potential has increased. Further, as the first N-channel transistor (4) becomes conductive due to the rise in the node (8), the node (7) is forcibly turned to °L''.
Channel type transistor! 61 +'! The non-4 A remains and the node (81U maintains "H". In this way, the "H°" latch is made stable when the power is turned on, and furthermore, the transistor i3), (41 or warp transistor +51, +61 are not conductive at the same time, and no wasteful power supply current is generated.A waveform diagram showing this operation is shown in Figure 2.
11, the output waveform of the latch circuit output node (8) is shown in the mouth, and the power supply current waveform is shown in Q41. In addition, the latch circuit outputs (8) as initial latch information when the power is turned on.
When latching L"i, the threshold voltage (Vthpl) of the first P-channel transistor (3) and the second P-channel transistor (3)
Threshold voltage (Vt) of channel type transistor (5)
hp 2 ) and the total order (just set it as in equation 21) IVthpH (:V') < 1Vthp21 (V)
=121 By setting in this way, it becomes possible to latch "L" in the same way as when latching "H". '-Also, during normal operation, this is done in exactly the same way as the conventional one.

〔Effect of the invention〕

As described above, according to the present invention, P
By increasing the direct voltage of the transistor (channel type MOS) to kW, instability of the latch information and wasteful current consumption at power-on are eliminated, and even the latch information at power-on can be arbitrarily set. big.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a latch circuit common to the conventional latch circuit and the present invention, and FIG. 2 is a waveform diagram showing the operation of the latch circuit of the present invention. In the figure, (1) is a high potential point, (2( is a low potential point, (
3). (5) P channel type MOS) transistor, +4+,
tel is an N-channel MOS transistor, +9)i
An N-channel MOS transistor is shown.

Claims (1)

[Claims] A CMOS circuit having a P-channel MOS transistor and an N-channel MOS transistor on the same substrate, the first P-channel MOS transistor and the first N-channel MOS transistor having their respective gate and drain ends connected in common. an inverter circuit, a second P-channel type MOS transistor, and a second N-channel type MO
It consists of a second inverter circuit in which the gate and drain ends of the S transistors are respectively connected in common, the gate input of the first inverter circuit is used as the drain output of the second inverter circuit, and the drain output of the first inverter circuit is used as the drain output of the second inverter circuit. 2. A semiconductor circuit device as a gate input of an inverter circuit, characterized in that the first P-channel MOS transistor and the second P-channel MOS transistor have different threshold voltages. .