JPH02119159A - Semiconductor wafer and semiconductor device using same and process evaluating method therefor - Google Patents

Abstract

PURPOSE:To optimize the manufacturing process of an MOS device and shorten the manufacturing period by providing a single testing MOS.FET in the marginal region of the IC of a semiconductor wafer and connecting the gate and the diffusion layer thereof with a wiring formed of a different layer. CONSTITUTION:An MOSIC with a three-layer wiring structure is formed in the IC region of a semiconductor wafer, and a plurality of test element group TEG consisting of a single MOS.FET are formed in the marginal region thereof. Then, a gate 6 and a diffusion layer 3 of a clamp circuit are connected by a wiring formed of a different wiring layer. When this TEG is in a floating state wherein the gate 6 and the diffusion layer 3 are not connected to each other, the single MOS.FET forming the TEG is susceptible to damage. Therefore, by evaluating the damage individually, the damage to the MOS.FET formed in the IC region due to plasma can be classified in accordance with respective deposition processes for insulating films. Thus, the manufacturing process of the MOS device can be optimized and the manufacturing period can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to a process evaluation technique for MOS devices.

[Conventional technology]

In the manufacturing process of semiconductor devices, TEG (Test Element) is applied to the remaining area of the circuit area of the semiconductor wafer.
This TEG is used to evaluate various process characteristics and device characteristics.

In addition, in the manufacturing process of semiconductor devices, plasma etching processes are used, such as the process of depositing an insulating film on a wafer using plasma CVD, and the reactive ion etching (RIE) process that uses ions generated in plasma. Since various processes using plasma are involved, it is essential to take measures to prevent element damage caused by plasma. Regarding the problem of element damage caused by plasma, see, for example, "Electronic Materials/19
It is explained in the November 1986 special issue, pages 128-131.

By the way, in the manufacturing process of a MOS device, charges are accumulated on the wiring in the above-mentioned process using plasma, and when this is discharged, it can damage the MOS-FET and cause the threshold voltage (VtH) to fluctuate. It is known that it can destroy the gate insulating film.

In particular, for example, the single MO3 FET that constitutes the TEG
M whose gate is in a floating state, as in
OS-FETs are easily damaged.

Therefore, the TEG of the wafer on which the MOS integrated circuit is formed is
is provided with a so-called clamp circuit for alleviating damage to the single MOS/FET caused by the above-mentioned charge discharge. This clamp circuit consists of the above-mentioned single MOS/FE
This is a circuit in which a T and a diffusion layer (pn junction) formed in the vicinity thereof are connected by wiring.

[Problem to be solved by the invention]

Incidentally, in recent years, semiconductor integrated circuits have become more and more multilayered in wiring, and accordingly, interlayer insulating films that insulate upper and lower wiring layers are also multilayered. Therefore, in order to optimize the manufacturing process of a MOS device, it is necessary to evaluate the degree of damage to the MOS-FET caused by plasma in the interlayer insulating film deposition process for each interlayer insulating film deposition process.

However, conventionally, MOS-F caused by plasma
The degree of ET damage is classified for each interlayer insulating film deposition process.
There was no TEG that could be clarified.

For example, a TEG equipped with the clamp circuit can alleviate damage to a single MOS-FET caused by plasma, but the degree of damage to the MOS-FET can be determined at each interlayer insulating film deposition step. cannot be evaluated.

The present invention has been made in view of the above-mentioned problems, and its purpose is to eliminate MOS-FE caused by plasma in the manufacturing process of a MOS device with a multilayer wiring structure.
It is an object of the present invention to provide a technique that can classify and clarify the degree of damage to T for each interlayer insulating film deposition process.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the invention according to claim 1 provides a gate of the single MOS-FET and the single MO
A predetermined number of TEGs are formed by connecting the diffusion layer formed near the S-FET with wiring, and the wiring layer of the wiring connecting the gate of the single MOS-FET and the diffusion layer is the predetermined number of TEGs. These are semiconductor wafers that are different in each case.

The invention according to claim 2 is a semiconductor device constructed using the semiconductor wafer according to claim 1.

Further, the invention according to claim 3 provides a single MOS/
This is a process evaluation method for semiconductor devices that evaluates the degree of damage to FETs individually.

[Effect]

The single MOS/FET constituting the TEG is easily damaged when its gate is in a floating state.

Therefore, for example, in the first TEG, the wiring connecting the gate of a single MOS/FET and the diffusion layer of the clamp circuit is
It is assumed that this is the first layer wiring, and in the second TEG, it is the second layer wiring. Further, the interlayer insulating film that insulates the first layer wiring and the 21st layer wiring is plasma CVD.
Assume that it is deposited using the D method.

In this case, in the step of depositing the interlayer insulating film, step 11 (
The gate of the DTEG (7) single MOS-FET is connected to the diffusion layer of the clamp circuit via the first layer wiring, so when the charge accumulated in the first layer wiring is discharged, Although the damage is alleviated, the single M of the second TEG
The OS/FETit is in a 70-ting state because the second layer wiring has not been formed yet.

Therefore, after the wafer process was completed, an electrical test was conducted on the two TEGs mentioned above. There was no abnormality in the single MOS/FET of the first TEG, but there was damage to the single MOS/FET of the second TEG (changes in threshold voltage). If damage (or destruction of the gate insulating film) is found, it can be said that the cause of this damage lies in the deposition process of the interlayer insulating film.

In this way, by individually evaluating a predetermined number of TEGs in which the gate of a single MO3 FET and the diffusion layer of a clamp circuit are connected by wiring in different wiring layers, the degree of damage to MOS FETs caused by plasma can be evaluated. The text can be divided and clarified for each interlayer insulating film deposition process.

〔Example〕

FIG. 1 is a schematic plan view of a first TEG formed on a semiconductor wafer constituting a semiconductor device according to an embodiment of the present invention;
Figure 2 is a sectional view taken along the ■-■ line in Figure 1, and Figure 3 is a cross-sectional view of the
FIG. 4 is a schematic plan view of the third TEG, FIG. 4 is a sectional view taken along the line rV-1'V in FIG.
The figure is a cross-sectional view taken along the line VT-Vl in FIG. 5, and FIG. 7 is a schematic plan view of this semiconductor wafer.

As shown in FIG. 7, a large number of integrated circuit regions 2 are arranged in a lattice pattern on the surface of a semiconductor wafer 1 made of, for example, p-type silicon single crystal. Although not shown, an MO3 integrated circuit is formed in each integrated circuit region 2. This M
The O8s product circuit has, for example, an A13 layer wiring structure.

The remaining area of the integrated circuit area 2 is a so-called scribe area, and after the wafer process is completed, this area is cut to create semiconductor pellets. A predetermined number of TEGs (T.

~T, ) are arranged at predetermined intervals.

Among the above TEG (T, ~T, ), T,, T,
and Ts are the TEGs of this embodiment, and their respective configurations are as follows.

First, the first TEG (T,) is as shown in FIG.
The MOS-FETQ and the diffusion layer 3 in its vicinity form an ia structure. The MOS-FETQ and the diffusion layer 3 are, for example, a field insulating film 4 made of 5102.
are separated from each other by.

The MOS-FETQ is composed of a diffusion layer 5 serving as a source/drain region and a gate 6 made of polysilicon, for example. This configuration is the same as the MOS/FET formed in the integrated circuit area 2 and forming the O5 integrated circuit.

The diffusion layer 5 and the diffusion layer 3 of the MOS/FETQ are:
For example, it is created by ion implantation of n-ru impurities such as phosphorus (P) and arsenic (As).

First layer Al interconnections 7a and 7b are connected to the source and drain regions of the diffusion layer 5 via contact holes C, C2. Further, one end of the gate 6 (upper side in the figure) is connected to the first layer and l wiring 7C via a contact hole C3.
is connected. Note that the other end side of this A2 wiring 7C is for power supply A, f! connected to the pad.

A contact hole C is provided at the other end of the gate 6 (lower side in the figure).
One end of the first layer Al wiring 7a is connected via 1. Further, the other end of this AA wiring 7d is connected to the diffusion layer 3 via a contact hole C5. That is, M
A clamp circuit consisting of an AA arrangement 7d and a diffusion layer 3 is provided in the OS-FETQ, and is configured to alleviate damage to the MO5FETQl caused by plasma.

The cross-sectional structure of the above TEG (T,) is as shown in FIG. That is, the MO3 FETQ has a diffusion g5, a gate dovetail film 8 made of, for example, Sigh,
The gate 6 is connected to the diffusion layer 3 by an Aβ wiring 7d.

A SiO□ film 9 is deposited on the field insulating film 4 using, for example, a CVD method.

On top of this 5102 film 9, there is a first layer deposited using, for example, sputtering! To the wirings 7c, 7d, and the first layer not shown in FIG. Wiring 7a7b is formed.

A first interstone insulating film 1 is formed on the first layer Al wirings 7a to 7d.
0 is coated. This first interlayer insulating film 10 is composed of, for example, a SiO□ film deposited using a plasma CVD method.

A second interlayer insulating film 11 is deposited on the first interlayer insulating film 10 with a second layer A1 wiring (not shown in FIG. 2) interposed therebetween. This second interlayer insulating film 11 is made of, for example, plasma C.
It consists of a film S10 deposited using the VD method.

A passivation film 12 is deposited on the second interlayer insulating film 11 with a second layer A1 wiring (not shown in FIG. 2) interposed therebetween. This passivation film 12 is composed of, for example, a 5IsNa film deposited using a plasma CVD method.

Next, the second TEG (T2) is configured as shown in FIGS. 3 and 4. That is, like the first TEG (TI), this TEG (T2) is a MOS-F E
T Q2, the diffusion layer 3, and Aj connecting these
It consists of 2 wires.

The difference with TEG (TI) is the MO of TEG (T,)
The S-FETQ and the diffusion layer 3 are connected to the first layer Al wiring 7d.
In contrast, in TEG (T2), the first FAf wiring 7e, 7f and the second layer Al wiring 13
It is at the point connected by a. Note that the second layer Al wiring 1
3a are connected to the first FAf wirings 7e and 7f via through holes Th, Th, opened in the first interlayer insulating film 10.

In this way, in the second TEC, (T2), the first
By forming the second layer Al wiring 13a on the interlayer insulating film 10, the MOS-FETQ2 and the diffusion layer 3 are connected for the first time.
are electrically connected. That is,
In the step of depositing the first interlayer insulating film 10 using the plasma CVD method, the gate 6 of the MOS-FET Q2 is in a floating state.

Next, the third TEG (T3) is as shown in FIGS. 5 and 6. That is, this TEG (T3) also
Similar to TEG (T,, T2) described above, MOS
-FETQ, diffusion layer 3, and Af connecting these
It consists of wiring.

The difference from TEG (T,, T2) is that MOS-FETQ
Y and the diffusion layer 3 are the first layer A f wirings 7g and 7h.

Second layer Aβ wiring 13b, 13c and third NA1 wiring 1
It is located at the point connected by 4. The second layer A1 wiring 13b has a through hole Th3 opened in the first interlayer insulating film 10.
1st F through! Connected to Af wiring 7g, second layer A
The first wiring 13C is connected to the first FAf wiring 7h via a through hole Th formed in the first interlayer insulating film 10. Further, the third T5 Aβ wiring 14 is formed through through holes Ths and Ths formed in the second inter-fan insulating film 11.
It is connected to the second layer and I wirings 13b and 13c via.

In this way, in the third T, EC (T3), the second
By forming the third layer, l wiring 14, on the interlayer insulating film 11, the MOS-FETQ3 and the diffusion layer 3 are connected for the first time.
are electrically connected. That is,
In the step of depositing the first interlayer insulating film 10 and the second interlayer insulating film 11 using the plasma CVD method, the MOS-FET
Gate 6 of Q3 is in a floating state.

Next, a process evaluation method using the above T EG (TI to T3) will be explained. The target of the process evaluation here is that when the first interlayer insulating film 10 and the second interlayer insulating film 11 are deposited using the plasma CVD method, the MOS-FET formed in the integrated circuit area 2 is The question is how much damage was sustained.

To perform the above process evaluation, TEG (T, ~T3)
This method takes advantage of the fact that when the gate 6 of the single MOS/FET Q, ~Q3 that constitutes is in a floating state, it is more easily damaged than when this gate 6 is connected to the diffusion layer 3. .

That is, after the wafer process is completed, TEG (T~T
3) Apply a probe to each pad (not shown) and conduct an electrical test individually to test the individual MOS/FETQ, ~Q3
The degree of damage (change in threshold voltage and breakdown of gate insulating film 8) is examined. As a result, for example, the first TEG (
(7) If there is no abnormality in the single MOS/FETQ, but damage is found in the single MOS/FETQ2 of the second TEG (T2), the cause of this damage is the first interlayer insulating film. It can be said that there are 10 deposition steps. That is, in the step of depositing the first interlayer insulating film 10, the first
The gate 6 of the TEG (T,) is connected to the third layer A1 wiring 14
Since it is connected to the diffusion layer 3 of the clamp circuit through This is because 13a is not formed, so it is in a floating state.

Next, for example, the single MO5 F of the first TEG (T,)
ETQ, rgo also has a second TEG (T2n's single M
There is no abnormality in OS-F ETCh, and the third TEG (
When damage is found in the single MO3 and FETQ1 of T3), it can be said that the cause of this damage is in the deposition process of the second interlayer insulating film 11. That is, in this case, in the step of depositing the second interlayer insulating film 11, the second TE
The gate 6 of G(T2) is the first layer AI! Arrangement 7e, 7f
Since the gate 6 of the third TEG (T,) is connected to the diffusion layer 3 via the third layer A1 wiring 14a, damage to the MOS-FET Q2 due to plasma is alleviated. This is because the A1 wiring 14 is not formed and is therefore in a floating state.

In this way, A13 is placed in the integrated circuit area 2 of the semiconductor wafer 1.
A MOS integrated circuit with a layer wiring structure is formed, and a single MOS/FET is formed in the remaining area of the integrated circuit area 2.
Three types of TEG (T+ -T*) are formed by connecting the gate 6 of the above-mentioned single MOS/FET and the diffusion layer 3 formed in the vicinity of the single MOS/FET with wiring of different wiring layers, and each TEG (T, ~Ts)
FETQ, ~Q3 '7) When the gates 6 are in a floating state, those gates 6 are connected to the diffusion layer 3
Compared to when connected to a standalone MOS/FETQ
, ~Q.

Each T E
Single MOS/FET that constitutes G (T+ -T3)
According to this embodiment, in which the degree of damage to Q, ~Q3 is individually evaluated, the first interlayer insulating film 10 is formed using a plasma CVD method.
When the second interlayer insulating film 11 is deposited, the degree of damage sustained by the MOS-FET formed in the integrated circuit region 2 can be classified and clarified for each step of depositing the interlayer insulating film 10.11. .

This facilitates optimization of the manufacturing process of a MOS device having an AN three-layer wiring structure, thereby shortening the development period of the MOS device.

Above, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the Examples and can be modified in various ways within the scope of the invention. It goes without saying that there is.

In the above embodiment, a case was explained in which a MOS integrated circuit with a 13-layer wiring structure was formed in the integrated circuit area of a wafer.
It can also be applied to the case of forming an integrated circuit, that is, a MOS integrated circuit including three or more layers of interlayer insulating films deposited using the plasma CVD method.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

That is, there are multiple patterns 'f' in the integrated circuit area of the semiconductor wafer.
A MOS integrated circuit having the A structure is formed, and the gates of the single to 105 FETs and the diffusion formed near the single MOS/FET are formed in different wiring layers in the remaining area of the integrated circuit area. A predetermined number of TEGs connected by wiring are formed, and a single MOS constitutes each TEG.
・By evaluating the degree of damage to FETs individually, the degree of damage caused by plasma to MOS-FETs formed in the integrated circuit area can be classified and clarified for each interlayer insulating film deposition process. be able to.

This facilitates optimization of the manufacturing process of a MOS device having a multilayer wiring structure, thereby shortening the development period.

[Brief explanation of the drawing]

Figure 1 shows a semiconductor device which is an embodiment of the present invention! FIG. 2 is a schematic plan view of the first TEG fabricated on a semiconductor wafer constituting the semiconductor wafer, FIG. The figure is the third
The rV-IV line sectional view in the figure, Figure 5 is also the third TEG.
6 is a sectional view taken along the line Vl--Vl in FIG. 5, and FIG. 7 is a schematic plan view of this semiconductor wafer. 1... Semiconductor wafer 2... Integrated circuit area, 3.5
... Diffusion layer, 4... Field insulating film, 6... Gate, 7a-7h... Second layer A1 wiring, 8... Gate insulating film, 9... SiC, film, IO. ...First interlayer insulating film, 11... Second interlayer insulating film, 12... Passivation film, 13a to 13C... Second layer A1 wiring, 1
4...Third layer A1 wiring, C2-C5...Contact hole, Ql-Q,...MOS-FET, T,-
T1...TEGSTh, -Ths...Through hole. Figure 11: Man's ZFj calm attitude No. 14: Military 3rd layer A! Wiring diagram T1-T0: TEG diagram

Claims (1)

[Claims] 1. A MOS integrated circuit having a multilayer wiring structure is formed in the remaining area of the integrated circuit area, and a gate of a single MOS/FET is formed in the remaining area of the integrated circuit area, A semiconductor wafer on which a predetermined number of TEGs are formed by connecting the single MOS/FET to a diffusion layer formed in the vicinity of the single MOS/FET, the wiring connecting the gate of the single MOS/FET and the diffusion layer. A semiconductor wafer, wherein the wiring layer is different for each of the predetermined number of TEGs. 2. A semiconductor device constructed using the semiconductor wafer according to claim 1. 3. Each T formed on the semiconductor wafer according to claim 1
A process evaluation method for a semiconductor device, characterized in that the degree of damage to a single MOS/FET constituting an EG is evaluated individually.