JPH02116948A - Information processing system - Google Patents

Abstract

PURPOSE:To execute the transfer communication of information at a high speed by constituting the title system so that an access to each group is determined by a processing mode and a processor number of a processor for executing an access. CONSTITUTION:When a request from a processor is received, a requested processor number, an operation mode of the processor, and address information are received by a processor number register 14, a mode register 9, and an address register 10, respectively. When the operation mode register 9 shows '1' of a privilege mode, the processor which sends out the request executes a system program, and when said register shows '0' of a non-privilege mode, the processor executes a user program.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of accessing a communication register for transmitting information at high speed between processors in a multi-gross sensor system.

(Prior Art) The purpose of configuring a system with multiprocessors is generally to increase the overall throughput of the system, but in some cases it is also required to shorten the turnaround time of a certain job. In this case, among the tasks of the job, those that have no dependencies can be accomplished by executing the tasks in parallel on multiple processors, or by having multiple processors execute a part of a task in parallel. be.

When certain tasks are executed in parallel, there may be synchronization between the tasks, or data that is commonly referenced between the tasks and should be used exclusively. When this data should be used exclusively, a lock word is determined, and if that word is unlocked, that word is locked, and only the locked processor can use the data exclusively. refer.

When the processor refers to the lock word and is in the locked state, the lock word is unlocked and access to data that should be used exclusively is prohibited. Conversely, when executing in parallel, it may be possible to refer to the same data.These data are generally stored in main memory.

(Problem to be Solved by the Invention) However, in the conventional information processing system described above, information is transmitted and communicated between processors.

Since the main memory is used, there is a drawback that the speed of information transmission and communication is slow.

In view of the above drawbacks, a second technical object of the present invention is to provide an information processing system that increases the speed of information transmission and communication between processors.

(Means for Solving the Problems) According to the present invention, there is provided an information processing system including a communication register accessed by a plurality of processors and composed of a large number of entries, wherein the communication register is divided into several groups. An information processing system is obtained in which access to each group is determined by the processing mode and processor number of the accessing processor.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

Processor "0 (1), 7'processor" 1 (2)
, processor #2 (3), and processor #3 (4) are normal processing devices and are all the same. The main memory 5 exchanges data between processors #0-3 (1-4).

Data is also exchanged between the communication register 6 and processors #0 to #3 (1 to 4). Communication register 6 is used as a storage location for information communicated between processors #0-3 (1-4).

FIG. 2 is a diagram showing one embodiment of the communication register 6. The communication register consists of 256 words (64 bits/word), 1st group A is word O to 127°, group B is word 128
-1599 group or words 160-1919 group is divided into words 192-2239 group E is divided into words 224-255. For each group of communication registers B-E, there is a 4-bit communication register 8, each bit corresponding to each processor. For example, as shown in FIG. 2, the leftmost bits correspond to processors 0, 1, 2, and 3. When a certain processor requests access to a communication register, the communication register directory 8 is checked and the specified communication register in the communication register group whose bit corresponding to the processor number is "1" is accessed.

FIG. 3 shows an example of access to the communication register 8. When a request is received from a processor, the requested processor number is stored in processor number register 1.
4, set the operating mode of the processor to mode register 9,
Address information is received into address register 10. Operating mote v'y, x.

If register 9 is 1", it indicates the privileged mode, and the processor that sent the request is executing the system program. If the operating mode register 9 is 0", it indicates the non-privileged mode, and the processor that sent the request is running the system program. A user program is running.

If the operating mode register 9 is "1", the indicated entry is 25 in bits 56 to 63 of the address register 10.
Any of the 6 words may be accessed. When the operating mode register 9 is '0'', the contents of the processor number register 8 are decoded by the decoder 11, and the output result and each bit of the communication register direct reef corresponding to the communication register group B-E are decoded by the comparator 12. The output of each comparator 12 is converted into 2 bits by an encoder 13.

To the left of these 2 bits, mode register 8 is set to non-privileged mode, so "1" is written, and to the right of the encoded 2 bits, bits 59-63 of address register 10 are written.
By combining.

The desired communication register is accessed.

FIG. 4 shows how to use each word of a communication register having a capacity of 256 words. FIG. 4(a) shows a format used as a data register for storing information. (
b) is a format used as a lock word for exclusive control. It is up to the software to decide which word in the communication register is used as a data register or a lock word. When used as a lock word, bit 0 is the lock indicator, and “1” indicates the lock status to “0”.
'' indicates an unlocked state. Bits 8-31 are a count section. Bits 32-63 store pinpoints 32-63 of data sent from the processor when locked.

Three types of instructions are prepared for accessing communication registers from the processor. These are a communication register save instruction to read the contents of the communication register, a communication register load instruction to store data sent from the processor to the communication register, and a communication register test and set instruction.

FIG. 5 is a block diagram showing instruction operations related to communication registers. The instruction register 20 receives instruction codes from the processor, and the data register 15 receives data from the processor. The contents of the instruction register 14 are decoded by a decoder 19. If the decoding result is a load instruction to the communication register, data register 1 will be loaded into the specified communication register.
Write the contents of 5. If the result of decoding the instruction register 14 is a communication register save instruction, the contents of the specified communication register are read into the 9 communication register read register 16 and sent to the requesting processor. Result of decoding of instruction register 20.

The contents of the communication register designated as a communication register test and set command are read to the two-communication read register 16 and sent to the requesting processor. The contents of bit O of the communication read register 16 are checked, and if bit O is 0, it is in the unlocked state, so bit O is set to 1.
''', all 1's in bits 8-31'', bits 32-6
3, bits 32-63 of data register 15 are stored in the designated communication register. That is, this indicates that the lock has been successfully achieved, and the counter section shown in FIG. 4(b) is set to the maximum value. The processor receives the lock word and can know that the lock was successful by testing its bit O with a subsequent instruction of the test and set instruction.

Even if bit 0 of the data read to the communication register read register 16 by the communication register test and set command is 1, the data is sent to the requesting processor.If bit 0 of the communication register read register 16 is 11
If it is 111, the contents of the count section at 8-31 are decremented by 1 in the decrement circuit 17, and the result is returned to the original communication node. When the deadlock detection circuit 18 detects that the result of subtracting 1 by the decrement circuit 17 from the contents of the count section of bits 8-31 is "0'", it notifies the processor of a deadlock detection signal. When the processor receives this signal, it enters deadlock exception handling. That is.

While the lock word is accessed twice.

Since the lock is not released and there is an abnormal condition, the process branches to that processing routine.

The processor receives the data resulting from the execution of the test and set commands, checks the bit O in the subsequent command, and finds that it is "1" to indicate that the lock has failed. At this time, the test and set commands are sent again and this operation is repeated until the lock is released.

There is a directory control command for setting or resetting bits in the communication register directory 8 shown in FIGS. 2 and 3. FIG. 6 shows the data format.

Bit 55 indicates control of the directory (Shibit) 6
0-63 indicates the master processor. bit 60
If is 1″, the master processor is processor #o (
i), if bit 61 is 111 I+, it indicates that the master processor is processor "1 (2).

If the C bit of bit 55 is 1, first, the communication register directory is checked using the requested processor number, and the bit corresponding to the processor number in the matching directory is reset. Next, the communication register directory is checked using the master processor data in bits 60-63, and a bit corresponding to the processor number is set in the matching directory.

If the C bit of bit 55 is 0, first beep) 60
Check the communication register directory using the master processor number -63, and reset the bit corresponding to the requested processor number from the matching directory. Subsequently, communication register directories that are empty, that is, in which no bits are set, are checked and a bit corresponding to the requested processor number is set in one of the directories.

An example of a procedure for performing multi (micro)tasking using communication registers is shown below. Assuming that each processor is doing a separate job, the group B of communication registers is:
Processor #0 has 2nd group C as processor #1 (2), group E as processor #2 (3), and group E as processor #3 (
4).

The program running on fo processor #1 (2).

When multitasking is indicated, the system program uses the currently idle processor or
A processor that is currently running but is executing a job with a low level (f priority) is secured. Here, it is assumed that processor '2(3) was idle and was reserved for executing multitasking. The secured processor #2 (3) executes the directory control instruction whose C bit is 1. The master processor at this time is processor "1 (2)."

Therefore, the result of executing a directory control instruction.

The group directory becomes empty, and the bits of processor "1 (2)" and processor "2 (3)" are set in the directory of the second group C. Therefore, processor #1 (2) and processor "2 (3) can communicate and access group C of tasks. In other words, processor #1 (2) can access task group C by referring to the information stored in the communication register of group 2 C. ) and processor "2 (3) execute tasks in parallel. When the need for multitasking is eliminated, processor #2 (3) executes a directory control instruction with the C bit set to O. As a result, the bit of processor #2 in the group C directory is reset and the bit corresponding to processor #2 in the empty group directory is set.

(Effects of the Invention) As explained above, the present invention provides a communication register that can be accessed by a plurality of processors, and has means for accessing this communication register, thereby enabling high-speed communication of information between f processors. There are effects that can be implemented.

・Task directory, 9...Mode register, 1°...Address register, 11...Decoder, 12.
...Comparator, 13...Encoder, 14...Processor number register, 16...Communication register read register.

17...Decrement circuit, 18...Deadlock detection circuit, 19...Decoder, 20...Instruction register.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram showing one embodiment of the present invention;
The figure is a configuration diagram showing one embodiment of a communication register. Third
The figure shows an example of a procedure for accessing a communication register. FIG. 4 shows the format of how to use the words of the communication register. FIG. 5 is a diagram showing command operations related to communication registers. FIG. 6 is a diagram showing the control data format of the communication register directory control command. 1-4... Processor, 5... Storage control device, 6.
...Communication register (CR), 7...Main memory, 8...
Communication Agent (7783) Patent Attorney Noriyasu Ikeda Figure Block Display Area Figure Figure

Claims (1)

[Claims] (1) In an information processing system including a plurality of processors each having a processor number, a storage device accessed by the plurality of processors, and a communication register accessed by the plurality of processors and composed of a plurality of entries. The information processing system is characterized in that the communication registers are divided into several groups, and access to each group of the communication registers is determined by the processing mode and processor number of the accessing processor.