JPH02116207A - Differential circuit - Google Patents

Abstract

PURPOSE:To synchronize the output level of a differential circuit part to the voltage fluctuation of a power source VSS and to synchronize with the fluctuation of the input logical threshold of a next step BFL inverter by using a differential circuit connecting a DFET in which the VSS is connected to a gate between the complementary output edges of the differential circuit, for an ECL input circuit. CONSTITUTION:When an input signal IN is level-shifted and a low level is inputted to a depression type MES electric field effect transistor (DFET) Q109 of the differential circuit of the circuit in an ECL input circuit, a high level is outputted to a contact N103, a low level is outputted to a contact N102 by the difference voltage in a referring voltage VREF, the contact N102 at the low level side of the differential circuits is clamped through a DFET Q122 to the potential of the contact N103 at the high level side and the level of the N102 at the low level side at this time depends on the capability of the DFET Q122. Namely, by the voltage fluctuation of the power source VSS, the level of the N102 at the low level side of the differential circuit is changed. Thus, the level of an output contact N104 of a differential circuit part 12 is synchronized to the level of the power source VSS.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to compound semiconductor integrated circuits, and particularly to differential circuits.

[Prior art] Conventionally, this type of differential circuit is a depletion type ME for load.
S field effect transistor (hereinafter referred to as depletion mode ME)
(S field effect transistor is called DFET), input D
It was composed of a FET and a constant current source DFET, and was converted to the BFL level, which is the GaAs internal logic level, through level shifting. This will be explained below using the drawings.

FIG. 3 is a circuit diagram of an ECL input circuit using a conventional differential circuit. The human input signal IN is input level shift circuit section 31
The output signal N301 is level-shifted by and input to the differential circuit section 32. In the differential circuit section 32,
The differential voltage between the reference voltage VREF and N301 is amplified and level shifted to convert it to a BFL level, and the output signal N304 of the differential circuit section 32 is input to the next stage BFL inverter.

Figure 4-a shows VSS=-2, OV, VEE=-5,2V
This is the DC transfer characteristic of the conventional ECL input circuit at (1). ECL input high level/low level = -Q, 9V/-1
゜When 7V is input to IN, the contact N of the differential circuit section 32
The output voltage appearing at 304 is high level/low level = -1,
6V/-2,7V is output.

[Problems to be Solved by the Invention] In the ECL input circuit using the conventional differential circuit described above, due to the voltage fluctuation of the power supply vSS, the BF of the next stage of the differential circuit section 32
The input logic threshold of the L inverter varies greatly. Figures 4-b and 4-c are VSS = -2 and 4V, respectively.
(+20%), ■5S=-1.6V (-20%), which are the DC transfer characteristics of a conventional ECL input circuit, and both VEEs are -5°2V. Output signal N30 of differential circuit section 32
DCL/J\le of 4 does not depend on the fluctuation of VSS, and B
The input logic threshold of the BFL inverter of the FL circuit section 33 changes. In particular, in Figure 4-b, ■5S=-2,
In the case of 4V (+20%), the low level of the output potential N304 of the differential circuit section 32 is a sufficiently low level (for example, the level of If the threshold voltage is VTD, it will not be less than [VSS-+VTD l], so there is a drawback that DFET Q317 of the BFL inverter cannot be sufficiently cut off.

[Differences between the invention and the prior art] E configured with the above-mentioned level shift and conventional differential circuit
For the CL input circuit, the present invention provides a complementary output terminal (
By using a differential circuit in which a DFET with vSS connected to the gate between N302 and N303 in Figure 3 is used as the ECL input circuit, the output level of the differential circuit section can be synchronized with the voltage fluctuation of the power supply vSS. , the difference is that it can be synchronized with the fluctuation of the human logic threshold of the next-stage BFL inverter.

[Means for solving the problem] The differential circuit of the present invention is connected between the complementary output terminals (N103 and N102 in FIG. 1) of the differential circuit in the ECL input circuit, and the gate is connected to VSS. It has a DFET.

That is, in the differential circuit of the present invention, the gate of the first depletion field effect transistor is connected to the first contact, the drain is connected to the first power supply, the source is connected to the first contact, and the gate of the first depletion field effect transistor is connected to the first contact.
The gate of a third field effect transistor is connected to a second contact, the drain is connected to the first power supply, and the source is connected to the second contact, and the gate of a third field effect transistor is connected to the first signal line, and the drain is connected to the first signal line. a source of the first contact is connected to a third contact, a gate of a fourth field effect transistor is connected to a second signal line, a drain is connected to the second contact, and a source is connected to the third contact; The gate of a fifth depression type field effect transistor is connected to a second power source, the drain is connected to the third contact, and the source is connected to the second power source, and the gate of the sixth depression type field effect transistor is connected to a third power source. The drain is connected to the first contact and the source is connected to the second contact.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an EC of the first embodiment using the differential circuit of the present invention.
FIG. 3 is a circuit diagram of an L input circuit. The input signal IN is level-shifted by the input level shift circuit section 11, and its output signal N101 is input to the differential circuit section 12. The differential voltage between the reference voltage VREF and N101 is amplified and level-shifted in the differential circuit section 12 to convert it to the BFL level.
It is input to the FL inverter. In contrast to the conventional ECL input circuit using a differential circuit, the present invention uses the DFET shown in FIG.
It is configured by adding Q122. Figure 23 shows VSS
FIG. 2 is a DC transfer characteristic of an ECL input circuit using the differential circuit of the present invention when VEE=-2, OV and VEE=-5°2V. Figure 2-b and Figure 2-C are VSS = -2 and 4V, respectively.
(+20%), VSS=-1.6V (-20%), and VEE are both -5.2V (-20%).

Hereinafter, the operation of FIG. 1 will be explained using FIG. 2-a, FIG. 2-b, and FIG. 2-c. In FIG. 1, the input signal IN
When J\ is inputted to DFET Q109 of the differential circuit in the ECL input circuit, the voltage difference between it and the reference voltage VREF causes the contact N103 to have a high level and the contact N102 to have a low level. The level will be output. At this time, the contact N102 on the low level side of the differential circuit is clamped to the potential of the contact N103 on the high level side via DFET Q122. Therefore, at this time, the low level side N10
The level of 2 depends on the capabilities of DFET Q122.

In other words, due to the voltage fluctuation of the power supply VSS, which is the gate potential of DFET Q122, the low side N1 of the differential circuit
02 level changes. Therefore, the level of the output contact N104 of the differential circuit section 12 is synchronized with the level of the power supply VSS.

Part 2-4. As shown in the figure, VSS=-2,4V (Ty
p+20%), the input logic threshold of the next stage BFL inverter is lower, but the DFET Q1 in the differential circuit
22 capacity decreases, and the output N on the low side of the differential circuit decreases.
The level of 102 drops drastically compared to when VSS=-2.0V (Typ), and the output amplitude of the differential circuit increases,
The output contact N104 of the differential circuit section 12 is also Vss.
Since it is lower than when = -2,0 (Typ), it is at a sufficiently low level (for example, if VTD is the threshold voltage of Q117, it is below (VSS - VTDI)), so the next stage B
It is possible to sufficiently cut off the DFET Q117 of the FL inverter, and the voltage fluctuation of RI and VSS is ±20%.
It works until. From the above, it is clear that E
The differential circuit in the CL input circuit can synchronize with the level fluctuation of the human logic threshold value of the BFL inverter due to the voltage fluctuation of the power supply SS.For example, VTD = -0,5V
When the difference between the low level of the power supply VSS and the output N104 of the differential circuit section 12 is Δ■, the deviation can be greater than ΔV=1V, and the differential circuit section 120 can stably drive the next stage BFL inverter. I can do it.

FIG. 5 shows an ECL using a differential circuit according to the second embodiment of the present invention.
FIG. 3 is a schematic diagram of the input circuit. Compared to the embodiment of FIG. 1, the differential circuit input transistor or DFE in the differential circuit section 52
T to enhancement type MES field effect transistor Q509. Q51C] (hereinafter referred to as enhancement type ME
A field effect transistor is called an EFET. In this embodiment, EFET Q509. is used as the input transistor of the differential circuit. Because I am using Q510,
It has the advantage of being easy to operate even if the voltage difference between the input signal IN and the reference voltage VREF is small. The operation is almost the same as the embodiment shown in FIG. 1, and the explanation of the operation will be omitted here.

As explained above, the present invention provides a differential circuit section (1
The output level (N104, N504.) of 2, 52) can be synchronized with the voltage fluctuation of the power supply VSS, and can be synchronized with the fluctuation of the human logic threshold of the BFL inverter in the next stage BFL circuit section. The low level side output (NiO2, N50/1-) of the section (12, 52) is connected to a sufficiently low level signal (for example, the threshold voltage of the driving DFET of the next stage BFL inverter is set to VFD and (VSS-I). VTD or less)
It can be done. For example, when vrD=-o:5■, the power supply VSS and the output N104 of the differential circuit section (12)
If the difference between the low level signals is △V, then △V=IV or more can be taken, stably driving the BFL inverter in the next stage of the differential circuit section (12), and suppressing the voltage fluctuation of the power supply VSS by ±20%.
It has the advantage that it can operate up to

[Effects of invention

[Brief explanation of drawings]

FIG. 1 shows an E using a differential circuit according to the first embodiment of the present invention.
The circuit diagram of the CL input circuit, Figure 2-a is the DC of the ECL input circuit using the differential circuit of the present invention when 5S=-2, OV.
The transfer characteristic diagram, Figure 2-b, shows E using the differential circuit of the present invention.
CL input circuit VSS=-2,4V (Typ+20%
), Figure 2-c shows the DC transfer characteristic diagram when VSS = -1,6V (Ty
p-20%), Figure 3 is a circuit diagram of an EECL input circuit using a conventional differential circuit, and Figure 4-a is a VSS diagram of an ECL input circuit using a conventional differential circuit. =-2
, OV (Typ) DC transfer characteristic diagram, Figure 4-b shows an ECL input circuit (7) using a conventional differential circuit (7) VSS=
DC transfer characteristic diagram at -2,4V (Typ+20%),
Figure 4-c is a DC transfer characteristic diagram when VSS = -1°6V (Typ-20%) of an ECL input circuit using a conventional differential circuit, and Figure 5 is a diagram showing the difference between the second embodiment of the present invention. FIG. 2 is a circuit diagram of an ECL input circuit using a dynamic circuit. 1l-QIOI, Q106~Q112°Q115~Q118. Q121゜Q122. Q301. Q306~Q312゜Q
315-Q318. 'Q321. Q501゜Q50
6~Q508. Q511. Q512゜Q515
~Q518+Qδ21. Q522 ・ ・
・・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
・ ・ ・ ・ ・ ・ D F E T. Q509. Q5]0 ・D102~D105°D 119. D 1.20°D313. D314°D502~D505°D519. D520・ ・ ・ ・ ・ ・ ・ ・ E F E T. D113. D114°D302~D305°D319. D320°D513. D5] 4°...Diode, N101 to N105. N30] ~ N305°N50
1~N505. 0UTI, 0UT3゜0UT5・
・ ・・・・・・・・・・・・Contact, IN ・ ・
・ VREF ・ GND ・ ・ vSS ・ ・ VEE ・ ・ ...Input, ・Reference voltage, ・First power supply, ・Third power supply, ・Second power supply.

Claims (1)

[Claims] The gate of the first depression type field effect transistor is connected to the first contact, the drain is connected to the first power supply, and the source is connected to the first contact, and the gate of the second depression type field effect transistor is connected to the second contact. the drain to the first
A third field effect transistor has its gate connected to the first signal line, its drain connected to the first contact, and its source connected to the third contact; The gate of the field effect transistor is connected to the second signal line, the drain is connected to the second contact, and the source is connected to the third contact, and the gate of the fifth depletion type field effect transistor is connected to the second power supply, and the drain is connected to the third contact. A third contact has a source connected to the second power supply, a gate of a sixth depletion field effect transistor is connected to the third power supply, a drain is connected to the first contact, and a source is connected to the second contact. A differential circuit comprising: