JPH02116083A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To accelerate an access time to a memory by varying the value of a bias current permitted to flow on a pair of common readout data lines separately from that from a differential amplifier for readout corresponding to the operating timing of the memory. CONSTITUTION:At the load circuit 4 of the pair of readout common data lines RD and RD', the bias currents IE and IE'(IE=IE') are permitted to flow on bipo lar transistors Q1 and Q1', and those bias currents are varied corresponding to the operating timing of the memory. Therefore, when an amplifier 2 for readout is operated, the potential of the RD and the RD' can almost be kept constant. In such a way, it is possible to prevent readout speed from being lowered and to accelerate readout time even when a large number of the read out amplifiers 2 are connected and incidental capacitance is increased in a large cale of memory array.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memories, and particularly to speeding up the readout circuit thereof.

[Conventional technology]

Conventionally, regarding speeding up the access time of MOS static memory, IEE, Journal Off Solid State Circuits, Volume Nisshi 19. No. 5, pages 545-551.

[Problem to be solved by the invention]

According to the above-mentioned prior art, the basic circuit configuration around the memory cell is as shown in FIG. Its feature is that a read MO8 differential amplifier 2 and a write transfer circuit 3 are provided for each data line pair D' to which a plurality of memory cells are connected. 2 was not present in the old circuit, and the data line pair and the common data line pair (
reading.

(common for writing) and exchanged information. In FIG. 2, RD and RD' are a pair of common data lines for reading, to which the outputs of a plurality of MO5 differential amplifiers for reading are connected. On the other hand, WD and WD' are a common data line pair for writing, to which a plurality of write transfer circuits are connected. At the time of reading, a current flows from one side of the load MO5 (M1 #M1') toward the cell according to the information of the memory cell 1 connected to the selected word line W, creating a potential difference between the data line and D'. occurs. The read MO8 differential amplifier 2 is activated by the high potential of the read column selection signal line YSH, and a read signal voltage appears on the read common data line pair RD, RD'. During writing, the write column selection signal line YSW is set to a high potential, the write transfer circuit 3 is turned on, and the write common data line pair W
The advantage of this method is that the write data on D and WD' is sent to the data line pair D' and the desired write is performed in the selected memory cell. For memory cells with a small size, it is sufficient to drive only the data line pair and the read MO8 differential amplifier.

Read time can be increased. When this circuit system is used in a dynamic memory, the effect becomes even greater as will be described later.

However, in large-capacity static memory (SRAM) and dynamic memory (DRAM), many readout differential amplifiers are connected and the wiring length is long, so the readout common data line pair RD, RD' has a large parasitic capacitance and is made up of lMOS transistors. The second circuit that takes a large signal amplitude in the load circuit 4
The circuit system shown in the figure had a limit to its high speed.

An object of the present invention is to speed up the access time of semiconductor memories such as DRAM and SRAM.

[Means to solve the problem]

The purpose of the above is to clamp the potential of the read common data line pair RD, RD', which has a large parasitic capacitance, with a bipolar transistor, suppress the potential change due to '1/0' reading of RD, RD' as small as possible, and read The signal voltage that represents information is taken out at the connection point between the collector of the bipolar transistor and the load resistor.Furthermore, by switching the bias current flowing through RD and RD' in conjunction with the memory operation timing, the readout speed can be increased even against power supply noise. In addition, the bias current can be reduced during the standby period of the memory, and the current consumption during the standby period of the memory can be reduced.

[Effect]

In this configuration, when a bias current is passed through RD and RD', the read common data line pair RD and RD' due to the read current difference when information different from "1" and '0' is read.
On the other hand, as a signal voltage for operating the subsequent stage circuit, a differential voltage represented by the product of the read current difference and the collector load resistance is taken out from the collector side. The equivalent load resistance of the read common data line pair is the internal resistance ra seen from the emitter side of the bipolar transistor, and assuming the bias current IE, rp=kT/qIε
It can be set to a value smaller than the actual load resistance on the collector side (k is Boltzmann's constant, T is temperature, and q is the amount of electron charge). Since rE can be suppressed to 100Ω or less by IH, even if a large parasitic capacitance is attached to the read common data line pair, its time constant (product of parasitic capacitance and equivalent resistance) can be suppressed to a relatively small value. Furthermore, if the bias current of the bipolar transistor is changed according to the operation timing, the bias current can be reduced during the memory standby period to suppress current consumption, and the operation period can be increased to reduce rE.
Furthermore, even if noise occurs in the power supply due to the operation of other peripheral circuits, the influence of power supply noise on the readout speed can be suppressed to a small level by adjusting the bias current during the operation period.

〔Example〕

The present invention will be explained in detail below using examples.

Although the embodiment will be explained using a DRAM circuit, the present invention is applicable to a DRAM circuit.
It is not limited to M, but can also be used in other SRAMs, ROMs, and bipolar memories.

FIG. 1 shows an embodiment in which the present invention is applied to a DRAM, and FIG. 3 is an operation timing diagram thereof. Circuit 1 is 1MO8
, a dynamic memory cell consisting of one capacitor. Circuit 5 is a precharge circuit, and during the memory standby period, the precharge line PC is set to a high potential, and the data line is
D' is the precharge voltage HVC (e.g. power supply voltage vC
Precharge to 1/2 of C). The circuit 6 is a rewriting amplifier, which reads information from memory cells.

After reading data to D', by changing the drive line PP to a high potential and PN to a low potential, the high potential side of D' is set to the PP level (power supply voltage Vcc or a constant lower than Vcc when using an electric limiter). voltage), and the low potential side to PN level (
GND level).

The read information is rewritten into the memory cell.

Circuit 2 is a read amplifier. MOS to which the column selection signal YSR is input during reading
A MOS for receiving data line pair signals is placed on the GND side. In this configuration, RD.

Since only the amplifier 2 of the selected column is electrically connected to RD', even if the potential of one of the data line pairs D' rises to the Vcc level due to the rewriting operation, the data lines of many non-selected columns will be connected to RD'. The read common data line pair RD and RD' are electrically isolated from each other, and a large number of unselected column data line capacitances are not added to the parasitic capacitance of the read common data line pair RD, RD'. Note that among the large number of read amplifiers 2 provided for each data line pair, current flows only through the amplifier selected by YSR. This current and.

The bias current of the read common data line pair RD, RD' has a small number of circuits, so its contribution to the current consumption during operation is small, and as will be described later, these currents can be kept small during the standby period. Circuit 3 is a write transfer circuit. The gate control signal YSW becomes High only in the selected column and during writing.

It remains Low during reading.

As mentioned above, in this configuration, the read common data line pair RD,
In the load circuit 4 of RD', bias current Igt IE (I
E=Ip') is caused to flow and this bias current is changed in accordance with the operation timing of the memory. When the read amplifier 2 operates, the potentials of RD and RD' are Q
If the base potential of l and Ql' is Va, then Vt5-Vts
It becomes almost constant at e. Therefore, even if a large number of read amplifiers 2 are connected in a large-scale memory array and the parasitic capacitance increases, there is little deterioration in read speed. The signal voltage is Ql
, the collector PI of Ql', taken out from PL', PL
, PL' are much smaller than those of RD and REI', and the time constants of PL and PL' are small. P.L.
The required signal amplitude at PL and PL' differs depending on the configuration of the subsequent circuit, and if a bipolar differential amplifier is used in the subsequent circuit, the sensitivity is good, so the signal amplitude at PL and PL' can be reduced, which is effective for further speeding up. .

Next, we will explain why it is necessary to change the bias current depending on the memory operation timing. FIG. 4 corresponds to the operation timing diagram of FIG. 3, and also shows the power supply noise within the chip. When CE becomes a low potential, many address buffers and decoder circuits start operating all at once, so the Vcc and GND lines near the load circuit 4 also drop to about 0 as shown in Figure 4.
．． It causes a 5v vibration. Therefore, the base potential VB of Ql and Ql' drops by about 0.5v, while the emitter potential is RD
, RD' is difficult to reduce significantly, so the cutoff period (t1 to ta in FIG. 4) becomes longer. In this cutoff state, the word line signal W.

When the column selection signal YSR becomes a high potential selection state (tz)
, D, D', readout amplifier 2 operates according to the signals R
A current difference occurs between D and RD'. However, this current does not appear in the collector, and the potentials of RD and RD' decrease Ql and Ql.
A signal voltage is not generated at PL and PL' until ' is turned on again. In this way, the high speed of the original current sensing method cannot be achieved due to the power supply noise inside the chip. It is difficult to reduce power supply noise, especially when In DRAM and SRAM, it is possible to start up many circuits at once by inputting an external clock.
Signal amplification is as large as the power supply voltage, and large power supply noise is generated due to reasons such as rewriting operation 1 in the DRAM.

Therefore, in the present invention, after the chip enters the operating state, W, Y
During the period (approximately 1. to tz) until SR is selected, by particularly increasing the bias current, Ql,
Speed up the on-recovery of Ql'(ta=6ta'), W,
As soon as YSR is selected, a signal voltage appears on the collector side of Ql and Ql'. FIG. 5 shows a principle example of bias current control for this purpose. IB in Figure 5
I~Igsw Igx'~I Ell' are bias currents with different values (however, II!t=IEI'), and SI!
1 to SE8, SEX' to Sga' are switches, and 0
1 to Cai are switch control signals. FIG. 6 shows the voltage and current waveforms at that time. Waiting period (GE: Hi
In gh), only Cz is High, and the sum ICE of each bias current is a minute current IE! Only. Operating period (100E
: Low), 01 becomes High and the bias current increases to Ian. Especially during the period until YSR is selected, C8 also becomes High and the bias current is IEt+I
ss, so RD and RD' are rapidly discharged and Ql
, speeds up recovery of Ql'. As soon as YSR is selected, a signal potential difference appears on the collector sides of Ql and Ql'. Here C3 is Lo% before YSR is selected
It is desirable to return to I, because when the read amplifier 2 is turned on, the current of the read amplifier 2 is further added to the bias current, and the potential drop of R1 and R1' becomes too large, making the design difficult. Furthermore, I El, I 1!
Set x' because the current is small.

The Set' switch may be abolished and the signal may be applied for the entire period. FIG. 7 shows a bias current control method different from that shown in FIG. 6. This is shown in Figure 5 as I ex, I I! This corresponds to abolishing x and constantly streaming I Ele I ex'.

The bias current is IE1+Ipa only during the period from the operation period (CE: Low) until YSR is selected.
Since the current rEt is increased to a constant value during other periods including the standby period (CE: High), the current consumption during standby increases, but one circuit becomes simpler.

The embodiment shown in FIG. 8 realizes the functions shown in FIG. 5 and the timing shown in FIG. 6 using actual transistor connections. In this figure, the switch and current source are constructed using MOS transistors. The control signal C8 in FIG. 6 corresponds to C1.
It is made using a delay circuit (Delay) and an inverter. Va is a gate control voltage of a current source using a MOS transistor. The current value is adjusted by Va and the gate width and gate length of the MOS transistor. Current sources Iaz and Ie
x'IE8 and I1! s' has become common. This is effective in reducing the number of elements as well as in equipotentially setting RD and RD' since no read signal has yet appeared in D' when these currents flow. R1゜R1'
Clamping diodes Di and Di' are placed in parallel with. This is to prevent saturation of Ql and Ql'.II
VB is set to a potential level shifted by VBE from Vcc by a diode D2. In order to increase the driving ability for the subsequent circuit, the outputs so and so' are outputs of an emitter follower whose base inputs are PL and PL'. The emitter follower current is also controlled by C1 and an inverter to maintain a large current only during the operation period. By using this circuit, the original high-speed current sensing method can be achieved even when power supply noise occurs within the chip, and current consumption during standby can be suppressed.

Furthermore, the concept of bias current change in the current sensing method of the present invention can be applied to the case where a bipolar differential amplifier is used in addition to the case where a MOS transistor is used as the read differential amplifier 2 as shown in FIG.

At this time, a line connecting the collectors of a plurality of differential amplifiers becomes a read common data line and controls its bias current.

Also, there is a difference between the data line pairs! ! In addition to the No. 11 amplifier, the present invention can be applied to control the bias current of the output line when a differential amplifier is provided in a common data line pair.

Next, the configuration of the Y decoder circuit for generating the control signal YSR for the read differential amplifier 2 and the control signal YSW for the write transfer circuit 3 in FIGS. 1 and 2 will be described.

FIG. 9 is a circuit diagram of the embodiment, and FIG. 10 is an operation timing diagram thereof.

GE and WE are external inputs. A Y nm is a partial decoder signal generated through a Y-system address buffer and predecoder. The WCL signal is generated based on the WE large input and equally inputs to many Y decoders. When multiple inputs AYnm of the Y decoder are all )Ihigh, YSR is l(i
gh is selected. In the read (Read) cycle, the WCL signal remains low, so YSW is set to M5. M6
It is Low via . In a write cycle, YSW is high only during the period when the WCL signal is high.
becomes. nMOS, M5 is mainly used for starting up ysw, p
MO81M6 mainly contributes to the shutdown. On the other hand, in the Y decoder for valve selection, M4 is on, M5. Since M6 is off, YSR and YSW are both Lo regardless of the WCL signal.
It is w. - pair YSR and YSW may control only one column of data line pair, but since the size of the memory cell is generally smaller than the Y decoder, it is better to control a plurality of columns.

Although the embodiment of the present invention has been described above with respect to a DRAM, the present invention can be easily applied to other SRAMs, ROMs, and even bipolar RAMs using a current sensing method.

〔Effect of the invention〕

By using the common data line bias current control method of the present invention, even if power supply noise occurs within the chip, its influence on the readout speed can be suppressed, and the original effect of the current sensing method, which clamps the voltage using the bipolar common data line with large parasitic capacitance, can be maintained. You can take advantage of it. In particular, in DRAM, the amplification speed of the data line signal rewriting amplifier (circuit 6 in Figure 1) is slow;
The readout method in which direct detection is performed by circuit 2) in the figure is a decisive factor in increasing the speed, but since the signal amount at this time is small and the power supply noise is large, the effect of the present invention is particularly large. Furthermore, current consumption during the standby period can be kept small by bias current control.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment in a DRAM, FIG. 2 is a circuit diagram of a conventional example, FIG. 3 is an operation timing diagram of FIG. 1, and FIG. 4 is a diagram showing problems in the current sensing circuit. Figure 5 shows the bias current control method of the present invention, Figures 6 and 7.
8 is a circuit diagram of a specific embodiment of bias current control, FIG. 9 is a circuit diagram of an embodiment of a Y decoder, and FIG. 10 is a diagram of its operation waveforms. 1...Memory cell, 2...Differential amplifier for reading, 3
...Write transfer circuit, 4...Common data line pair load circuit, 5...Precharge circuit, 6...Rewrite amplifier, CE...Chip enable input, WE...
Write enable input, Xo”X-1Y o ”Y
--Address input. W...word line, D, D'...data line, RD,
RD'...Common data line for reading, WD, WD'...
・Common data line for writing, YSR... Column selection signal for reading.

Claims (1)

[Claims] 1. A MOS or bipolar reading differential amplifier that receives the data line signal as an input signal is provided for each data line pair to which a plurality of memory cells are connected, and the drain or collector is connected to the plurality of data line pairs. In a semiconductor memory in which columns are connected to form a common read data line pair, each common read data line pair is connected to the emitter of a bipolar transistor, a constant voltage is supplied to the base, and a load resistor is connected between the collector and the positive power supply. 1. A semiconductor memory characterized in that the value of a bias current flowing through the common read data line pair separately from the current from a read differential amplifier is changed in accordance with the operation timing of the memory. 2. The value of the bias current flowing through the common read data line pair is determined from the time when the memory transitions from the standby period to the operation period until the read differential amplifier is selected and the signal current begins to flow. A semiconductor memory characterized in that the current flows more than a period or a period in which a read differential amplifier is on. 3. For each data line pair to which a plurality of memory cells are connected, control the connection between the MOS or bipolar reading differential amplifier that uses this data line signal as an input signal, the write common data line pair, and the data line pair. has a write transfer circuit to
The selection signal for the read differential amplifier is generated by a two-stage configuration of a CMOS inverter and another input NAND circuit that takes the previous stage circuit output as input, and the selection signal for the write transfer circuit has its source connected to GND and its gate connected to the other input NAND circuit. The drain of the nMOS connected to the output of the circuit, the source of the pMOS connected to the common write drive line, and the gate connected to the output of the other input NAND circuit.
nM whose drain is connected to a common write drive line and whose gate is connected to the control signal line of the read differential amplifier.
A semiconductor memory characterized by having a column selection circuit that applies voltage from three connection points with the drain of an OS.