JPH02113754A - Coding modulation demodulation circuit - Google Patents

Abstract

PURPOSE:To increase a coding gain by obtaining a redundant bit required for coding through increase in a transmission speed without increasing a modulation signal point. CONSTITUTION:The title circuit consists of a speed conversion circuit 1, a coding circuit 2, an arrangement circuit 3 to signal space, a modulation circuit 4, a demodulation circuit 5, a decoding circuit 6, a speed conversion circuit 7, clock speed conversion circuits 8, 9 and a clock recovery circuit 10. Then the increase in the required transmission speed due to the redundant bit added through the coding is compensated not by the increase in the multi-value number but by the transmission speed. Thus, a large coding gain is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an encoding modulation/demodulation circuit, and particularly to an encoding modulation/demodulation circuit using a multidimensional code.

(Prior Art) Conventionally, in a multidimensional coded modulation system, m bits (m), 2.
, , ) can be converted into n bits (
n = 1.2. , , ) redundant bits are added (ma
n) bits, and a modulation method with a multilevel number of 2 man was used without changing the code speed (for example, in the literature, Yamanaka et al.
Maritime: Study of multidimensional trellis coding device in high-speed voice band modem, IT 87-23, Institute of Electronics, Information and Communication Engineers Information Theory Study Group, pp97102). A block diagram of this conventional multidimensional coded modulation is shown in FIG. In this figure, 1 is a multidimensional encoding circuit, 2 is a signal space placement circuit, 3 is a modulation circuit, 4 is a demodulation circuit, 5 is a decoding circuit, and 6 is a clock iTG generation circuit. - As an example, a configuration example of a convolutional encoding circuit (number of states: 16, encoding rate 3/4) for eight-dimensional trellis encoding is shown in FIG.

The coded modulation method combines error correction and modulation/demodulation techniques to encode each symbol in a way that maximizes the Euclidean distance in the signal space. It is possible to obtain a larger coding gain than error correction that is coded as follows.

(Problem to be Solved by the Invention) However, if m=3, which shows the signal space in FIG. As in the example of n=1, the number of multilevels increases from 16QAM to coded 32QAM, and the signal point interval becomes approximately 172, resulting in a required C/N of 3d.
This led to deterioration on the order of B, and the coding gain decreased accordingly. Another disadvantage is that as the number of multi-values increases, highly accurate hardware is required, making modem design difficult.

An object of the present invention is to solve the above-mentioned problem of the decrease in coding gain due to an increase in the number of multilevel values and the difficulty in realizing hardware, and to obtain a large coding gain.

(Means for Solving the Problem) The feature of the present invention for achieving the above object is that mbit/
In a multidimensional coding modulation/demodulation circuit that divides the 8 transmission stars of s (m is a natural number) and codes each symbol so that the Euclidean distance on the signal space between code words is maximized,
On the transmitting side, a signal with a code rate i/T consisting of an m-bit sequence (m = 1.2,...) is manually transmitted, and a code rate 1/T is generated by a (m-n) bit sequence (n is a natural number). T'(T'
−(m −n )/m・T) as an output signal;
The receiving side includes a multidimensional encoding circuit that outputs a series of signals, and a circuit that arranges the output of the encoding circuit so that the Euclidean distance between code words is maximized on the signal space. Clock speed 1/T by manually generating m-bit series signals
A decoding circuit that operates at a speed of
-n) An encoding modulation/demodulation circuit having a speed conversion circuit for converting a bit signal sequence into an m-hit signal sequence with a code rate of 1/T.

(Function) The present invention is characterized in that, in a multidimensional coding modulator/demodulator, a reduction in signal point spacing is prevented by not increasing the number of modulation levels, and as a result, a large coding gain is obtained.

In this coding modulation circuit, the increase in required transmission speed due to redundant bits added by coding is
This is compensated for by increasing the transmission speed rather than increasing the number of multilevel values. In the prior art, this was compensated for by increasing the number of multi-values, resulting in an increase in the signal point interval and an increase in the required CZN value.

According to the present invention, as the transmission speed increases, the noise bandwidth expands, but the deterioration of the required C7N value due to this is very slight, and is smaller than the amount of deterioration caused by increasing the number of multilevels, resulting in a large coding gain. It is something.

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which 1 is a speed conversion circuit, 2 is a multidimensional convolutional encoding circuit, 3 is a placement circuit in signal space, 4 is a modulation circuit, and 5 is a demodulation circuit. , 6 is a decoding circuit,
7 is a speed conversion circuit, 8.9 is a clock speed conversion circuit that becomes necessary due to speed conversion, and 10 is a clock regeneration circuit. For example, in this example 256QAM
When m=8 and n=1 using a modulation circuit, T and T' in the figure have a relationship of T'=7/8T. Consider an example in which a multidimensional convolutional encoder is used as an encoder and a Viterbi decoder is used as a decoder. First, on the transmitting side, the speed is converted from 8 bits/T to 7 bits/T'(T' - (m -
n)/m-T). Redundant bits are added to this signal sequence by a multidimensional convolutional code circuit, resulting in an output of 8 pins l-/T'. After this, Set, -partit, which takes into account the relationship between Euclidean distance and code, is added to the 256QAM signal space.
It passes through an optimal placement circuit called ion and is modulated. In addition, 5et-partition is the document 'G, I]ng
erboeck, ”(:hannej (:odin
g with Multjlevel/Phase Si
gnals”, IEEE IT, , jan1982
pp 55-57”. On the receiving side, the output of the two demodulation circuits is passed through a hitahi demodulation circuit to obtain a 7-hit/T' signal sequence. This is passed through a speed conversion circuit to 8 hits/T.
Obtain the demodulated code sequence. In this example, 8
Even if trellis coding is applied to the hit/T signal sequence, 25
It can be transmitted using 6QAM modulation.

(Effects of the Invention) As explained above, according to the present invention, encoding modulation and demodulation can be performed without increasing the number of modulation and demodulation values, so the distance between signal points does not decrease. This corresponds to a gain of 3 dB when n=1, and even considering the deterioration due to band expansion, it is possible to obtain a larger coding gain than conventional coded modulation. It also becomes easier to implement in hardware.

As an example, m=8. Consider the case where n=1.

In this case, the signal spatial arrangement is 256QAM according to the invention.
However, according to conventional coded modulation, M5 to 2"" Q
It will be 120AM. Table 1 shows a comparison of the coding gains between the two (simulation calculation results).

Table 1 Comparison of coding gain 8-dimensional, 16STATE, 3/4 convolutional code In this table, conventional coding 5]2QAM has a gain of 6.3dB due to Viterbi decoding, but the amount of deterioration due to halving the signal point spacing is 3d
B, the total is 3.3dB (BER=10
−' point).

- In Rikiki's invention, the transmission speed is increased 877 times, so although there is a deterioration of 0.6 dB due to the expansion of the noise band, there is no deterioration due to the reduction in the signal point interval, so a gain of 5.7 dB can be obtained in the end. As a result, a 2.4 dB larger gain can be obtained compared to the conventional encoding 5]2QAM method.

The coding gain effect explained above is obtained by increasing the transmission speed, not by increasing the redundant bits and modulation signal points necessary for encoding, and it depends on the size (absolute) of the modulation signal points. Needless to say, it does not depend on the value) or the physical shape of the signal space arrangement.

Therefore, this technology is applicable not only to numerically 2'-QAM (k: integer), but also to 2k-FSX and so-called SS-Q
AM (Stepped Square-QAM: Reference T, Ryu, et al., Astepped 5
square 256QAM for digital
radi.

system, , ICC86, pp46.6.1-
46.6.5. June 1986. It goes without saying that the present invention can be extended and used for all multidimensional coding modulation systems having a signal space arrangement such as ).

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an encoding modulation/demodulation circuit according to the present invention;
Fig. 2 is a block diagram of conventional multidimensional coded modulation, Fig. 3 is a configuration example of a multidimensional convolutional encoder, and Fig. 4 is a modulated signal space layout diagram. FIG. 6 is a diagram showing that the interval between points decreases (uncoded +60AM and encoded 32QAM). I: speed conversion circuit, 2: encoding circuit, 3: placement circuit in signal space, 4: modulation circuit, 5: demodulation circuit,
6: Decoding circuit, 7: Speed conversion circuit, 8.9: Clock speed conversion circuit, 10: Clock regeneration circuit.

Claims (1)

[Claims] A multidimensional coding modulation/demodulation circuit that has a transmission capacity of mbit/s (m is a natural number) and performs coding in symbol units so that the Euclidean distance on the signal space between code words is maximized. In the above, the transmitting side inputs a signal with a code rate of 1/T consisting of an m-bit sequence (m = 1, 2, ...), and a signal with a code rate of 1/T with an (m-n) bit sequence (n is a natural number). T'(T'=(m-
A speed conversion circuit that outputs a signal of n)/m・T), and outputs an m-bit sequence signal encoded by the speed conversion circuit output of an (m-n) bit sequence at a clock speed of 1/T'. The receiving side receives an m-bit sequence signal as input. a decoding circuit that operates at a clock speed of 1/T' and outputs a decoded signal of an (m-n) bit sequence;
An encoding modulation/demodulation circuit comprising a speed conversion circuit that converts an m-n) bit signal sequence into an m-bit signal sequence with a code rate of 1/T.